/**
 * this file is automatic generate by genregs.awk , Please do not edit it 
 * base files are ../ucode/register.h ../ucode/c_always_on_pointer.h ../ucode/pctl.h 
 * ../ucode/c_stb_define.h ../ucode/secure_apb.h from VLSI team
 */
#ifndef __MACH_MESON6_REG_ADDR_H_
#define __MACH_MESON6_REG_ADDR_H_
#define SECOND_DEMUX_OFFSET_0 0x50 	///../ucode/register.h
#define P_SECOND_DEMUX_OFFSET_0 		CBUS_REG_ADDR(SECOND_DEMUX_OFFSET_0) 	///../ucode/register.h
#define THIRD_DEMUX_OFFSET_0 0xa0 	///../ucode/register.h
#define P_THIRD_DEMUX_OFFSET_0 		CBUS_REG_ADDR(THIRD_DEMUX_OFFSET_0) 	///../ucode/register.h
#define STB_TOP_CONFIG 0x16f0 	///../ucode/register.h
#define P_STB_TOP_CONFIG 		CBUS_REG_ADDR(STB_TOP_CONFIG) 	///../ucode/register.h
#define TS_TOP_CONFIG 0x16f1 	///../ucode/register.h
#define P_TS_TOP_CONFIG 		CBUS_REG_ADDR(TS_TOP_CONFIG) 	///../ucode/register.h
#define TS_FILE_CONFIG 0x16f2 	///../ucode/register.h
#define P_TS_FILE_CONFIG 		CBUS_REG_ADDR(TS_FILE_CONFIG) 	///../ucode/register.h
#define TS_PL_PID_INDEX 0x16f3 	///../ucode/register.h
#define P_TS_PL_PID_INDEX 		CBUS_REG_ADDR(TS_PL_PID_INDEX) 	///../ucode/register.h
#define TS_PL_PID_DATA 0x16f4 	///../ucode/register.h
#define P_TS_PL_PID_DATA 		CBUS_REG_ADDR(TS_PL_PID_DATA) 	///../ucode/register.h
#define COMM_DESC_KEY0 0x16f5 	///../ucode/register.h
#define P_COMM_DESC_KEY0 		CBUS_REG_ADDR(COMM_DESC_KEY0) 	///../ucode/register.h
#define COMM_DESC_KEY1 0x16f6 	///../ucode/register.h
#define P_COMM_DESC_KEY1 		CBUS_REG_ADDR(COMM_DESC_KEY1) 	///../ucode/register.h
#define COMM_DESC_KEY_RW 0x16f7 	///../ucode/register.h
#define P_COMM_DESC_KEY_RW 		CBUS_REG_ADDR(COMM_DESC_KEY_RW) 	///../ucode/register.h
#define PREG_CTLREG0_ADDR 0x2000 	///../ucode/register.h
#define P_PREG_CTLREG0_ADDR 		CBUS_REG_ADDR(PREG_CTLREG0_ADDR) 	///../ucode/register.h
#define PREG_PAD_GPIO6_EN_N 0x2008 	///../ucode/register.h
#define P_PREG_PAD_GPIO6_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO6_EN_N) 	///../ucode/register.h
#define PREG_PAD_GPIO6_O 0x2009 	///../ucode/register.h
#define P_PREG_PAD_GPIO6_O 		CBUS_REG_ADDR(PREG_PAD_GPIO6_O) 	///../ucode/register.h
#define PREG_PAD_GPIO6_I 0x200a 	///../ucode/register.h
#define P_PREG_PAD_GPIO6_I 		CBUS_REG_ADDR(PREG_PAD_GPIO6_I) 	///../ucode/register.h
#define PREG_JTAG_GPIO_ADDR 0x200b 	///../ucode/register.h
#define P_PREG_JTAG_GPIO_ADDR 		CBUS_REG_ADDR(PREG_JTAG_GPIO_ADDR) 	///../ucode/register.h
#define PREG_PAD_GPIO0_EN_N 0x200c 	///../ucode/register.h
#define P_PREG_PAD_GPIO0_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO0_EN_N) 	///../ucode/register.h
#define PREG_PAD_GPIO0_O 0x200d 	///../ucode/register.h
#define P_PREG_PAD_GPIO0_O 		CBUS_REG_ADDR(PREG_PAD_GPIO0_O) 	///../ucode/register.h
#define PREG_PAD_GPIO0_I 0x200e 	///../ucode/register.h
#define P_PREG_PAD_GPIO0_I 		CBUS_REG_ADDR(PREG_PAD_GPIO0_I) 	///../ucode/register.h
#define PREG_PAD_GPIO1_EN_N 0x200f 	///../ucode/register.h
#define P_PREG_PAD_GPIO1_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO1_EN_N) 	///../ucode/register.h
#define PREG_PAD_GPIO1_O 0x2010 	///../ucode/register.h
#define P_PREG_PAD_GPIO1_O 		CBUS_REG_ADDR(PREG_PAD_GPIO1_O) 	///../ucode/register.h
#define PREG_PAD_GPIO1_I 0x2011 	///../ucode/register.h
#define P_PREG_PAD_GPIO1_I 		CBUS_REG_ADDR(PREG_PAD_GPIO1_I) 	///../ucode/register.h
#define PREG_PAD_GPIO2_EN_N 0x2012 	///../ucode/register.h
#define P_PREG_PAD_GPIO2_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO2_EN_N) 	///../ucode/register.h
#define PREG_PAD_GPIO2_O 0x2013 	///../ucode/register.h
#define P_PREG_PAD_GPIO2_O 		CBUS_REG_ADDR(PREG_PAD_GPIO2_O) 	///../ucode/register.h
#define PREG_PAD_GPIO2_I 0x2014 	///../ucode/register.h
#define P_PREG_PAD_GPIO2_I 		CBUS_REG_ADDR(PREG_PAD_GPIO2_I) 	///../ucode/register.h
#define PREG_PAD_GPIO3_EN_N 0x2015 	///../ucode/register.h
#define P_PREG_PAD_GPIO3_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO3_EN_N) 	///../ucode/register.h
#define PREG_PAD_GPIO3_O 0x2016 	///../ucode/register.h
#define P_PREG_PAD_GPIO3_O 		CBUS_REG_ADDR(PREG_PAD_GPIO3_O) 	///../ucode/register.h
#define PREG_PAD_GPIO3_I 0x2017 	///../ucode/register.h
#define P_PREG_PAD_GPIO3_I 		CBUS_REG_ADDR(PREG_PAD_GPIO3_I) 	///../ucode/register.h
#define PREG_PAD_GPIO4_EN_N 0x2018 	///../ucode/register.h
#define P_PREG_PAD_GPIO4_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO4_EN_N) 	///../ucode/register.h
#define PREG_PAD_GPIO4_O 0x2019 	///../ucode/register.h
#define P_PREG_PAD_GPIO4_O 		CBUS_REG_ADDR(PREG_PAD_GPIO4_O) 	///../ucode/register.h
#define PREG_PAD_GPIO4_I 0x201a 	///../ucode/register.h
#define P_PREG_PAD_GPIO4_I 		CBUS_REG_ADDR(PREG_PAD_GPIO4_I) 	///../ucode/register.h
#define PREG_PAD_GPIO5_EN_N 0x201b 	///../ucode/register.h
#define P_PREG_PAD_GPIO5_EN_N 		CBUS_REG_ADDR(PREG_PAD_GPIO5_EN_N) 	///../ucode/register.h
#define PREG_PAD_GPIO5_O 0x201c 	///../ucode/register.h
#define P_PREG_PAD_GPIO5_O 		CBUS_REG_ADDR(PREG_PAD_GPIO5_O) 	///../ucode/register.h
#define PREG_PAD_GPIO5_I 0x201d 	///../ucode/register.h
#define P_PREG_PAD_GPIO5_I 		CBUS_REG_ADDR(PREG_PAD_GPIO5_I) 	///../ucode/register.h
#define A9_CFG0 0x2020 	///../ucode/register.h
#define P_A9_CFG0 		CBUS_REG_ADDR(A9_CFG0) 	///../ucode/register.h
#define A9_CFG1 0x2021 	///../ucode/register.h
#define P_A9_CFG1 		CBUS_REG_ADDR(A9_CFG1) 	///../ucode/register.h
#define A9_CFG2 0x2022 	///../ucode/register.h
#define P_A9_CFG2 		CBUS_REG_ADDR(A9_CFG2) 	///../ucode/register.h
#define A9_PERIPH_BASE 0x2023 	///../ucode/register.h
#define P_A9_PERIPH_BASE 		CBUS_REG_ADDR(A9_PERIPH_BASE) 	///../ucode/register.h
#define A9_L2_REG_BASE 0x2024 	///../ucode/register.h
#define P_A9_L2_REG_BASE 		CBUS_REG_ADDR(A9_L2_REG_BASE) 	///../ucode/register.h
#define A9_L2_STATUS 0x2025 	///../ucode/register.h
#define P_A9_L2_STATUS 		CBUS_REG_ADDR(A9_L2_STATUS) 	///../ucode/register.h
#define A9_POR_CFG 0x2026 	///../ucode/register.h
#define P_A9_POR_CFG 		CBUS_REG_ADDR(A9_POR_CFG) 	///../ucode/register.h
#define MALI_IDLE_STAT 0x2027 	///../ucode/register.h
#define P_MALI_IDLE_STAT 		CBUS_REG_ADDR(MALI_IDLE_STAT) 	///../ucode/register.h
#define AXI_REG_EN 0x2028 	///../ucode/register.h
#define P_AXI_REG_EN 		CBUS_REG_ADDR(AXI_REG_EN) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_0 0x202c 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_0 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_0) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_1 0x202d 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_1 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_1) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_2 0x202e 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_2 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_2) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_3 0x202f 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_3 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_3) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_4 0x2030 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_4 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_4) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_5 0x2031 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_5 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_5) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_6 0x2032 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_6 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_6) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_7 0x2033 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_7 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_7) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_8 0x2034 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_8 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_8) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_9 0x2035 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_9 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_9) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_10 0x2036 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_10 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_10) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_11 0x2037 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_11 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_11) 	///../ucode/register.h
#define PERIPHS_PIN_MUX_12 0x2038 	///../ucode/register.h
#define P_PERIPHS_PIN_MUX_12 		CBUS_REG_ADDR(PERIPHS_PIN_MUX_12) 	///../ucode/register.h
#define PAD_PULL_UP_REG6 0x2039 	///../ucode/register.h
#define P_PAD_PULL_UP_REG6 		CBUS_REG_ADDR(PAD_PULL_UP_REG6) 	///../ucode/register.h
#define PAD_PULL_UP_REG0 0x203a 	///../ucode/register.h
#define P_PAD_PULL_UP_REG0 		CBUS_REG_ADDR(PAD_PULL_UP_REG0) 	///../ucode/register.h
#define PAD_PULL_UP_REG1 0x203b 	///../ucode/register.h
#define P_PAD_PULL_UP_REG1 		CBUS_REG_ADDR(PAD_PULL_UP_REG1) 	///../ucode/register.h
#define PAD_PULL_UP_REG2 0x203c 	///../ucode/register.h
#define P_PAD_PULL_UP_REG2 		CBUS_REG_ADDR(PAD_PULL_UP_REG2) 	///../ucode/register.h
#define PAD_PULL_UP_REG3 0x203d 	///../ucode/register.h
#define P_PAD_PULL_UP_REG3 		CBUS_REG_ADDR(PAD_PULL_UP_REG3) 	///../ucode/register.h
#define PAD_PULL_UP_REG4 0x203e 	///../ucode/register.h
#define P_PAD_PULL_UP_REG4 		CBUS_REG_ADDR(PAD_PULL_UP_REG4) 	///../ucode/register.h
#define PAD_PULL_UP_REG5 0x203f 	///../ucode/register.h
#define P_PAD_PULL_UP_REG5 		CBUS_REG_ADDR(PAD_PULL_UP_REG5) 	///../ucode/register.h
#define RAND64_ADDR0 0x2040 	///../ucode/register.h
#define P_RAND64_ADDR0 		CBUS_REG_ADDR(RAND64_ADDR0) 	///../ucode/register.h
#define RAND64_ADDR1 0x2041 	///../ucode/register.h
#define P_RAND64_ADDR1 		CBUS_REG_ADDR(RAND64_ADDR1) 	///../ucode/register.h
#define PREG_ETHERNET_ADDR0 0x2042 	///../ucode/register.h
#define P_PREG_ETHERNET_ADDR0 		CBUS_REG_ADDR(PREG_ETHERNET_ADDR0) 	///../ucode/register.h
#define PREG_AM_ANALOG_ADDR 0x2043 	///../ucode/register.h
#define P_PREG_AM_ANALOG_ADDR 		CBUS_REG_ADDR(PREG_AM_ANALOG_ADDR) 	///../ucode/register.h
#define PREG_MALI_BYTE_CNTL 0x2044 	///../ucode/register.h
#define P_PREG_MALI_BYTE_CNTL 		CBUS_REG_ADDR(PREG_MALI_BYTE_CNTL) 	///../ucode/register.h
#define PREG_WIFI_CNTL 0x2045 	///../ucode/register.h
#define P_PREG_WIFI_CNTL 		CBUS_REG_ADDR(PREG_WIFI_CNTL) 	///../ucode/register.h
#define AM_ANALOG_TOP_REG0 0x206e 	///../ucode/register.h
#define P_AM_ANALOG_TOP_REG0 		CBUS_REG_ADDR(AM_ANALOG_TOP_REG0) 	///../ucode/register.h
#define AM_ANALOG_TOP_REG1 0x206f 	///../ucode/register.h
#define P_AM_ANALOG_TOP_REG1 		CBUS_REG_ADDR(AM_ANALOG_TOP_REG1) 	///../ucode/register.h
#define PREG_STICKY_REG0 0x207c 	///../ucode/register.h
#define P_PREG_STICKY_REG0 		CBUS_REG_ADDR(PREG_STICKY_REG0) 	///../ucode/register.h
#define PREG_STICKY_REG1 0x207d 	///../ucode/register.h
#define P_PREG_STICKY_REG1 		CBUS_REG_ADDR(PREG_STICKY_REG1) 	///../ucode/register.h
#define PREG_MV_REG 0x207e 	///../ucode/register.h
#define P_PREG_MV_REG 		CBUS_REG_ADDR(PREG_MV_REG) 	///../ucode/register.h
#define AM_RING_OSC_REG0 0x207f 	///../ucode/register.h
#define P_AM_RING_OSC_REG0 		CBUS_REG_ADDR(AM_RING_OSC_REG0) 	///../ucode/register.h
#define USB_ADDR0 0x2100 	///../ucode/register.h
#define P_USB_ADDR0 		CBUS_REG_ADDR(USB_ADDR0) 	///../ucode/register.h
#define USB_ADDR1 0x2101 	///../ucode/register.h
#define P_USB_ADDR1 		CBUS_REG_ADDR(USB_ADDR1) 	///../ucode/register.h
#define USB_ADDR2 0x2102 	///../ucode/register.h
#define P_USB_ADDR2 		CBUS_REG_ADDR(USB_ADDR2) 	///../ucode/register.h
#define USB_ADDR3 0x2103 	///../ucode/register.h
#define P_USB_ADDR3 		CBUS_REG_ADDR(USB_ADDR3) 	///../ucode/register.h
#define USB_ADDR4 0x2104 	///../ucode/register.h
#define P_USB_ADDR4 		CBUS_REG_ADDR(USB_ADDR4) 	///../ucode/register.h
#define USB_ADDR5 0x2105 	///../ucode/register.h
#define P_USB_ADDR5 		CBUS_REG_ADDR(USB_ADDR5) 	///../ucode/register.h
#define USB_ADDR6 0x2106 	///../ucode/register.h
#define P_USB_ADDR6 		CBUS_REG_ADDR(USB_ADDR6) 	///../ucode/register.h
#define USB_ADDR7 0x2107 	///../ucode/register.h
#define P_USB_ADDR7 		CBUS_REG_ADDR(USB_ADDR7) 	///../ucode/register.h
#define USB_ADDR8 0x2108 	///../ucode/register.h
#define P_USB_ADDR8 		CBUS_REG_ADDR(USB_ADDR8) 	///../ucode/register.h
#define USB_ADDR9 0x2109 	///../ucode/register.h
#define P_USB_ADDR9 		CBUS_REG_ADDR(USB_ADDR9) 	///../ucode/register.h
#define USB_ADDR10 0x210a 	///../ucode/register.h
#define P_USB_ADDR10 		CBUS_REG_ADDR(USB_ADDR10) 	///../ucode/register.h
#define USB_ADDR11 0x210b 	///../ucode/register.h
#define P_USB_ADDR11 		CBUS_REG_ADDR(USB_ADDR11) 	///../ucode/register.h
#define USB_ADDR12 0x210c 	///../ucode/register.h
#define P_USB_ADDR12 		CBUS_REG_ADDR(USB_ADDR12) 	///../ucode/register.h
#define USB_ADDR13 0x210d 	///../ucode/register.h
#define P_USB_ADDR13 		CBUS_REG_ADDR(USB_ADDR13) 	///../ucode/register.h
#define USB_ADDR14 0x210e 	///../ucode/register.h
#define P_USB_ADDR14 		CBUS_REG_ADDR(USB_ADDR14) 	///../ucode/register.h
#define USB_ADDR15 0x210f 	///../ucode/register.h
#define P_USB_ADDR15 		CBUS_REG_ADDR(USB_ADDR15) 	///../ucode/register.h
#define SMARTCARD_REG0 0x2110 	///../ucode/register.h
#define P_SMARTCARD_REG0 		CBUS_REG_ADDR(SMARTCARD_REG0) 	///../ucode/register.h
#define SMARTCARD_REG1 0x2111 	///../ucode/register.h
#define P_SMARTCARD_REG1 		CBUS_REG_ADDR(SMARTCARD_REG1) 	///../ucode/register.h
#define SMARTCARD_REG2 0x2112 	///../ucode/register.h
#define P_SMARTCARD_REG2 		CBUS_REG_ADDR(SMARTCARD_REG2) 	///../ucode/register.h
#define SMARTCARD_STATUS 0x2113 	///../ucode/register.h
#define P_SMARTCARD_STATUS 		CBUS_REG_ADDR(SMARTCARD_STATUS) 	///../ucode/register.h
#define SMARTCARD_INTR 0x2114 	///../ucode/register.h
#define P_SMARTCARD_INTR 		CBUS_REG_ADDR(SMARTCARD_INTR) 	///../ucode/register.h
#define SMARTCARD_REG5 0x2115 	///../ucode/register.h
#define P_SMARTCARD_REG5 		CBUS_REG_ADDR(SMARTCARD_REG5) 	///../ucode/register.h
#define SMARTCARD_REG6 0x2116 	///../ucode/register.h
#define P_SMARTCARD_REG6 		CBUS_REG_ADDR(SMARTCARD_REG6) 	///../ucode/register.h
#define SMARTCARD_FIFO 0x2117 	///../ucode/register.h
#define P_SMARTCARD_FIFO 		CBUS_REG_ADDR(SMARTCARD_FIFO) 	///../ucode/register.h
#define IR_DEC_LDR_ACTIVE 0x2120 	///../ucode/register.h
#define P_IR_DEC_LDR_ACTIVE 		CBUS_REG_ADDR(IR_DEC_LDR_ACTIVE) 	///../ucode/register.h
#define IR_DEC_LDR_IDLE 0x2121 	///../ucode/register.h
#define P_IR_DEC_LDR_IDLE 		CBUS_REG_ADDR(IR_DEC_LDR_IDLE) 	///../ucode/register.h
#define IR_DEC_LDR_REPEAT 0x2122 	///../ucode/register.h
#define P_IR_DEC_LDR_REPEAT 		CBUS_REG_ADDR(IR_DEC_LDR_REPEAT) 	///../ucode/register.h
#define IR_DEC_BIT_0 0x2123 	///../ucode/register.h
#define P_IR_DEC_BIT_0 		CBUS_REG_ADDR(IR_DEC_BIT_0) 	///../ucode/register.h
#define IR_DEC_REG0 0x2124 	///../ucode/register.h
#define P_IR_DEC_REG0 		CBUS_REG_ADDR(IR_DEC_REG0) 	///../ucode/register.h
#define IR_DEC_FRAME 0x2125 	///../ucode/register.h
#define P_IR_DEC_FRAME 		CBUS_REG_ADDR(IR_DEC_FRAME) 	///../ucode/register.h
#define IR_DEC_STATUS 0x2126 	///../ucode/register.h
#define P_IR_DEC_STATUS 		CBUS_REG_ADDR(IR_DEC_STATUS) 	///../ucode/register.h
#define IR_DEC_REG1 0x2127 	///../ucode/register.h
#define P_IR_DEC_REG1 		CBUS_REG_ADDR(IR_DEC_REG1) 	///../ucode/register.h
#define DEMOD_ADC_SAMPLING 0x212d 	///../ucode/register.h
#define P_DEMOD_ADC_SAMPLING 		CBUS_REG_ADDR(DEMOD_ADC_SAMPLING) 	///../ucode/register.h
#define UART0_WFIFO 0x2130 	///../ucode/register.h
#define P_UART0_WFIFO 		CBUS_REG_ADDR(UART0_WFIFO) 	///../ucode/register.h
#define UART0_RFIFO 0x2131 	///../ucode/register.h
#define P_UART0_RFIFO 		CBUS_REG_ADDR(UART0_RFIFO) 	///../ucode/register.h
#define UART0_CONTROL 0x2132 	///../ucode/register.h
#define P_UART0_CONTROL 		CBUS_REG_ADDR(UART0_CONTROL) 	///../ucode/register.h
#define UART0_STATUS 0x2133 	///../ucode/register.h
#define P_UART0_STATUS 		CBUS_REG_ADDR(UART0_STATUS) 	///../ucode/register.h
#define UART0_MISC 0x2134 	///../ucode/register.h
#define P_UART0_MISC 		CBUS_REG_ADDR(UART0_MISC) 	///../ucode/register.h
#define UART0_REG5 0x2135 	///../ucode/register.h
#define P_UART0_REG5 		CBUS_REG_ADDR(UART0_REG5) 	///../ucode/register.h
#define UART1_WFIFO 0x2137 	///../ucode/register.h
#define P_UART1_WFIFO 		CBUS_REG_ADDR(UART1_WFIFO) 	///../ucode/register.h
#define UART1_RFIFO 0x2138 	///../ucode/register.h
#define P_UART1_RFIFO 		CBUS_REG_ADDR(UART1_RFIFO) 	///../ucode/register.h
#define UART1_CONTROL 0x2139 	///../ucode/register.h
#define P_UART1_CONTROL 		CBUS_REG_ADDR(UART1_CONTROL) 	///../ucode/register.h
#define UART1_STATUS 0x213a 	///../ucode/register.h
#define P_UART1_STATUS 		CBUS_REG_ADDR(UART1_STATUS) 	///../ucode/register.h
#define UART1_MISC 0x213b 	///../ucode/register.h
#define P_UART1_MISC 		CBUS_REG_ADDR(UART1_MISC) 	///../ucode/register.h
#define UART1_REG5 0x213c 	///../ucode/register.h
#define P_UART1_REG5 		CBUS_REG_ADDR(UART1_REG5) 	///../ucode/register.h
#define I2C_M_0_CONTROL_REG 0x2140 	///../ucode/register.h
#define P_I2C_M_0_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_0_CONTROL_REG) 	///../ucode/register.h
#define I2C_M_0_SLAVE_ADDR 0x2141 	///../ucode/register.h
#define P_I2C_M_0_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_0_SLAVE_ADDR) 	///../ucode/register.h
#define I2C_M_0_TOKEN_LIST0 0x2142 	///../ucode/register.h
#define P_I2C_M_0_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST0) 	///../ucode/register.h
#define I2C_M_0_TOKEN_LIST1 0x2143 	///../ucode/register.h
#define P_I2C_M_0_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_0_TOKEN_LIST1) 	///../ucode/register.h
#define I2C_M_0_WDATA_REG0 0x2144 	///../ucode/register.h
#define P_I2C_M_0_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_0_WDATA_REG0) 	///../ucode/register.h
#define I2C_M_0_WDATA_REG1 0x2145 	///../ucode/register.h
#define P_I2C_M_0_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_0_WDATA_REG1) 	///../ucode/register.h
#define I2C_M_0_RDATA_REG0 0x2146 	///../ucode/register.h
#define P_I2C_M_0_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_0_RDATA_REG0) 	///../ucode/register.h
#define I2C_M_0_RDATA_REG1 0x2147 	///../ucode/register.h
#define P_I2C_M_0_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_0_RDATA_REG1) 	///../ucode/register.h
#define I2C_S_CONTROL_REG 0x2150 	///../ucode/register.h
#define P_I2C_S_CONTROL_REG 		CBUS_REG_ADDR(I2C_S_CONTROL_REG) 	///../ucode/register.h
#define I2C_S_SEND_REG 0x2151 	///../ucode/register.h
#define P_I2C_S_SEND_REG 		CBUS_REG_ADDR(I2C_S_SEND_REG) 	///../ucode/register.h
#define I2C_S_RECV_REG 0x2152 	///../ucode/register.h
#define P_I2C_S_RECV_REG 		CBUS_REG_ADDR(I2C_S_RECV_REG) 	///../ucode/register.h
#define I2C_S_CNTL1_REG 0x2153 	///../ucode/register.h
#define P_I2C_S_CNTL1_REG 		CBUS_REG_ADDR(I2C_S_CNTL1_REG) 	///../ucode/register.h
#define PWM_PWM_A 0x2154 	///../ucode/register.h
#define P_PWM_PWM_A 		CBUS_REG_ADDR(PWM_PWM_A) 	///../ucode/register.h
#define PWM_PWM_B 0x2155 	///../ucode/register.h
#define P_PWM_PWM_B 		CBUS_REG_ADDR(PWM_PWM_B) 	///../ucode/register.h
#define PWM_MISC_REG_AB 0x2156 	///../ucode/register.h
#define P_PWM_MISC_REG_AB 		CBUS_REG_ADDR(PWM_MISC_REG_AB) 	///../ucode/register.h
#define PWM_DELTA_SIGMA_AB 0x2157 	///../ucode/register.h
#define P_PWM_DELTA_SIGMA_AB 		CBUS_REG_ADDR(PWM_DELTA_SIGMA_AB) 	///../ucode/register.h
#define ATAPI_IDEREG0 0x2160 	///../ucode/register.h
#define P_ATAPI_IDEREG0 		CBUS_REG_ADDR(ATAPI_IDEREG0) 	///../ucode/register.h
#define ATAPI_IDEREG1 0x2161 	///../ucode/register.h
#define P_ATAPI_IDEREG1 		CBUS_REG_ADDR(ATAPI_IDEREG1) 	///../ucode/register.h
#define ATAPI_IDEREG2 0x2162 	///../ucode/register.h
#define P_ATAPI_IDEREG2 		CBUS_REG_ADDR(ATAPI_IDEREG2) 	///../ucode/register.h
#define ATAPI_CYCTIME 0x2163 	///../ucode/register.h
#define P_ATAPI_CYCTIME 		CBUS_REG_ADDR(ATAPI_CYCTIME) 	///../ucode/register.h
#define ATAPI_IDETIME 0x2164 	///../ucode/register.h
#define P_ATAPI_IDETIME 		CBUS_REG_ADDR(ATAPI_IDETIME) 	///../ucode/register.h
#define ATAPI_PIO_TIMING 0x2165 	///../ucode/register.h
#define P_ATAPI_PIO_TIMING 		CBUS_REG_ADDR(ATAPI_PIO_TIMING) 	///../ucode/register.h
#define ATAPI_TABLE_ADD_REG 0x2166 	///../ucode/register.h
#define P_ATAPI_TABLE_ADD_REG 		CBUS_REG_ADDR(ATAPI_TABLE_ADD_REG) 	///../ucode/register.h
#define ATAPI_IDEREG3 0x2167 	///../ucode/register.h
#define P_ATAPI_IDEREG3 		CBUS_REG_ADDR(ATAPI_IDEREG3) 	///../ucode/register.h
#define ATAPI_UDMA_REG0 0x2168 	///../ucode/register.h
#define P_ATAPI_UDMA_REG0 		CBUS_REG_ADDR(ATAPI_UDMA_REG0) 	///../ucode/register.h
#define ATAPI_UDMA_REG1 0x2169 	///../ucode/register.h
#define P_ATAPI_UDMA_REG1 		CBUS_REG_ADDR(ATAPI_UDMA_REG1) 	///../ucode/register.h
#define TRANS_PWMA_REG0 0x2170 	///../ucode/register.h
#define P_TRANS_PWMA_REG0 		CBUS_REG_ADDR(TRANS_PWMA_REG0) 	///../ucode/register.h
#define TRANS_PWMA_REG1 0x2171 	///../ucode/register.h
#define P_TRANS_PWMA_REG1 		CBUS_REG_ADDR(TRANS_PWMA_REG1) 	///../ucode/register.h
#define TRANS_PWMA_MUX0 0x2172 	///../ucode/register.h
#define P_TRANS_PWMA_MUX0 		CBUS_REG_ADDR(TRANS_PWMA_MUX0) 	///../ucode/register.h
#define TRANS_PWMA_MUX1 0x2173 	///../ucode/register.h
#define P_TRANS_PWMA_MUX1 		CBUS_REG_ADDR(TRANS_PWMA_MUX1) 	///../ucode/register.h
#define TRANS_PWMA_MUX2 0x2174 	///../ucode/register.h
#define P_TRANS_PWMA_MUX2 		CBUS_REG_ADDR(TRANS_PWMA_MUX2) 	///../ucode/register.h
#define TRANS_PWMA_MUX3 0x2175 	///../ucode/register.h
#define P_TRANS_PWMA_MUX3 		CBUS_REG_ADDR(TRANS_PWMA_MUX3) 	///../ucode/register.h
#define TRANS_PWMA_MUX4 0x2176 	///../ucode/register.h
#define P_TRANS_PWMA_MUX4 		CBUS_REG_ADDR(TRANS_PWMA_MUX4) 	///../ucode/register.h
#define TRANS_PWMA_MUX5 0x2177 	///../ucode/register.h
#define P_TRANS_PWMA_MUX5 		CBUS_REG_ADDR(TRANS_PWMA_MUX5) 	///../ucode/register.h
#define TRANS_PWMB_REG0 0x2178 	///../ucode/register.h
#define P_TRANS_PWMB_REG0 		CBUS_REG_ADDR(TRANS_PWMB_REG0) 	///../ucode/register.h
#define TRANS_PWMB_REG1 0x2179 	///../ucode/register.h
#define P_TRANS_PWMB_REG1 		CBUS_REG_ADDR(TRANS_PWMB_REG1) 	///../ucode/register.h
#define TRANS_PWMB_MUX0 0x217a 	///../ucode/register.h
#define P_TRANS_PWMB_MUX0 		CBUS_REG_ADDR(TRANS_PWMB_MUX0) 	///../ucode/register.h
#define TRANS_PWMB_MUX1 0x217b 	///../ucode/register.h
#define P_TRANS_PWMB_MUX1 		CBUS_REG_ADDR(TRANS_PWMB_MUX1) 	///../ucode/register.h
#define TRANS_PWMB_MUX2 0x217c 	///../ucode/register.h
#define P_TRANS_PWMB_MUX2 		CBUS_REG_ADDR(TRANS_PWMB_MUX2) 	///../ucode/register.h
#define TRANS_PWMB_MUX3 0x217d 	///../ucode/register.h
#define P_TRANS_PWMB_MUX3 		CBUS_REG_ADDR(TRANS_PWMB_MUX3) 	///../ucode/register.h
#define TRANS_PWMB_MUX4 0x217e 	///../ucode/register.h
#define P_TRANS_PWMB_MUX4 		CBUS_REG_ADDR(TRANS_PWMB_MUX4) 	///../ucode/register.h
#define TRANS_PWMB_MUX5 0x217f 	///../ucode/register.h
#define P_TRANS_PWMB_MUX5 		CBUS_REG_ADDR(TRANS_PWMB_MUX5) 	///../ucode/register.h
#define NAND_START 0x2180 	///../ucode/register.h
#define P_NAND_START 		CBUS_REG_ADDR(NAND_START) 	///../ucode/register.h
#define NAND_ADR_CMD 0x218a 	///../ucode/register.h
#define P_NAND_ADR_CMD 		CBUS_REG_ADDR(NAND_ADR_CMD) 	///../ucode/register.h
#define NAND_ADR_STS 0x218b 	///../ucode/register.h
#define P_NAND_ADR_STS 		CBUS_REG_ADDR(NAND_ADR_STS) 	///../ucode/register.h
#define NAND_END 0x218f 	///../ucode/register.h
#define P_NAND_END 		CBUS_REG_ADDR(NAND_END) 	///../ucode/register.h
#define PWM_PWM_C 0x2194 	///../ucode/register.h
#define P_PWM_PWM_C 		CBUS_REG_ADDR(PWM_PWM_C) 	///../ucode/register.h
#define PWM_PWM_D 0x2195 	///../ucode/register.h
#define P_PWM_PWM_D 		CBUS_REG_ADDR(PWM_PWM_D) 	///../ucode/register.h
#define PWM_MISC_REG_CD 0x2196 	///../ucode/register.h
#define P_PWM_MISC_REG_CD 		CBUS_REG_ADDR(PWM_MISC_REG_CD) 	///../ucode/register.h
#define PWM_DELTA_SIGMA_CD 0x2197 	///../ucode/register.h
#define P_PWM_DELTA_SIGMA_CD 		CBUS_REG_ADDR(PWM_DELTA_SIGMA_CD) 	///../ucode/register.h
#define SAR_ADC_REG0 0x21a0 	///../ucode/register.h
#define P_SAR_ADC_REG0 		CBUS_REG_ADDR(SAR_ADC_REG0) 	///../ucode/register.h
#define SAR_ADC_CHAN_LIST 0x21a1 	///../ucode/register.h
#define P_SAR_ADC_CHAN_LIST 		CBUS_REG_ADDR(SAR_ADC_CHAN_LIST) 	///../ucode/register.h
#define SAR_ADC_AVG_CNTL 0x21a2 	///../ucode/register.h
#define P_SAR_ADC_AVG_CNTL 		CBUS_REG_ADDR(SAR_ADC_AVG_CNTL) 	///../ucode/register.h
#define SAR_ADC_REG3 0x21a3 	///../ucode/register.h
#define P_SAR_ADC_REG3 		CBUS_REG_ADDR(SAR_ADC_REG3) 	///../ucode/register.h
#define SAR_ADC_DELAY 0x21a4 	///../ucode/register.h
#define P_SAR_ADC_DELAY 		CBUS_REG_ADDR(SAR_ADC_DELAY) 	///../ucode/register.h
#define SAR_ADC_LAST_RD 0x21a5 	///../ucode/register.h
#define P_SAR_ADC_LAST_RD 		CBUS_REG_ADDR(SAR_ADC_LAST_RD) 	///../ucode/register.h
#define SAR_ADC_FIFO_RD 0x21a6 	///../ucode/register.h
#define P_SAR_ADC_FIFO_RD 		CBUS_REG_ADDR(SAR_ADC_FIFO_RD) 	///../ucode/register.h
#define SAR_ADC_AUX_SW 0x21a7 	///../ucode/register.h
#define P_SAR_ADC_AUX_SW 		CBUS_REG_ADDR(SAR_ADC_AUX_SW) 	///../ucode/register.h
#define SAR_ADC_CHAN_10_SW 0x21a8 	///../ucode/register.h
#define P_SAR_ADC_CHAN_10_SW 		CBUS_REG_ADDR(SAR_ADC_CHAN_10_SW) 	///../ucode/register.h
#define SAR_ADC_DETECT_IDLE_SW 0x21a9 	///../ucode/register.h
#define P_SAR_ADC_DETECT_IDLE_SW 		CBUS_REG_ADDR(SAR_ADC_DETECT_IDLE_SW) 	///../ucode/register.h
#define SAR_ADC_DELTA_10 0x21aa 	///../ucode/register.h
#define P_SAR_ADC_DELTA_10 		CBUS_REG_ADDR(SAR_ADC_DELTA_10) 	///../ucode/register.h
#define CTOUCH_REG0 0x21b0 	///../ucode/register.h
#define P_CTOUCH_REG0 		CBUS_REG_ADDR(CTOUCH_REG0) 	///../ucode/register.h
#define CTOUCH_REG1 0x21b1 	///../ucode/register.h
#define P_CTOUCH_REG1 		CBUS_REG_ADDR(CTOUCH_REG1) 	///../ucode/register.h
#define CTOUCH_FIFO 0x21b2 	///../ucode/register.h
#define P_CTOUCH_FIFO 		CBUS_REG_ADDR(CTOUCH_FIFO) 	///../ucode/register.h
#define CTOUCH_REG3 0x21b3 	///../ucode/register.h
#define P_CTOUCH_REG3 		CBUS_REG_ADDR(CTOUCH_REG3) 	///../ucode/register.h
#define CTOUCH_INIT_CLK0 0x21b4 	///../ucode/register.h
#define P_CTOUCH_INIT_CLK0 		CBUS_REG_ADDR(CTOUCH_INIT_CLK0) 	///../ucode/register.h
#define CTOUCH_INIT_CLK1 0x21b5 	///../ucode/register.h
#define P_CTOUCH_INIT_CLK1 		CBUS_REG_ADDR(CTOUCH_INIT_CLK1) 	///../ucode/register.h
#define CTOUCH_REG6 0x21b6 	///../ucode/register.h
#define P_CTOUCH_REG6 		CBUS_REG_ADDR(CTOUCH_REG6) 	///../ucode/register.h
#define CTOUCH_GND_SW_MASK 0x21b7 	///../ucode/register.h
#define P_CTOUCH_GND_SW_MASK 		CBUS_REG_ADDR(CTOUCH_GND_SW_MASK) 	///../ucode/register.h
#define CTOUCH_MSR_TB_SEL 0x21b8 	///../ucode/register.h
#define P_CTOUCH_MSR_TB_SEL 		CBUS_REG_ADDR(CTOUCH_MSR_TB_SEL) 	///../ucode/register.h
#define CTOUCH_CAP_THRESH0 0x21b9 	///../ucode/register.h
#define P_CTOUCH_CAP_THRESH0 		CBUS_REG_ADDR(CTOUCH_CAP_THRESH0) 	///../ucode/register.h
#define CTOUCH_CAP_THRESH1 0x21ba 	///../ucode/register.h
#define P_CTOUCH_CAP_THRESH1 		CBUS_REG_ADDR(CTOUCH_CAP_THRESH1) 	///../ucode/register.h
#define CTOUCH_CHAN_LIST0 0x21bb 	///../ucode/register.h
#define P_CTOUCH_CHAN_LIST0 		CBUS_REG_ADDR(CTOUCH_CHAN_LIST0) 	///../ucode/register.h
#define CTOUCH_CHAN_LIST1 0x21bc 	///../ucode/register.h
#define P_CTOUCH_CHAN_LIST1 		CBUS_REG_ADDR(CTOUCH_CHAN_LIST1) 	///../ucode/register.h
#define CTOUCH_MSR_TB0 0x21bd 	///../ucode/register.h
#define P_CTOUCH_MSR_TB0 		CBUS_REG_ADDR(CTOUCH_MSR_TB0) 	///../ucode/register.h
#define CTOUCH_MSR_TB1 0x21be 	///../ucode/register.h
#define P_CTOUCH_MSR_TB1 		CBUS_REG_ADDR(CTOUCH_MSR_TB1) 	///../ucode/register.h
#define CTOUCH_REG15 0x21bf 	///../ucode/register.h
#define P_CTOUCH_REG15 		CBUS_REG_ADDR(CTOUCH_REG15) 	///../ucode/register.h
#define UART2_WFIFO 0x21c0 	///../ucode/register.h
#define P_UART2_WFIFO 		CBUS_REG_ADDR(UART2_WFIFO) 	///../ucode/register.h
#define UART2_RFIFO 0x21c1 	///../ucode/register.h
#define P_UART2_RFIFO 		CBUS_REG_ADDR(UART2_RFIFO) 	///../ucode/register.h
#define UART2_CONTROL 0x21c2 	///../ucode/register.h
#define P_UART2_CONTROL 		CBUS_REG_ADDR(UART2_CONTROL) 	///../ucode/register.h
#define UART2_STATUS 0x21c3 	///../ucode/register.h
#define P_UART2_STATUS 		CBUS_REG_ADDR(UART2_STATUS) 	///../ucode/register.h
#define UART2_MISC 0x21c4 	///../ucode/register.h
#define P_UART2_MISC 		CBUS_REG_ADDR(UART2_MISC) 	///../ucode/register.h
#define UART2_REG5 0x21c5 	///../ucode/register.h
#define P_UART2_REG5 		CBUS_REG_ADDR(UART2_REG5) 	///../ucode/register.h
#define UART3_WFIFO 0x21c8 	///../ucode/register.h
#define P_UART3_WFIFO 		CBUS_REG_ADDR(UART3_WFIFO) 	///../ucode/register.h
#define UART3_RFIFO 0x21c9 	///../ucode/register.h
#define P_UART3_RFIFO 		CBUS_REG_ADDR(UART3_RFIFO) 	///../ucode/register.h
#define UART3_CONTROL 0x21ca 	///../ucode/register.h
#define P_UART3_CONTROL 		CBUS_REG_ADDR(UART3_CONTROL) 	///../ucode/register.h
#define UART3_STATUS 0x21cb 	///../ucode/register.h
#define P_UART3_STATUS 		CBUS_REG_ADDR(UART3_STATUS) 	///../ucode/register.h
#define UART3_MISC 0x21cc 	///../ucode/register.h
#define P_UART3_MISC 		CBUS_REG_ADDR(UART3_MISC) 	///../ucode/register.h
#define UART3_REG5 0x21cd 	///../ucode/register.h
#define P_UART3_REG5 		CBUS_REG_ADDR(UART3_REG5) 	///../ucode/register.h
#define RTC_ADDR0 0x21d0 	///../ucode/register.h
#define P_RTC_ADDR0 		CBUS_REG_ADDR(RTC_ADDR0) 	///../ucode/register.h
#define RTC_ADDR1 0x21d1 	///../ucode/register.h
#define P_RTC_ADDR1 		CBUS_REG_ADDR(RTC_ADDR1) 	///../ucode/register.h
#define RTC_ADDR2 0x21d2 	///../ucode/register.h
#define P_RTC_ADDR2 		CBUS_REG_ADDR(RTC_ADDR2) 	///../ucode/register.h
#define RTC_ADDR3 0x21d3 	///../ucode/register.h
#define P_RTC_ADDR3 		CBUS_REG_ADDR(RTC_ADDR3) 	///../ucode/register.h
#define RTC_ADDR4 0x21d4 	///../ucode/register.h
#define P_RTC_ADDR4 		CBUS_REG_ADDR(RTC_ADDR4) 	///../ucode/register.h
#define MSR_CLK_DUTY 0x21d6 	///../ucode/register.h
#define P_MSR_CLK_DUTY 		CBUS_REG_ADDR(MSR_CLK_DUTY) 	///../ucode/register.h
#define MSR_CLK_REG0 0x21d7 	///../ucode/register.h
#define P_MSR_CLK_REG0 		CBUS_REG_ADDR(MSR_CLK_REG0) 	///../ucode/register.h
#define MSR_CLK_REG1 0x21d8 	///../ucode/register.h
#define P_MSR_CLK_REG1 		CBUS_REG_ADDR(MSR_CLK_REG1) 	///../ucode/register.h
#define MSR_CLK_REG2 0x21d9 	///../ucode/register.h
#define P_MSR_CLK_REG2 		CBUS_REG_ADDR(MSR_CLK_REG2) 	///../ucode/register.h
#define LED_PWM_REG0 0x21da 	///../ucode/register.h
#define P_LED_PWM_REG0 		CBUS_REG_ADDR(LED_PWM_REG0) 	///../ucode/register.h
#define LED_PWM_REG1 0x21db 	///../ucode/register.h
#define P_LED_PWM_REG1 		CBUS_REG_ADDR(LED_PWM_REG1) 	///../ucode/register.h
#define LED_PWM_REG2 0x21dc 	///../ucode/register.h
#define P_LED_PWM_REG2 		CBUS_REG_ADDR(LED_PWM_REG2) 	///../ucode/register.h
#define LED_PWM_REG3 0x21dd 	///../ucode/register.h
#define P_LED_PWM_REG3 		CBUS_REG_ADDR(LED_PWM_REG3) 	///../ucode/register.h
#define LED_PWM_REG4 0x21de 	///../ucode/register.h
#define P_LED_PWM_REG4 		CBUS_REG_ADDR(LED_PWM_REG4) 	///../ucode/register.h
#define LED_PWM_REG5 0x21df 	///../ucode/register.h
#define P_LED_PWM_REG5 		CBUS_REG_ADDR(LED_PWM_REG5) 	///../ucode/register.h
#define LED_PWM_REG6 0x21e0 	///../ucode/register.h
#define P_LED_PWM_REG6 		CBUS_REG_ADDR(LED_PWM_REG6) 	///../ucode/register.h
#define VGHL_PWM_REG0 0x21e1 	///../ucode/register.h
#define P_VGHL_PWM_REG0 		CBUS_REG_ADDR(VGHL_PWM_REG0) 	///../ucode/register.h
#define VGHL_PWM_REG1 0x21e2 	///../ucode/register.h
#define P_VGHL_PWM_REG1 		CBUS_REG_ADDR(VGHL_PWM_REG1) 	///../ucode/register.h
#define VGHL_PWM_REG2 0x21e3 	///../ucode/register.h
#define P_VGHL_PWM_REG2 		CBUS_REG_ADDR(VGHL_PWM_REG2) 	///../ucode/register.h
#define VGHL_PWM_REG3 0x21e4 	///../ucode/register.h
#define P_VGHL_PWM_REG3 		CBUS_REG_ADDR(VGHL_PWM_REG3) 	///../ucode/register.h
#define VGHL_PWM_REG4 0x21e5 	///../ucode/register.h
#define P_VGHL_PWM_REG4 		CBUS_REG_ADDR(VGHL_PWM_REG4) 	///../ucode/register.h
#define VGHL_PWM_REG5 0x21e6 	///../ucode/register.h
#define P_VGHL_PWM_REG5 		CBUS_REG_ADDR(VGHL_PWM_REG5) 	///../ucode/register.h
#define VGHL_PWM_REG6 0x21e7 	///../ucode/register.h
#define P_VGHL_PWM_REG6 		CBUS_REG_ADDR(VGHL_PWM_REG6) 	///../ucode/register.h
#define I2C_M_1_CONTROL_REG 0x21f0 	///../ucode/register.h
#define P_I2C_M_1_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_1_CONTROL_REG) 	///../ucode/register.h
#define I2C_M_1_SLAVE_ADDR 0x21f1 	///../ucode/register.h
#define P_I2C_M_1_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_1_SLAVE_ADDR) 	///../ucode/register.h
#define I2C_M_1_TOKEN_LIST0 0x21f2 	///../ucode/register.h
#define P_I2C_M_1_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST0) 	///../ucode/register.h
#define I2C_M_1_TOKEN_LIST1 0x21f3 	///../ucode/register.h
#define P_I2C_M_1_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_1_TOKEN_LIST1) 	///../ucode/register.h
#define I2C_M_1_WDATA_REG0 0x21f4 	///../ucode/register.h
#define P_I2C_M_1_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_1_WDATA_REG0) 	///../ucode/register.h
#define I2C_M_1_WDATA_REG1 0x21f5 	///../ucode/register.h
#define P_I2C_M_1_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_1_WDATA_REG1) 	///../ucode/register.h
#define I2C_M_1_RDATA_REG0 0x21f6 	///../ucode/register.h
#define P_I2C_M_1_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_1_RDATA_REG0) 	///../ucode/register.h
#define I2C_M_1_RDATA_REG1 0x21f7 	///../ucode/register.h
#define P_I2C_M_1_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_1_RDATA_REG1) 	///../ucode/register.h
#define I2C_M_2_CONTROL_REG 0x21f8 	///../ucode/register.h
#define P_I2C_M_2_CONTROL_REG 		CBUS_REG_ADDR(I2C_M_2_CONTROL_REG) 	///../ucode/register.h
#define I2C_M_2_SLAVE_ADDR 0x21f9 	///../ucode/register.h
#define P_I2C_M_2_SLAVE_ADDR 		CBUS_REG_ADDR(I2C_M_2_SLAVE_ADDR) 	///../ucode/register.h
#define I2C_M_2_TOKEN_LIST0 0x21fa 	///../ucode/register.h
#define P_I2C_M_2_TOKEN_LIST0 		CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST0) 	///../ucode/register.h
#define I2C_M_2_TOKEN_LIST1 0x21fb 	///../ucode/register.h
#define P_I2C_M_2_TOKEN_LIST1 		CBUS_REG_ADDR(I2C_M_2_TOKEN_LIST1) 	///../ucode/register.h
#define I2C_M_2_WDATA_REG0 0x21fc 	///../ucode/register.h
#define P_I2C_M_2_WDATA_REG0 		CBUS_REG_ADDR(I2C_M_2_WDATA_REG0) 	///../ucode/register.h
#define I2C_M_2_WDATA_REG1 0x21fd 	///../ucode/register.h
#define P_I2C_M_2_WDATA_REG1 		CBUS_REG_ADDR(I2C_M_2_WDATA_REG1) 	///../ucode/register.h
#define I2C_M_2_RDATA_REG0 0x21fe 	///../ucode/register.h
#define P_I2C_M_2_RDATA_REG0 		CBUS_REG_ADDR(I2C_M_2_RDATA_REG0) 	///../ucode/register.h
#define I2C_M_2_RDATA_REG1 0x21ff 	///../ucode/register.h
#define P_I2C_M_2_RDATA_REG1 		CBUS_REG_ADDR(I2C_M_2_RDATA_REG1) 	///../ucode/register.h
#define BT_CTRL 0x2240 	///../ucode/register.h
#define P_BT_CTRL 		CBUS_REG_ADDR(BT_CTRL) 	///../ucode/register.h
#define BT_VBISTART 0x2241 	///../ucode/register.h
#define P_BT_VBISTART 		CBUS_REG_ADDR(BT_VBISTART) 	///../ucode/register.h
#define BT_VBIEND 0x2242 	///../ucode/register.h
#define P_BT_VBIEND 		CBUS_REG_ADDR(BT_VBIEND) 	///../ucode/register.h
#define BT_FIELDSADR 0x2243 	///../ucode/register.h
#define P_BT_FIELDSADR 		CBUS_REG_ADDR(BT_FIELDSADR) 	///../ucode/register.h
#define BT_LINECTRL 0x2244 	///../ucode/register.h
#define P_BT_LINECTRL 		CBUS_REG_ADDR(BT_LINECTRL) 	///../ucode/register.h
#define BT_VIDEOSTART 0x2245 	///../ucode/register.h
#define P_BT_VIDEOSTART 		CBUS_REG_ADDR(BT_VIDEOSTART) 	///../ucode/register.h
#define BT_VIDEOEND 0x2246 	///../ucode/register.h
#define P_BT_VIDEOEND 		CBUS_REG_ADDR(BT_VIDEOEND) 	///../ucode/register.h
#define BT_SLICELINE0 0x2247 	///../ucode/register.h
#define P_BT_SLICELINE0 		CBUS_REG_ADDR(BT_SLICELINE0) 	///../ucode/register.h
#define BT_SLICELINE1 0x2248 	///../ucode/register.h
#define P_BT_SLICELINE1 		CBUS_REG_ADDR(BT_SLICELINE1) 	///../ucode/register.h
#define BT_PORT_CTRL 0x2249 	///../ucode/register.h
#define P_BT_PORT_CTRL 		CBUS_REG_ADDR(BT_PORT_CTRL) 	///../ucode/register.h
#define BT_SWAP_CTRL 0x224a 	///../ucode/register.h
#define P_BT_SWAP_CTRL 		CBUS_REG_ADDR(BT_SWAP_CTRL) 	///../ucode/register.h
#define BT_ANCISADR 0x224b 	///../ucode/register.h
#define P_BT_ANCISADR 		CBUS_REG_ADDR(BT_ANCISADR) 	///../ucode/register.h
#define BT_ANCIEADR 0x224c 	///../ucode/register.h
#define P_BT_ANCIEADR 		CBUS_REG_ADDR(BT_ANCIEADR) 	///../ucode/register.h
#define BT_AFIFO_CTRL 0x224d 	///../ucode/register.h
#define P_BT_AFIFO_CTRL 		CBUS_REG_ADDR(BT_AFIFO_CTRL) 	///../ucode/register.h
#define BT_601_CTRL0 0x224e 	///../ucode/register.h
#define P_BT_601_CTRL0 		CBUS_REG_ADDR(BT_601_CTRL0) 	///../ucode/register.h
#define BT_601_CTRL1 0x224f 	///../ucode/register.h
#define P_BT_601_CTRL1 		CBUS_REG_ADDR(BT_601_CTRL1) 	///../ucode/register.h
#define BT_601_CTRL2 0x2250 	///../ucode/register.h
#define P_BT_601_CTRL2 		CBUS_REG_ADDR(BT_601_CTRL2) 	///../ucode/register.h
#define BT_601_CTRL3 0x2251 	///../ucode/register.h
#define P_BT_601_CTRL3 		CBUS_REG_ADDR(BT_601_CTRL3) 	///../ucode/register.h
#define BT_FIELD_LUMA 0x2252 	///../ucode/register.h
#define P_BT_FIELD_LUMA 		CBUS_REG_ADDR(BT_FIELD_LUMA) 	///../ucode/register.h
#define BT_RAW_CTRL 0x2253 	///../ucode/register.h
#define P_BT_RAW_CTRL 		CBUS_REG_ADDR(BT_RAW_CTRL) 	///../ucode/register.h
#define BT_STATUS 0x2254 	///../ucode/register.h
#define P_BT_STATUS 		CBUS_REG_ADDR(BT_STATUS) 	///../ucode/register.h
#define BT_INT_CTRL 0x2255 	///../ucode/register.h
#define P_BT_INT_CTRL 		CBUS_REG_ADDR(BT_INT_CTRL) 	///../ucode/register.h
#define BT_ANCI_STATUS 0x2256 	///../ucode/register.h
#define P_BT_ANCI_STATUS 		CBUS_REG_ADDR(BT_ANCI_STATUS) 	///../ucode/register.h
#define BT_VLINE_STATUS 0x2257 	///../ucode/register.h
#define P_BT_VLINE_STATUS 		CBUS_REG_ADDR(BT_VLINE_STATUS) 	///../ucode/register.h
#define BT_AFIFO_PTR 0x2258 	///../ucode/register.h
#define P_BT_AFIFO_PTR 		CBUS_REG_ADDR(BT_AFIFO_PTR) 	///../ucode/register.h
#define BT_JPEGBYTENUM 0x2259 	///../ucode/register.h
#define P_BT_JPEGBYTENUM 		CBUS_REG_ADDR(BT_JPEGBYTENUM) 	///../ucode/register.h
#define BT_ERR_CNT 0x225a 	///../ucode/register.h
#define P_BT_ERR_CNT 		CBUS_REG_ADDR(BT_ERR_CNT) 	///../ucode/register.h
#define BT_JPEG_STATUS0 0x225b 	///../ucode/register.h
#define P_BT_JPEG_STATUS0 		CBUS_REG_ADDR(BT_JPEG_STATUS0) 	///../ucode/register.h
#define BT_JPEG_STATUS1 0x225c 	///../ucode/register.h
#define P_BT_JPEG_STATUS1 		CBUS_REG_ADDR(BT_JPEG_STATUS1) 	///../ucode/register.h
#define BT_LCNT_STATUS 0x225d 	///../ucode/register.h
#define P_BT_LCNT_STATUS 		CBUS_REG_ADDR(BT_LCNT_STATUS) 	///../ucode/register.h
#define BT_PCNT_STATUS 0x225e 	///../ucode/register.h
#define P_BT_PCNT_STATUS 		CBUS_REG_ADDR(BT_PCNT_STATUS) 	///../ucode/register.h
#define BT656_ADDR_END 0x225f 	///../ucode/register.h
#define P_BT656_ADDR_END 		CBUS_REG_ADDR(BT656_ADDR_END) 	///../ucode/register.h
#define NDMA_CNTL_REG0 0x2270 	///../ucode/register.h
#define P_NDMA_CNTL_REG0 		CBUS_REG_ADDR(NDMA_CNTL_REG0) 	///../ucode/register.h
#define NDMA_TABLE_ADD_REG 0x2272 	///../ucode/register.h
#define P_NDMA_TABLE_ADD_REG 		CBUS_REG_ADDR(NDMA_TABLE_ADD_REG) 	///../ucode/register.h
#define NDMA_TDES_KEY_LO 0x2273 	///../ucode/register.h
#define P_NDMA_TDES_KEY_LO 		CBUS_REG_ADDR(NDMA_TDES_KEY_LO) 	///../ucode/register.h
#define NDMA_TDES_KEY_HI 0x2274 	///../ucode/register.h
#define P_NDMA_TDES_KEY_HI 		CBUS_REG_ADDR(NDMA_TDES_KEY_HI) 	///../ucode/register.h
#define NDMA_TDES_CONTROL 0x2275 	///../ucode/register.h
#define P_NDMA_TDES_CONTROL 		CBUS_REG_ADDR(NDMA_TDES_CONTROL) 	///../ucode/register.h
#define NDMA_AES_CONTROL 0x2276 	///../ucode/register.h
#define P_NDMA_AES_CONTROL 		CBUS_REG_ADDR(NDMA_AES_CONTROL) 	///../ucode/register.h
#define NDMA_AES_RK_FIFO 0x2277 	///../ucode/register.h
#define P_NDMA_AES_RK_FIFO 		CBUS_REG_ADDR(NDMA_AES_RK_FIFO) 	///../ucode/register.h
#define NDMA_CRC_OUT 0x2278 	///../ucode/register.h
#define P_NDMA_CRC_OUT 		CBUS_REG_ADDR(NDMA_CRC_OUT) 	///../ucode/register.h
#define NDMA_THREAD_REG 0x2279 	///../ucode/register.h
#define P_NDMA_THREAD_REG 		CBUS_REG_ADDR(NDMA_THREAD_REG) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_START0 0x2280 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_START0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START0) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_CURR0 0x2281 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_CURR0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR0) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_END0 0x2282 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_END0 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END0) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_START1 0x2283 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_START1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START1) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_CURR1 0x2284 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_CURR1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR1) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_END1 0x2285 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_END1 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END1) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_START2 0x2286 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_START2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START2) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_CURR2 0x2287 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_CURR2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR2) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_END2 0x2288 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_END2 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END2) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_START3 0x2289 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_START3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_START3) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_CURR3 0x228a 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_CURR3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_CURR3) 	///../ucode/register.h
#define NDMA_THREAD_TABLE_END3 0x228b 	///../ucode/register.h
#define P_NDMA_THREAD_TABLE_END3 		CBUS_REG_ADDR(NDMA_THREAD_TABLE_END3) 	///../ucode/register.h
#define NDMA_CNTL_REG1 0x228c 	///../ucode/register.h
#define P_NDMA_CNTL_REG1 		CBUS_REG_ADDR(NDMA_CNTL_REG1) 	///../ucode/register.h
#define STREAM_EVENT_INFO 0x2300 	///../ucode/register.h
#define P_STREAM_EVENT_INFO 		CBUS_REG_ADDR(STREAM_EVENT_INFO) 	///../ucode/register.h
#define STREAM_OUTPUT_CONFIG 0x2301 	///../ucode/register.h
#define P_STREAM_OUTPUT_CONFIG 		CBUS_REG_ADDR(STREAM_OUTPUT_CONFIG) 	///../ucode/register.h
#define C_D_BUS_CONTROL 0x2302 	///../ucode/register.h
#define P_C_D_BUS_CONTROL 		CBUS_REG_ADDR(C_D_BUS_CONTROL) 	///../ucode/register.h
#define C_DATA 0x2303 	///../ucode/register.h
#define P_C_DATA 		CBUS_REG_ADDR(C_DATA) 	///../ucode/register.h
#define STREAM_BUS_CONFIG 0x2304 	///../ucode/register.h
#define P_STREAM_BUS_CONFIG 		CBUS_REG_ADDR(STREAM_BUS_CONFIG) 	///../ucode/register.h
#define STREAM_DATA_IN_CONFIG 0x2305 	///../ucode/register.h
#define P_STREAM_DATA_IN_CONFIG 		CBUS_REG_ADDR(STREAM_DATA_IN_CONFIG) 	///../ucode/register.h
#define STREAM_WAIT_IRQ_CONFIG 0x2306 	///../ucode/register.h
#define P_STREAM_WAIT_IRQ_CONFIG 		CBUS_REG_ADDR(STREAM_WAIT_IRQ_CONFIG) 	///../ucode/register.h
#define STREAM_EVENT_CTL 0x2307 	///../ucode/register.h
#define P_STREAM_EVENT_CTL 		CBUS_REG_ADDR(STREAM_EVENT_CTL) 	///../ucode/register.h
#define CMD_ARGUMENT 0x2308 	///../ucode/register.h
#define P_CMD_ARGUMENT 		CBUS_REG_ADDR(CMD_ARGUMENT) 	///../ucode/register.h
#define CMD_SEND 0x2309 	///../ucode/register.h
#define P_CMD_SEND 		CBUS_REG_ADDR(CMD_SEND) 	///../ucode/register.h
#define SDIO_CONFIG 0x230a 	///../ucode/register.h
#define P_SDIO_CONFIG 		CBUS_REG_ADDR(SDIO_CONFIG) 	///../ucode/register.h
#define SDIO_STATUS_IRQ 0x230b 	///../ucode/register.h
#define P_SDIO_STATUS_IRQ 		CBUS_REG_ADDR(SDIO_STATUS_IRQ) 	///../ucode/register.h
#define SDIO_IRQ_CONFIG 0x230c 	///../ucode/register.h
#define P_SDIO_IRQ_CONFIG 		CBUS_REG_ADDR(SDIO_IRQ_CONFIG) 	///../ucode/register.h
#define SDIO_MULT_CONFIG 0x230d 	///../ucode/register.h
#define P_SDIO_MULT_CONFIG 		CBUS_REG_ADDR(SDIO_MULT_CONFIG) 	///../ucode/register.h
#define SDIO_M_ADDR 0x230e 	///../ucode/register.h
#define P_SDIO_M_ADDR 		CBUS_REG_ADDR(SDIO_M_ADDR) 	///../ucode/register.h
#define SDIO_EXTENSION 0x230f 	///../ucode/register.h
#define P_SDIO_EXTENSION 		CBUS_REG_ADDR(SDIO_EXTENSION) 	///../ucode/register.h
#define ASYNC_FIFO_REG0 0x2310 	///../ucode/register.h
#define P_ASYNC_FIFO_REG0 		CBUS_REG_ADDR(ASYNC_FIFO_REG0) 	///../ucode/register.h
#define ASYNC_FIFO_REG1 0x2311 	///../ucode/register.h
#define P_ASYNC_FIFO_REG1 		CBUS_REG_ADDR(ASYNC_FIFO_REG1) 	///../ucode/register.h
#define ASYNC_FIFO_REG2 0x2312 	///../ucode/register.h
#define P_ASYNC_FIFO_REG2 		CBUS_REG_ADDR(ASYNC_FIFO_REG2) 	///../ucode/register.h
#define ASYNC_FIFO_REG3 0x2313 	///../ucode/register.h
#define P_ASYNC_FIFO_REG3 		CBUS_REG_ADDR(ASYNC_FIFO_REG3) 	///../ucode/register.h
#define ASYNC_FIFO2_REG0 0x2314 	///../ucode/register.h
#define P_ASYNC_FIFO2_REG0 		CBUS_REG_ADDR(ASYNC_FIFO2_REG0) 	///../ucode/register.h
#define ASYNC_FIFO2_REG1 0x2315 	///../ucode/register.h
#define P_ASYNC_FIFO2_REG1 		CBUS_REG_ADDR(ASYNC_FIFO2_REG1) 	///../ucode/register.h
#define ASYNC_FIFO2_REG2 0x2316 	///../ucode/register.h
#define P_ASYNC_FIFO2_REG2 		CBUS_REG_ADDR(ASYNC_FIFO2_REG2) 	///../ucode/register.h
#define ASYNC_FIFO2_REG3 0x2317 	///../ucode/register.h
#define P_ASYNC_FIFO2_REG3 		CBUS_REG_ADDR(ASYNC_FIFO2_REG3) 	///../ucode/register.h
#define SDIO_AHB_CBUS_CTRL 0x2318 	///../ucode/register.h
#define P_SDIO_AHB_CBUS_CTRL 		CBUS_REG_ADDR(SDIO_AHB_CBUS_CTRL) 	///../ucode/register.h
#define SDIO_AHB_CBUS_M_DATA 0x2319 	///../ucode/register.h
#define P_SDIO_AHB_CBUS_M_DATA 		CBUS_REG_ADDR(SDIO_AHB_CBUS_M_DATA) 	///../ucode/register.h
#define SPI_FLASH_CMD 0x2320 	///../ucode/register.h
#define P_SPI_FLASH_CMD 		CBUS_REG_ADDR(SPI_FLASH_CMD) 	///../ucode/register.h
#define SPI_FLASH_ADDR 0x2321 	///../ucode/register.h
#define P_SPI_FLASH_ADDR 		CBUS_REG_ADDR(SPI_FLASH_ADDR) 	///../ucode/register.h
#define SPI_FLASH_CTRL 0x2322 	///../ucode/register.h
#define P_SPI_FLASH_CTRL 		CBUS_REG_ADDR(SPI_FLASH_CTRL) 	///../ucode/register.h
#define SPI_FLASH_CTRL1 0x2323 	///../ucode/register.h
#define P_SPI_FLASH_CTRL1 		CBUS_REG_ADDR(SPI_FLASH_CTRL1) 	///../ucode/register.h
#define SPI_FLASH_STATUS 0x2324 	///../ucode/register.h
#define P_SPI_FLASH_STATUS 		CBUS_REG_ADDR(SPI_FLASH_STATUS) 	///../ucode/register.h
#define SPI_FLASH_CTRL2 0x2325 	///../ucode/register.h
#define P_SPI_FLASH_CTRL2 		CBUS_REG_ADDR(SPI_FLASH_CTRL2) 	///../ucode/register.h
#define SPI_FLASH_CLOCK 0x2326 	///../ucode/register.h
#define P_SPI_FLASH_CLOCK 		CBUS_REG_ADDR(SPI_FLASH_CLOCK) 	///../ucode/register.h
#define SPI_FLASH_USER 0x2327 	///../ucode/register.h
#define P_SPI_FLASH_USER 		CBUS_REG_ADDR(SPI_FLASH_USER) 	///../ucode/register.h
#define SPI_FLASH_USER1 0x2328 	///../ucode/register.h
#define P_SPI_FLASH_USER1 		CBUS_REG_ADDR(SPI_FLASH_USER1) 	///../ucode/register.h
#define SPI_FLASH_USER2 0x2329 	///../ucode/register.h
#define P_SPI_FLASH_USER2 		CBUS_REG_ADDR(SPI_FLASH_USER2) 	///../ucode/register.h
#define SPI_FLASH_USER3 0x232a 	///../ucode/register.h
#define P_SPI_FLASH_USER3 		CBUS_REG_ADDR(SPI_FLASH_USER3) 	///../ucode/register.h
#define SPI_FLASH_USER4 0x232b 	///../ucode/register.h
#define P_SPI_FLASH_USER4 		CBUS_REG_ADDR(SPI_FLASH_USER4) 	///../ucode/register.h
#define SPI_FLASH_SLAVE 0x232c 	///../ucode/register.h
#define P_SPI_FLASH_SLAVE 		CBUS_REG_ADDR(SPI_FLASH_SLAVE) 	///../ucode/register.h
#define SPI_FLASH_SLAVE1 0x232d 	///../ucode/register.h
#define P_SPI_FLASH_SLAVE1 		CBUS_REG_ADDR(SPI_FLASH_SLAVE1) 	///../ucode/register.h
#define SPI_FLASH_SLAVE2 0x232e 	///../ucode/register.h
#define P_SPI_FLASH_SLAVE2 		CBUS_REG_ADDR(SPI_FLASH_SLAVE2) 	///../ucode/register.h
#define SPI_FLASH_SLAVE3 0x232f 	///../ucode/register.h
#define P_SPI_FLASH_SLAVE3 		CBUS_REG_ADDR(SPI_FLASH_SLAVE3) 	///../ucode/register.h
#define SPI_FLASH_C0 0x2330 	///../ucode/register.h
#define P_SPI_FLASH_C0 		CBUS_REG_ADDR(SPI_FLASH_C0) 	///../ucode/register.h
#define SPI_FLASH_C1 0x2331 	///../ucode/register.h
#define P_SPI_FLASH_C1 		CBUS_REG_ADDR(SPI_FLASH_C1) 	///../ucode/register.h
#define SPI_FLASH_C2 0x2332 	///../ucode/register.h
#define P_SPI_FLASH_C2 		CBUS_REG_ADDR(SPI_FLASH_C2) 	///../ucode/register.h
#define SPI_FLASH_C3 0x2333 	///../ucode/register.h
#define P_SPI_FLASH_C3 		CBUS_REG_ADDR(SPI_FLASH_C3) 	///../ucode/register.h
#define SPI_FLASH_C4 0x2334 	///../ucode/register.h
#define P_SPI_FLASH_C4 		CBUS_REG_ADDR(SPI_FLASH_C4) 	///../ucode/register.h
#define SPI_FLASH_C5 0x2335 	///../ucode/register.h
#define P_SPI_FLASH_C5 		CBUS_REG_ADDR(SPI_FLASH_C5) 	///../ucode/register.h
#define SPI_FLASH_C6 0x2336 	///../ucode/register.h
#define P_SPI_FLASH_C6 		CBUS_REG_ADDR(SPI_FLASH_C6) 	///../ucode/register.h
#define SPI_FLASH_C7 0x2337 	///../ucode/register.h
#define P_SPI_FLASH_C7 		CBUS_REG_ADDR(SPI_FLASH_C7) 	///../ucode/register.h
#define SPI_FLASH_B8 0x2338 	///../ucode/register.h
#define P_SPI_FLASH_B8 		CBUS_REG_ADDR(SPI_FLASH_B8) 	///../ucode/register.h
#define SPI_FLASH_B9 0x2339 	///../ucode/register.h
#define P_SPI_FLASH_B9 		CBUS_REG_ADDR(SPI_FLASH_B9) 	///../ucode/register.h
#define SPI_FLASH_B10 0x233a 	///../ucode/register.h
#define P_SPI_FLASH_B10 		CBUS_REG_ADDR(SPI_FLASH_B10) 	///../ucode/register.h
#define SPI_FLASH_B11 0x233b 	///../ucode/register.h
#define P_SPI_FLASH_B11 		CBUS_REG_ADDR(SPI_FLASH_B11) 	///../ucode/register.h
#define SPI_FLASH_B12 0x233c 	///../ucode/register.h
#define P_SPI_FLASH_B12 		CBUS_REG_ADDR(SPI_FLASH_B12) 	///../ucode/register.h
#define SPI_FLASH_B13 0x233d 	///../ucode/register.h
#define P_SPI_FLASH_B13 		CBUS_REG_ADDR(SPI_FLASH_B13) 	///../ucode/register.h
#define SPI_FLASH_B14 0x233e 	///../ucode/register.h
#define P_SPI_FLASH_B14 		CBUS_REG_ADDR(SPI_FLASH_B14) 	///../ucode/register.h
#define SPI_FLASH_B15 0x233f 	///../ucode/register.h
#define P_SPI_FLASH_B15 		CBUS_REG_ADDR(SPI_FLASH_B15) 	///../ucode/register.h
#define SPICC_RXDATA 0x2360 	///../ucode/register.h
#define P_SPICC_RXDATA 		CBUS_REG_ADDR(SPICC_RXDATA) 	///../ucode/register.h
#define SPICC_TXDATA 0x2361 	///../ucode/register.h
#define P_SPICC_TXDATA 		CBUS_REG_ADDR(SPICC_TXDATA) 	///../ucode/register.h
#define SPICC_CONREG 0x2362 	///../ucode/register.h
#define P_SPICC_CONREG 		CBUS_REG_ADDR(SPICC_CONREG) 	///../ucode/register.h
#define SPICC_INTREG 0x2363 	///../ucode/register.h
#define P_SPICC_INTREG 		CBUS_REG_ADDR(SPICC_INTREG) 	///../ucode/register.h
#define SPICC_DMAREG 0x2364 	///../ucode/register.h
#define P_SPICC_DMAREG 		CBUS_REG_ADDR(SPICC_DMAREG) 	///../ucode/register.h
#define SPICC_STATREG 0x2365 	///../ucode/register.h
#define P_SPICC_STATREG 		CBUS_REG_ADDR(SPICC_STATREG) 	///../ucode/register.h
#define SPICC_PERIODREG 0x2366 	///../ucode/register.h
#define P_SPICC_PERIODREG 		CBUS_REG_ADDR(SPICC_PERIODREG) 	///../ucode/register.h
#define SPICC_TESTREG 0x2367 	///../ucode/register.h
#define P_SPICC_TESTREG 		CBUS_REG_ADDR(SPICC_TESTREG) 	///../ucode/register.h
#define SPICC_DRADDR 0x2368 	///../ucode/register.h
#define P_SPICC_DRADDR 		CBUS_REG_ADDR(SPICC_DRADDR) 	///../ucode/register.h
#define SPICC_DWADDR 0x2369 	///../ucode/register.h
#define P_SPICC_DWADDR 		CBUS_REG_ADDR(SPICC_DWADDR) 	///../ucode/register.h
#define SD_REG0_ARGU 0x2380 	///../ucode/register.h
#define P_SD_REG0_ARGU 		CBUS_REG_ADDR(SD_REG0_ARGU) 	///../ucode/register.h
#define SD_REG1_SEND 0x2381 	///../ucode/register.h
#define P_SD_REG1_SEND 		CBUS_REG_ADDR(SD_REG1_SEND) 	///../ucode/register.h
#define SD_REG2_CNTL 0x2382 	///../ucode/register.h
#define P_SD_REG2_CNTL 		CBUS_REG_ADDR(SD_REG2_CNTL) 	///../ucode/register.h
#define SD_REG3_STAT 0x2383 	///../ucode/register.h
#define P_SD_REG3_STAT 		CBUS_REG_ADDR(SD_REG3_STAT) 	///../ucode/register.h
#define SD_REG4_CLKC 0x2384 	///../ucode/register.h
#define P_SD_REG4_CLKC 		CBUS_REG_ADDR(SD_REG4_CLKC) 	///../ucode/register.h
#define SD_REG5_ADDR 0x2385 	///../ucode/register.h
#define P_SD_REG5_ADDR 		CBUS_REG_ADDR(SD_REG5_ADDR) 	///../ucode/register.h
#define SD_REG6_PDMA 0x2386 	///../ucode/register.h
#define P_SD_REG6_PDMA 		CBUS_REG_ADDR(SD_REG6_PDMA) 	///../ucode/register.h
#define SD_REG7_MISC 0x2387 	///../ucode/register.h
#define P_SD_REG7_MISC 		CBUS_REG_ADDR(SD_REG7_MISC) 	///../ucode/register.h
#define SD_REG8_DATA 0x2388 	///../ucode/register.h
#define P_SD_REG8_DATA 		CBUS_REG_ADDR(SD_REG8_DATA) 	///../ucode/register.h
#define SD_REG9_ICTL 0x2389 	///../ucode/register.h
#define P_SD_REG9_ICTL 		CBUS_REG_ADDR(SD_REG9_ICTL) 	///../ucode/register.h
#define SD_REGA_ISTA 0x238a 	///../ucode/register.h
#define P_SD_REGA_ISTA 		CBUS_REG_ADDR(SD_REGA_ISTA) 	///../ucode/register.h
#define SD_REGB_SRST 0x238b 	///../ucode/register.h
#define P_SD_REGB_SRST 		CBUS_REG_ADDR(SD_REGB_SRST) 	///../ucode/register.h
#define ISA_DEBUG_REG0 0x2600 	///../ucode/register.h
#define P_ISA_DEBUG_REG0 		CBUS_REG_ADDR(ISA_DEBUG_REG0) 	///../ucode/register.h
#define ISA_DEBUG_REG1 0x2601 	///../ucode/register.h
#define P_ISA_DEBUG_REG1 		CBUS_REG_ADDR(ISA_DEBUG_REG1) 	///../ucode/register.h
#define ISA_DEBUG_REG2 0x2602 	///../ucode/register.h
#define P_ISA_DEBUG_REG2 		CBUS_REG_ADDR(ISA_DEBUG_REG2) 	///../ucode/register.h
#define ISA_PLL_CLK_SIM0 0x2608 	///../ucode/register.h
#define P_ISA_PLL_CLK_SIM0 		CBUS_REG_ADDR(ISA_PLL_CLK_SIM0) 	///../ucode/register.h
#define ISA_CNTL_REG0 0x2609 	///../ucode/register.h
#define P_ISA_CNTL_REG0 		CBUS_REG_ADDR(ISA_CNTL_REG0) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN0_INTR_STAT 0x2610 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN0_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_STAT) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN0_INTR_STAT_CLR 0x2611 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN0_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_STAT_CLR) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN0_INTR_MASK 0x2612 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN0_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_MASK) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN0_INTR_FIRQ_SEL 0x2613 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN0_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN0_INTR_FIRQ_SEL) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN1_INTR_STAT 0x2614 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN1_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_STAT) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN1_INTR_STAT_CLR 0x2615 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN1_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_STAT_CLR) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN1_INTR_MASK 0x2616 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN1_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_MASK) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN1_INTR_FIRQ_SEL 0x2617 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN1_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN1_INTR_FIRQ_SEL) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN2_INTR_STAT 0x2618 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN2_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_STAT) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN2_INTR_STAT_CLR 0x2619 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN2_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_STAT_CLR) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN2_INTR_MASK 0x261a 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN2_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_MASK) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN2_INTR_FIRQ_SEL 0x261b 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN2_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN2_INTR_FIRQ_SEL) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN3_INTR_STAT 0x261c 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN3_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_STAT) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN3_INTR_STAT_CLR 0x261d 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN3_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_STAT_CLR) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN3_INTR_MASK 0x261e 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN3_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_MASK) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN3_INTR_FIRQ_SEL 0x261f 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN3_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN3_INTR_FIRQ_SEL) 	///../ucode/register.h
#define GPIO_INTR_EDGE_POL 0x2620 	///../ucode/register.h
#define P_GPIO_INTR_EDGE_POL 		CBUS_REG_ADDR(GPIO_INTR_EDGE_POL) 	///../ucode/register.h
#define GPIO_INTR_GPIO_SEL0 0x2621 	///../ucode/register.h
#define P_GPIO_INTR_GPIO_SEL0 		CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL0) 	///../ucode/register.h
#define GPIO_INTR_GPIO_SEL1 0x2622 	///../ucode/register.h
#define P_GPIO_INTR_GPIO_SEL1 		CBUS_REG_ADDR(GPIO_INTR_GPIO_SEL1) 	///../ucode/register.h
#define GPIO_INTR_FILTER_SEL0 0x2623 	///../ucode/register.h
#define P_GPIO_INTR_FILTER_SEL0 		CBUS_REG_ADDR(GPIO_INTR_FILTER_SEL0) 	///../ucode/register.h
#define GLOBAL_INTR_DISABLE 0x2624 	///../ucode/register.h
#define P_GLOBAL_INTR_DISABLE 		CBUS_REG_ADDR(GLOBAL_INTR_DISABLE) 	///../ucode/register.h
#define WATCHDOG_TC 0x2640 	///../ucode/register.h
#define P_WATCHDOG_TC 		CBUS_REG_ADDR(WATCHDOG_TC) 	///../ucode/register.h
#define WATCHDOG_RESET 0x2641 	///../ucode/register.h
#define P_WATCHDOG_RESET 		CBUS_REG_ADDR(WATCHDOG_RESET) 	///../ucode/register.h
#define WATCHDOG_ENABLE_BIT    22	
#define AHB_ARBITER_REG 0x2642 	///../ucode/register.h
#define P_AHB_ARBITER_REG 		CBUS_REG_ADDR(AHB_ARBITER_REG) 	///../ucode/register.h
#define AHB_ARBDEC_REG 0x2643 	///../ucode/register.h
#define P_AHB_ARBDEC_REG 		CBUS_REG_ADDR(AHB_ARBDEC_REG) 	///../ucode/register.h
#define AHB_ARBITER2_REG 0x264a 	///../ucode/register.h
#define P_AHB_ARBITER2_REG 		CBUS_REG_ADDR(AHB_ARBITER2_REG) 	///../ucode/register.h
#define DEVICE_MMCP_CNTL 0x264b 	///../ucode/register.h
#define P_DEVICE_MMCP_CNTL 		CBUS_REG_ADDR(DEVICE_MMCP_CNTL) 	///../ucode/register.h
#define AUDIO_MMCP_CNTL 0x264c 	///../ucode/register.h
#define P_AUDIO_MMCP_CNTL 		CBUS_REG_ADDR(AUDIO_MMCP_CNTL) 	///../ucode/register.h
#define ISA_BIST_REG0 0x2644 	///../ucode/register.h
#define P_ISA_BIST_REG0 		CBUS_REG_ADDR(ISA_BIST_REG0) 	///../ucode/register.h
#define ISA_BIST_REG1 0x2645 	///../ucode/register.h
#define P_ISA_BIST_REG1 		CBUS_REG_ADDR(ISA_BIST_REG1) 	///../ucode/register.h
#define ISA_BIST_REG2 0x2646 	///../ucode/register.h
#define P_ISA_BIST_REG2 		CBUS_REG_ADDR(ISA_BIST_REG2) 	///../ucode/register.h
#define ISA_BIST_REG3 0x2647 	///../ucode/register.h
#define P_ISA_BIST_REG3 		CBUS_REG_ADDR(ISA_BIST_REG3) 	///../ucode/register.h
#define ISA_BIST_REG4 0x2648 	///../ucode/register.h
#define P_ISA_BIST_REG4 		CBUS_REG_ADDR(ISA_BIST_REG4) 	///../ucode/register.h
#define ISA_BIST_REG5 0x2649 	///../ucode/register.h
#define P_ISA_BIST_REG5 		CBUS_REG_ADDR(ISA_BIST_REG5) 	///../ucode/register.h
#define ISA_BIST_REG6 0x264e 	///../ucode/register.h
#define P_ISA_BIST_REG6 		CBUS_REG_ADDR(ISA_BIST_REG6) 	///../ucode/register.h
#define ISA_TIMER_MUX 0x2650 	///../ucode/register.h
#define P_ISA_TIMER_MUX 		CBUS_REG_ADDR(ISA_TIMER_MUX) 	///../ucode/register.h
#define ISA_TIMERA 0x2651 	///../ucode/register.h
#define P_ISA_TIMERA 		CBUS_REG_ADDR(ISA_TIMERA) 	///../ucode/register.h
#define ISA_TIMERB 0x2652 	///../ucode/register.h
#define P_ISA_TIMERB 		CBUS_REG_ADDR(ISA_TIMERB) 	///../ucode/register.h
#define ISA_TIMERC 0x2653 	///../ucode/register.h
#define P_ISA_TIMERC 		CBUS_REG_ADDR(ISA_TIMERC) 	///../ucode/register.h
#define ISA_TIMERD 0x2654 	///../ucode/register.h
#define P_ISA_TIMERD 		CBUS_REG_ADDR(ISA_TIMERD) 	///../ucode/register.h
#define ISA_TIMERE 0x2655 	///../ucode/register.h
#define P_ISA_TIMERE 		CBUS_REG_ADDR(ISA_TIMERE) 	///../ucode/register.h
#define FBUF_ADDR 0x2656 	///../ucode/register.h
#define P_FBUF_ADDR 		CBUS_REG_ADDR(FBUF_ADDR) 	///../ucode/register.h
#define SDRAM_CTL0 0x2657 	///../ucode/register.h
#define P_SDRAM_CTL0 		CBUS_REG_ADDR(SDRAM_CTL0) 	///../ucode/register.h
#define SDRAM_CTL2 0x2658 	///../ucode/register.h
#define P_SDRAM_CTL2 		CBUS_REG_ADDR(SDRAM_CTL2) 	///../ucode/register.h
#define MEDIA_CPU_CTL 0x2659 	///../ucode/register.h
#define P_MEDIA_CPU_CTL 		CBUS_REG_ADDR(MEDIA_CPU_CTL) 	///../ucode/register.h
#define SDRAM_CTL4 0x265a 	///../ucode/register.h
#define P_SDRAM_CTL4 		CBUS_REG_ADDR(SDRAM_CTL4) 	///../ucode/register.h
#define SDRAM_CTL5 0x265b 	///../ucode/register.h
#define P_SDRAM_CTL5 		CBUS_REG_ADDR(SDRAM_CTL5) 	///../ucode/register.h
#define SDRAM_CTL6 0x265c 	///../ucode/register.h
#define P_SDRAM_CTL6 		CBUS_REG_ADDR(SDRAM_CTL6) 	///../ucode/register.h
#define SDRAM_CTL7 0x265d 	///../ucode/register.h
#define P_SDRAM_CTL7 		CBUS_REG_ADDR(SDRAM_CTL7) 	///../ucode/register.h
#define SDRAM_CTL8 0x265e 	///../ucode/register.h
#define P_SDRAM_CTL8 		CBUS_REG_ADDR(SDRAM_CTL8) 	///../ucode/register.h
#define AHB_MP4_MC_CTL 0x265f 	///../ucode/register.h
#define P_AHB_MP4_MC_CTL 		CBUS_REG_ADDR(AHB_MP4_MC_CTL) 	///../ucode/register.h
#define MEDIA_CPU_PCR 0x2660 	///../ucode/register.h
#define P_MEDIA_CPU_PCR 		CBUS_REG_ADDR(MEDIA_CPU_PCR) 	///../ucode/register.h
#define ABUF_WR_CTL0 0x2670 	///../ucode/register.h
#define P_ABUF_WR_CTL0 		CBUS_REG_ADDR(ABUF_WR_CTL0) 	///../ucode/register.h
#define ABUF_WR_CTL1 0x2671 	///../ucode/register.h
#define P_ABUF_WR_CTL1 		CBUS_REG_ADDR(ABUF_WR_CTL1) 	///../ucode/register.h
#define ABUF_WR_CTL2 0x2672 	///../ucode/register.h
#define P_ABUF_WR_CTL2 		CBUS_REG_ADDR(ABUF_WR_CTL2) 	///../ucode/register.h
#define ABUF_WR_CTL3 0x2673 	///../ucode/register.h
#define P_ABUF_WR_CTL3 		CBUS_REG_ADDR(ABUF_WR_CTL3) 	///../ucode/register.h
#define ABUF_RD_CTL0 0x2674 	///../ucode/register.h
#define P_ABUF_RD_CTL0 		CBUS_REG_ADDR(ABUF_RD_CTL0) 	///../ucode/register.h
#define ABUF_RD_CTL1 0x2675 	///../ucode/register.h
#define P_ABUF_RD_CTL1 		CBUS_REG_ADDR(ABUF_RD_CTL1) 	///../ucode/register.h
#define ABUF_RD_CTL2 0x2676 	///../ucode/register.h
#define P_ABUF_RD_CTL2 		CBUS_REG_ADDR(ABUF_RD_CTL2) 	///../ucode/register.h
#define ABUF_RD_CTL3 0x2677 	///../ucode/register.h
#define P_ABUF_RD_CTL3 		CBUS_REG_ADDR(ABUF_RD_CTL3) 	///../ucode/register.h
#define ABUF_ARB_CTL0 0x2678 	///../ucode/register.h
#define P_ABUF_ARB_CTL0 		CBUS_REG_ADDR(ABUF_ARB_CTL0) 	///../ucode/register.h
#define ABUF_FIFO_CTL0 0x2679 	///../ucode/register.h
#define P_ABUF_FIFO_CTL0 		CBUS_REG_ADDR(ABUF_FIFO_CTL0) 	///../ucode/register.h
#define AHB_BRIDGE_CNTL_WR 0x2680 	///../ucode/register.h
#define P_AHB_BRIDGE_CNTL_WR 		CBUS_REG_ADDR(AHB_BRIDGE_CNTL_WR) 	///../ucode/register.h
#define AHB_BRIDGE_REMAP0 0x2681 	///../ucode/register.h
#define P_AHB_BRIDGE_REMAP0 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP0) 	///../ucode/register.h
#define AHB_BRIDGE_REMAP1 0x2682 	///../ucode/register.h
#define P_AHB_BRIDGE_REMAP1 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP1) 	///../ucode/register.h
#define AHB_BRIDGE_REMAP2 0x2683 	///../ucode/register.h
#define P_AHB_BRIDGE_REMAP2 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP2) 	///../ucode/register.h
#define AHB_BRIDGE_REMAP3 0x2684 	///../ucode/register.h
#define P_AHB_BRIDGE_REMAP3 		CBUS_REG_ADDR(AHB_BRIDGE_REMAP3) 	///../ucode/register.h
#define AHB_BRIDGE_CNTL_REG1 0x2685 	///../ucode/register.h
#define P_AHB_BRIDGE_CNTL_REG1 		CBUS_REG_ADDR(AHB_BRIDGE_CNTL_REG1) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN0_INTR_STAT 0x2690 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN0_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN0_INTR_STAT_CLR 0x2691 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN0_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN0_INTR_MASK 0x2692 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN0_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN0_INTR_FIRQ_SEL 0x2693 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN0_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN0_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN1_INTR_STAT 0x2694 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN1_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR 0x2695 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN1_INTR_MASK 0x2696 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN1_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN1_INTR_FIRQ_SEL 0x2697 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN1_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN1_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN2_INTR_STAT 0x2698 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN2_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN2_INTR_STAT_CLR 0x2699 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN2_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN2_INTR_MASK 0x269a 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN2_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN2_INTR_FIRQ_SEL 0x269b 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN2_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN2_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN3_INTR_STAT 0x269c 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN3_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN3_INTR_STAT_CLR 0x269d 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN3_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN3_INTR_MASK 0x269e 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN3_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN3_INTR_FIRQ_SEL 0x269f 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN3_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN3_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN0_INTR_STAT 0x26a0 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN0_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN0_INTR_STAT_CLR 0x26a1 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN0_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN0_INTR_MASK 0x26a2 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN0_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN0_INTR_FIRQ_SEL 0x26a3 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN0_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN0_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN1_INTR_STAT 0x26a4 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN1_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN1_INTR_STAT_CLR 0x26a5 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN1_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN1_INTR_MASK 0x26a6 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN1_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN1_INTR_FIRQ_SEL 0x26a7 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN1_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN1_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN2_INTR_STAT 0x26a8 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN2_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN2_INTR_STAT_CLR 0x26a9 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN2_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN2_INTR_MASK 0x26aa 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN2_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN2_INTR_FIRQ_SEL 0x26ab 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN2_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN2_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN3_INTR_STAT 0x26ac 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN3_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN3_INTR_STAT_CLR 0x26ad 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN3_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN3_INTR_MASK 0x26ae 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN3_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN3_INTR_FIRQ_SEL 0x26af 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN3_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN3_INTR_FIRQ_SEL) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN4_INTR_STAT 0x26b0 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN4_INTR_STAT 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_STAT) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN4_INTR_STAT_CLR 0x26b1 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN4_INTR_STAT_CLR 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_STAT_CLR) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN4_INTR_MASK 0x26b2 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN4_INTR_MASK 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_MASK) 	///../ucode/register.h
#define MEDIA_CPU_IRQ_IN4_INTR_FIRQ_SEL 0x26b3 	///../ucode/register.h
#define P_MEDIA_CPU_IRQ_IN4_INTR_FIRQ_SEL 		CBUS_REG_ADDR(MEDIA_CPU_IRQ_IN4_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN4_INTR_STAT 0x26b4 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN4_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN4_INTR_STAT_CLR 0x26b5 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN4_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN4_INTR_MASK 0x26b6 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN4_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_0_IRQ_IN4_INTR_FIRQ_SEL 0x26b7 	///../ucode/register.h
#define P_SYS_CPU_0_IRQ_IN4_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_0_IRQ_IN4_INTR_FIRQ_SEL) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN4_INTR_STAT 0x26b8 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN4_INTR_STAT 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_STAT) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN4_INTR_STAT_CLR 0x26b9 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN4_INTR_STAT_CLR 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_STAT_CLR) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN4_INTR_MASK 0x26ba 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN4_INTR_MASK 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_MASK) 	///../ucode/register.h
#define SYS_CPU_1_IRQ_IN4_INTR_FIRQ_SEL 0x26bb 	///../ucode/register.h
#define P_SYS_CPU_1_IRQ_IN4_INTR_FIRQ_SEL 		CBUS_REG_ADDR(SYS_CPU_1_IRQ_IN4_INTR_FIRQ_SEL) 	///../ucode/register.h
#define IQ_OM_WIDTH 0x2510 	///../ucode/register.h
#define P_IQ_OM_WIDTH 		CBUS_REG_ADDR(IQ_OM_WIDTH) 	///../ucode/register.h
#define DBG_ADDR_START 0x2ff0 	///../ucode/register.h
#define P_DBG_ADDR_START 		CBUS_REG_ADDR(DBG_ADDR_START) 	///../ucode/register.h
#define DBG_ADDR_END 0x2fff 	///../ucode/register.h
#define P_DBG_ADDR_END 		CBUS_REG_ADDR(DBG_ADDR_END) 	///../ucode/register.h
#define DBG_CTRL 0x2ff1 	///../ucode/register.h
#define P_DBG_CTRL 		CBUS_REG_ADDR(DBG_CTRL) 	///../ucode/register.h
#define DBG_LED 0x2ff2 	///../ucode/register.h
#define P_DBG_LED 		CBUS_REG_ADDR(DBG_LED) 	///../ucode/register.h
#define DBG_SWITCH 0x2ff3 	///../ucode/register.h
#define P_DBG_SWITCH 		CBUS_REG_ADDR(DBG_SWITCH) 	///../ucode/register.h
#define DBG_VERSION 0x2ff4 	///../ucode/register.h
#define P_DBG_VERSION 		CBUS_REG_ADDR(DBG_VERSION) 	///../ucode/register.h
#define VERSION_CTRL 0x1100 	///../ucode/register.h
#define P_VERSION_CTRL 		CBUS_REG_ADDR(VERSION_CTRL) 	///../ucode/register.h
#define RESET0_REGISTER 0x1101 	///../ucode/register.h
#define P_RESET0_REGISTER 		CBUS_REG_ADDR(RESET0_REGISTER) 	///../ucode/register.h
#define RESET1_REGISTER 0x1102 	///../ucode/register.h
#define P_RESET1_REGISTER 		CBUS_REG_ADDR(RESET1_REGISTER) 	///../ucode/register.h
#define RESET2_REGISTER 0x1103 	///../ucode/register.h
#define P_RESET2_REGISTER 		CBUS_REG_ADDR(RESET2_REGISTER) 	///../ucode/register.h
#define RESET3_REGISTER 0x1104 	///../ucode/register.h
#define P_RESET3_REGISTER 		CBUS_REG_ADDR(RESET3_REGISTER) 	///../ucode/register.h
#define RESET4_REGISTER 0x1105 	///../ucode/register.h
#define P_RESET4_REGISTER 		CBUS_REG_ADDR(RESET4_REGISTER) 	///../ucode/register.h
#define RESET5_REGISTER 0x1106 	///../ucode/register.h
#define P_RESET5_REGISTER 		CBUS_REG_ADDR(RESET5_REGISTER) 	///../ucode/register.h
#define RESET6_REGISTER 0x1107 	///../ucode/register.h
#define P_RESET6_REGISTER 		CBUS_REG_ADDR(RESET6_REGISTER) 	///../ucode/register.h
#define RESET0_MASK 0x1110 	///../ucode/register.h
#define P_RESET0_MASK 		CBUS_REG_ADDR(RESET0_MASK) 	///../ucode/register.h
#define RESET1_MASK 0x1111 	///../ucode/register.h
#define P_RESET1_MASK 		CBUS_REG_ADDR(RESET1_MASK) 	///../ucode/register.h
#define RESET2_MASK 0x1112 	///../ucode/register.h
#define P_RESET2_MASK 		CBUS_REG_ADDR(RESET2_MASK) 	///../ucode/register.h
#define RESET3_MASK 0x1113 	///../ucode/register.h
#define P_RESET3_MASK 		CBUS_REG_ADDR(RESET3_MASK) 	///../ucode/register.h
#define RESET4_MASK 0x1114 	///../ucode/register.h
#define P_RESET4_MASK 		CBUS_REG_ADDR(RESET4_MASK) 	///../ucode/register.h
#define RESET5_MASK 0x1115 	///../ucode/register.h
#define P_RESET5_MASK 		CBUS_REG_ADDR(RESET5_MASK) 	///../ucode/register.h
#define RESET6_MASK 0x1116 	///../ucode/register.h
#define P_RESET6_MASK 		CBUS_REG_ADDR(RESET6_MASK) 	///../ucode/register.h
#define CRT_MASK 0x1117 	///../ucode/register.h
#define P_CRT_MASK 		CBUS_REG_ADDR(CRT_MASK) 	///../ucode/register.h
#define SCR_HIU 0x100b 	///../ucode/register.h
#define P_SCR_HIU 		CBUS_REG_ADDR(SCR_HIU) 	///../ucode/register.h
#define HPG_TIMER 0x100f 	///../ucode/register.h
#define P_HPG_TIMER 		CBUS_REG_ADDR(HPG_TIMER) 	///../ucode/register.h
#define HARM_ASB_MB0 0x1030 	///../ucode/register.h
#define P_HARM_ASB_MB0 		CBUS_REG_ADDR(HARM_ASB_MB0) 	///../ucode/register.h
#define HARM_ASB_MB1 0x1031 	///../ucode/register.h
#define P_HARM_ASB_MB1 		CBUS_REG_ADDR(HARM_ASB_MB1) 	///../ucode/register.h
#define HARM_ASB_MB2 0x1032 	///../ucode/register.h
#define P_HARM_ASB_MB2 		CBUS_REG_ADDR(HARM_ASB_MB2) 	///../ucode/register.h
#define HARM_ASB_MB3 0x1033 	///../ucode/register.h
#define P_HARM_ASB_MB3 		CBUS_REG_ADDR(HARM_ASB_MB3) 	///../ucode/register.h
#define HASB_ARM_MB0 0x1034 	///../ucode/register.h
#define P_HASB_ARM_MB0 		CBUS_REG_ADDR(HASB_ARM_MB0) 	///../ucode/register.h
#define HASB_ARM_MB1 0x1035 	///../ucode/register.h
#define P_HASB_ARM_MB1 		CBUS_REG_ADDR(HASB_ARM_MB1) 	///../ucode/register.h
#define HASB_ARM_MB2 0x1036 	///../ucode/register.h
#define P_HASB_ARM_MB2 		CBUS_REG_ADDR(HASB_ARM_MB2) 	///../ucode/register.h
#define HASB_ARM_MB3 0x1037 	///../ucode/register.h
#define P_HASB_ARM_MB3 		CBUS_REG_ADDR(HASB_ARM_MB3) 	///../ucode/register.h
#define HHI_TIMER90K 0x103b 	///../ucode/register.h
#define P_HHI_TIMER90K 		CBUS_REG_ADDR(HHI_TIMER90K) 	///../ucode/register.h
#define HHI_AUD_DAC_CTRL 0x1044 	///../ucode/register.h
#define P_HHI_AUD_DAC_CTRL 		CBUS_REG_ADDR(HHI_AUD_DAC_CTRL) 	///../ucode/register.h
#define HHI_VIID_PLL_CNTL4 0x1046 	///../ucode/register.h
#define P_HHI_VIID_PLL_CNTL4 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL4) 	///../ucode/register.h
#define HHI_VIID_PLL_CNTL 0x1047 	///../ucode/register.h
#define P_HHI_VIID_PLL_CNTL 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL) 	///../ucode/register.h
#define HHI_VIID_PLL_CNTL2 0x1048 	///../ucode/register.h
#define P_HHI_VIID_PLL_CNTL2 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL2) 	///../ucode/register.h
#define HHI_VIID_PLL_CNTL3 0x1049 	///../ucode/register.h
#define P_HHI_VIID_PLL_CNTL3 		CBUS_REG_ADDR(HHI_VIID_PLL_CNTL3) 	///../ucode/register.h
#define HHI_VIID_CLK_DIV 0x104a 	///../ucode/register.h
#define P_HHI_VIID_CLK_DIV 		CBUS_REG_ADDR(HHI_VIID_CLK_DIV) 	///../ucode/register.h
#define HHI_VIID_CLK_CNTL 0x104b 	///../ucode/register.h
#define P_HHI_VIID_CLK_CNTL 		CBUS_REG_ADDR(HHI_VIID_CLK_CNTL) 	///../ucode/register.h
#define HHI_VIID_DIVIDER_CNTL 0x104c 	///../ucode/register.h
#define P_HHI_VIID_DIVIDER_CNTL 		CBUS_REG_ADDR(HHI_VIID_DIVIDER_CNTL) 	///../ucode/register.h
#define HHI_GCLK_MPEG0 0x1050 	///../ucode/register.h
#define P_HHI_GCLK_MPEG0 		CBUS_REG_ADDR(HHI_GCLK_MPEG0) 	///../ucode/register.h
#define HHI_GCLK_MPEG1 0x1051 	///../ucode/register.h
#define P_HHI_GCLK_MPEG1 		CBUS_REG_ADDR(HHI_GCLK_MPEG1) 	///../ucode/register.h
#define HHI_GCLK_MPEG2 0x1052 	///../ucode/register.h
#define P_HHI_GCLK_MPEG2 		CBUS_REG_ADDR(HHI_GCLK_MPEG2) 	///../ucode/register.h
#define HHI_GCLK_OTHER 0x1054 	///../ucode/register.h
#define P_HHI_GCLK_OTHER 		CBUS_REG_ADDR(HHI_GCLK_OTHER) 	///../ucode/register.h
#define HHI_GCLK_AO 0x1055 	///../ucode/register.h
#define P_HHI_GCLK_AO 		CBUS_REG_ADDR(HHI_GCLK_AO) 	///../ucode/register.h
#define HHI_VID_CLK_DIV 0x1059 	///../ucode/register.h
#define P_HHI_VID_CLK_DIV 		CBUS_REG_ADDR(HHI_VID_CLK_DIV) 	///../ucode/register.h
#define HHI_MPEG_CLK_CNTL 0x105d 	///../ucode/register.h
#define P_HHI_MPEG_CLK_CNTL 		CBUS_REG_ADDR(HHI_MPEG_CLK_CNTL) 	///../ucode/register.h
#define HHI_AUD_CLK_CNTL 0x105e 	///../ucode/register.h
#define P_HHI_AUD_CLK_CNTL 		CBUS_REG_ADDR(HHI_AUD_CLK_CNTL) 	///../ucode/register.h
#define HHI_VID_CLK_CNTL 0x105f 	///../ucode/register.h
#define P_HHI_VID_CLK_CNTL 		CBUS_REG_ADDR(HHI_VID_CLK_CNTL) 	///../ucode/register.h
#define HHI_WIFI_CLK_CNTL 0x1060 	///../ucode/register.h
#define P_HHI_WIFI_CLK_CNTL 		CBUS_REG_ADDR(HHI_WIFI_CLK_CNTL) 	///../ucode/register.h
#define HHI_WIFI_PLL_CNTL 0x1061 	///../ucode/register.h
#define P_HHI_WIFI_PLL_CNTL 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL) 	///../ucode/register.h
#define HHI_WIFI_PLL_CNTL2 0x1062 	///../ucode/register.h
#define P_HHI_WIFI_PLL_CNTL2 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL2) 	///../ucode/register.h
#define HHI_WIFI_PLL_CNTL3 0x1063 	///../ucode/register.h
#define P_HHI_WIFI_PLL_CNTL3 		CBUS_REG_ADDR(HHI_WIFI_PLL_CNTL3) 	///../ucode/register.h
#define HHI_AUD_CLK_CNTL2 0x1064 	///../ucode/register.h
#define P_HHI_AUD_CLK_CNTL2 		CBUS_REG_ADDR(HHI_AUD_CLK_CNTL2) 	///../ucode/register.h
#define HHI_VID_DIVIDER_CNTL 0x1066 	///../ucode/register.h
#define P_HHI_VID_DIVIDER_CNTL 		CBUS_REG_ADDR(HHI_VID_DIVIDER_CNTL) 	///../ucode/register.h
#define HHI_SYS_CPU_CLK_CNTL 0x1067 	///../ucode/register.h
#define P_HHI_SYS_CPU_CLK_CNTL 		CBUS_REG_ADDR(HHI_SYS_CPU_CLK_CNTL) 	///../ucode/register.h
#define HHI_DDR_PLL_CNTL 0x1068 	///../ucode/register.h
#define P_HHI_DDR_PLL_CNTL 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL) 	///../ucode/register.h
#define HHI_DDR_PLL_CNTL2 0x1069 	///../ucode/register.h
#define P_HHI_DDR_PLL_CNTL2 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL2) 	///../ucode/register.h
#define HHI_DDR_PLL_CNTL3 0x106a 	///../ucode/register.h
#define P_HHI_DDR_PLL_CNTL3 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL3) 	///../ucode/register.h
#define HHI_DDR_PLL_CNTL4 0x106b 	///../ucode/register.h
#define P_HHI_DDR_PLL_CNTL4 		CBUS_REG_ADDR(HHI_DDR_PLL_CNTL4) 	///../ucode/register.h
#define HHI_MALI_CLK_CNTL 0x106c 	///../ucode/register.h
#define P_HHI_MALI_CLK_CNTL 		CBUS_REG_ADDR(HHI_MALI_CLK_CNTL) 	///../ucode/register.h
#define HHI_VDEC_CLK_CNTL 0x106d 	///../ucode/register.h
#define P_HHI_VDEC_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDEC_CLK_CNTL) 	///../ucode/register.h
#define HHI_MIPI_PHY_CLK_CNTL 0x106e 	///../ucode/register.h
#define P_HHI_MIPI_PHY_CLK_CNTL 		CBUS_REG_ADDR(HHI_MIPI_PHY_CLK_CNTL) 	///../ucode/register.h
#define HHI_OTHER_PLL_CNTL 0x1070 	///../ucode/register.h
#define P_HHI_OTHER_PLL_CNTL 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL) 	///../ucode/register.h
#define HHI_OTHER_PLL_CNTL2 0x1071 	///../ucode/register.h
#define P_HHI_OTHER_PLL_CNTL2 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL2) 	///../ucode/register.h
#define HHI_OTHER_PLL_CNTL3 0x1072 	///../ucode/register.h
#define P_HHI_OTHER_PLL_CNTL3 		CBUS_REG_ADDR(HHI_OTHER_PLL_CNTL3) 	///../ucode/register.h
#define HHI_HDMI_CLK_CNTL 0x1073 	///../ucode/register.h
#define P_HHI_HDMI_CLK_CNTL 		CBUS_REG_ADDR(HHI_HDMI_CLK_CNTL) 	///../ucode/register.h
#define HHI_DEMOD_CLK_CNTL 0x1074 	///../ucode/register.h
#define P_HHI_DEMOD_CLK_CNTL 		CBUS_REG_ADDR(HHI_DEMOD_CLK_CNTL) 	///../ucode/register.h
#define HHI_SATA_CLK_CNTL 0x1075 	///../ucode/register.h
#define P_HHI_SATA_CLK_CNTL 		CBUS_REG_ADDR(HHI_SATA_CLK_CNTL) 	///../ucode/register.h
#define HHI_ETH_CLK_CNTL 0x1076 	///../ucode/register.h
#define P_HHI_ETH_CLK_CNTL 		CBUS_REG_ADDR(HHI_ETH_CLK_CNTL) 	///../ucode/register.h
#define HHI_CLK_DOUBLE_CNTL 0x1077 	///../ucode/register.h
#define P_HHI_CLK_DOUBLE_CNTL 		CBUS_REG_ADDR(HHI_CLK_DOUBLE_CNTL) 	///../ucode/register.h
#define HHI_SYS_CPU_AUTO_CLK0 0x1078 	///../ucode/register.h
#define P_HHI_SYS_CPU_AUTO_CLK0 		CBUS_REG_ADDR(HHI_SYS_CPU_AUTO_CLK0) 	///../ucode/register.h
#define HHI_SYS_CPU_AUTO_CLK1 0x1079 	///../ucode/register.h
#define P_HHI_SYS_CPU_AUTO_CLK1 		CBUS_REG_ADDR(HHI_SYS_CPU_AUTO_CLK1) 	///../ucode/register.h
#define HHI_MEDIA_CPU_AUTO_CLK0 0x107a 	///../ucode/register.h
#define P_HHI_MEDIA_CPU_AUTO_CLK0 		CBUS_REG_ADDR(HHI_MEDIA_CPU_AUTO_CLK0) 	///../ucode/register.h
#define HHI_MEDIA_CPU_AUTO_CLK1 0x107b 	///../ucode/register.h
#define P_HHI_MEDIA_CPU_AUTO_CLK1 		CBUS_REG_ADDR(HHI_MEDIA_CPU_AUTO_CLK1) 	///../ucode/register.h
#define HHI_HDMI_PLL_CNTL 0x107c 	///../ucode/register.h
#define P_HHI_HDMI_PLL_CNTL 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL) 	///../ucode/register.h
#define HHI_HDMI_PLL_CNTL1 0x107d 	///../ucode/register.h
#define P_HHI_HDMI_PLL_CNTL1 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL1) 	///../ucode/register.h
#define HHI_HDMI_PLL_CNTL2 0x107e 	///../ucode/register.h
#define P_HHI_HDMI_PLL_CNTL2 		CBUS_REG_ADDR(HHI_HDMI_PLL_CNTL2) 	///../ucode/register.h
#define HHI_HDMI_AFC_CNTL 0x107f 	///../ucode/register.h
#define P_HHI_HDMI_AFC_CNTL 		CBUS_REG_ADDR(HHI_HDMI_AFC_CNTL) 	///../ucode/register.h
#define HHI_VID_PLL_MOD_CNTL0 0x1084 	///../ucode/register.h
#define P_HHI_VID_PLL_MOD_CNTL0 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_CNTL0) 	///../ucode/register.h
#define HHI_VID_PLL_MOD_LOW_TCNT 0x1085 	///../ucode/register.h
#define P_HHI_VID_PLL_MOD_LOW_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_LOW_TCNT) 	///../ucode/register.h
#define HHI_VID_PLL_MOD_HIGH_TCNT 0x1086 	///../ucode/register.h
#define P_HHI_VID_PLL_MOD_HIGH_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_HIGH_TCNT) 	///../ucode/register.h
#define HHI_VID_PLL_MOD_NOM_TCNT 0x1087 	///../ucode/register.h
#define P_HHI_VID_PLL_MOD_NOM_TCNT 		CBUS_REG_ADDR(HHI_VID_PLL_MOD_NOM_TCNT) 	///../ucode/register.h
#define HHI_DDR_CLK_CNTL 0x1088 	///../ucode/register.h
#define P_HHI_DDR_CLK_CNTL 		CBUS_REG_ADDR(HHI_DDR_CLK_CNTL) 	///../ucode/register.h
#define HHI_GEN_CLK_CNTL 0x108a 	///../ucode/register.h
#define P_HHI_GEN_CLK_CNTL 		CBUS_REG_ADDR(HHI_GEN_CLK_CNTL) 	///../ucode/register.h
#define HHI_GEN_CLK_CNTL2 0x108b 	///../ucode/register.h
#define P_HHI_GEN_CLK_CNTL2 		CBUS_REG_ADDR(HHI_GEN_CLK_CNTL2) 	///../ucode/register.h
#define HHI_JTAG_CONFIG 0x108e 	///../ucode/register.h
#define P_HHI_JTAG_CONFIG 		CBUS_REG_ADDR(HHI_JTAG_CONFIG) 	///../ucode/register.h
#define HHI_VAFE_CLKXTALIN_CNTL 0x108f 	///../ucode/register.h
#define P_HHI_VAFE_CLKXTALIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKXTALIN_CNTL) 	///../ucode/register.h
#define HHI_VAFE_CLKOSCIN_CNTL 0x1090 	///../ucode/register.h
#define P_HHI_VAFE_CLKOSCIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKOSCIN_CNTL) 	///../ucode/register.h
#define HHI_VAFE_CLKIN_CNTL 0x1091 	///../ucode/register.h
#define P_HHI_VAFE_CLKIN_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKIN_CNTL) 	///../ucode/register.h
#define HHI_TVFE_AUTOMODE_CLK_CNTL 0x1092 	///../ucode/register.h
#define P_HHI_TVFE_AUTOMODE_CLK_CNTL 		CBUS_REG_ADDR(HHI_TVFE_AUTOMODE_CLK_CNTL) 	///../ucode/register.h
#define HHI_VAFE_CLKPI_CNTL 0x1093 	///../ucode/register.h
#define P_HHI_VAFE_CLKPI_CNTL 		CBUS_REG_ADDR(HHI_VAFE_CLKPI_CNTL) 	///../ucode/register.h
#define HHI_VDIN_MEAS_CLK_CNTL 0x1094 	///../ucode/register.h
#define P_HHI_VDIN_MEAS_CLK_CNTL 		CBUS_REG_ADDR(HHI_VDIN_MEAS_CLK_CNTL) 	///../ucode/register.h
#define HHI_PCM_CLK_CNTL 0x1096 	///../ucode/register.h
#define P_HHI_PCM_CLK_CNTL 		CBUS_REG_ADDR(HHI_PCM_CLK_CNTL) 	///../ucode/register.h
#define HHI_SYS_PLL_CNTL 0x1098 	///../ucode/register.h
#define P_HHI_SYS_PLL_CNTL 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL) 	///../ucode/register.h
#define HHI_SYS_PLL_CNTL2 0x1099 	///../ucode/register.h
#define P_HHI_SYS_PLL_CNTL2 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL2) 	///../ucode/register.h
#define HHI_SYS_PLL_CNTL3 0x109a 	///../ucode/register.h
#define P_HHI_SYS_PLL_CNTL3 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL3) 	///../ucode/register.h
#define HHI_SYS_PLL_CNTL4 0x109b 	///../ucode/register.h
#define P_HHI_SYS_PLL_CNTL4 		CBUS_REG_ADDR(HHI_SYS_PLL_CNTL4) 	///../ucode/register.h
#define HHI_VID_PLL_CNTL 0x109c 	///../ucode/register.h
#define P_HHI_VID_PLL_CNTL 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL) 	///../ucode/register.h
#define HHI_VID_PLL_CNTL2 0x109d 	///../ucode/register.h
#define P_HHI_VID_PLL_CNTL2 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL2) 	///../ucode/register.h
#define HHI_VID_PLL_CNTL3 0x109e 	///../ucode/register.h
#define P_HHI_VID_PLL_CNTL3 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL3) 	///../ucode/register.h
#define HHI_VID_PLL_CNTL4 0x109f 	///../ucode/register.h
#define P_HHI_VID_PLL_CNTL4 		CBUS_REG_ADDR(HHI_VID_PLL_CNTL4) 	///../ucode/register.h
#define HHI_MPLL_CNTL 0x10a0 	///../ucode/register.h
#define P_HHI_MPLL_CNTL 		CBUS_REG_ADDR(HHI_MPLL_CNTL) 	///../ucode/register.h
#define HHI_MPLL_CNTL2 0x10a1 	///../ucode/register.h
#define P_HHI_MPLL_CNTL2 		CBUS_REG_ADDR(HHI_MPLL_CNTL2) 	///../ucode/register.h
#define HHI_MPLL_CNTL3 0x10a2 	///../ucode/register.h
#define P_HHI_MPLL_CNTL3 		CBUS_REG_ADDR(HHI_MPLL_CNTL3) 	///../ucode/register.h
#define HHI_MPLL_CNTL4 0x10a3 	///../ucode/register.h
#define P_HHI_MPLL_CNTL4 		CBUS_REG_ADDR(HHI_MPLL_CNTL4) 	///../ucode/register.h
#define HHI_MPLL_CNTL5 0x10a4 	///../ucode/register.h
#define P_HHI_MPLL_CNTL5 		CBUS_REG_ADDR(HHI_MPLL_CNTL5) 	///../ucode/register.h
#define HHI_MPLL_CNTL6 0x10a5 	///../ucode/register.h
#define P_HHI_MPLL_CNTL6 		CBUS_REG_ADDR(HHI_MPLL_CNTL6) 	///../ucode/register.h
#define HHI_MPLL_CNTL7 0x10a6 	///../ucode/register.h
#define P_HHI_MPLL_CNTL7 		CBUS_REG_ADDR(HHI_MPLL_CNTL7) 	///../ucode/register.h
#define HHI_MPLL_CNTL8 0x10a7 	///../ucode/register.h
#define P_HHI_MPLL_CNTL8 		CBUS_REG_ADDR(HHI_MPLL_CNTL8) 	///../ucode/register.h
#define HHI_MPLL_CNTL9 0x10a8 	///../ucode/register.h
#define P_HHI_MPLL_CNTL9 		CBUS_REG_ADDR(HHI_MPLL_CNTL9) 	///../ucode/register.h
#define HHI_MPLL_CNTL10 0x10a9 	///../ucode/register.h
#define P_HHI_MPLL_CNTL10 		CBUS_REG_ADDR(HHI_MPLL_CNTL10) 	///../ucode/register.h
#define PARSER_CONTROL 0x2960 	///../ucode/register.h
#define P_PARSER_CONTROL 		CBUS_REG_ADDR(PARSER_CONTROL) 	///../ucode/register.h
#define PARSER_FETCH_ADDR 0x2961 	///../ucode/register.h
#define P_PARSER_FETCH_ADDR 		CBUS_REG_ADDR(PARSER_FETCH_ADDR) 	///../ucode/register.h
#define PARSER_FETCH_CMD 0x2962 	///../ucode/register.h
#define P_PARSER_FETCH_CMD 		CBUS_REG_ADDR(PARSER_FETCH_CMD) 	///../ucode/register.h
#define PARSER_FETCH_STOP_ADDR 0x2963 	///../ucode/register.h
#define P_PARSER_FETCH_STOP_ADDR 		CBUS_REG_ADDR(PARSER_FETCH_STOP_ADDR) 	///../ucode/register.h
#define PARSER_FETCH_LEVEL 0x2964 	///../ucode/register.h
#define P_PARSER_FETCH_LEVEL 		CBUS_REG_ADDR(PARSER_FETCH_LEVEL) 	///../ucode/register.h
#define PARSER_CONFIG 0x2965 	///../ucode/register.h
#define P_PARSER_CONFIG 		CBUS_REG_ADDR(PARSER_CONFIG) 	///../ucode/register.h
#define PFIFO_WR_PTR 0x2966 	///../ucode/register.h
#define P_PFIFO_WR_PTR 		CBUS_REG_ADDR(PFIFO_WR_PTR) 	///../ucode/register.h
#define PFIFO_RD_PTR 0x2967 	///../ucode/register.h
#define P_PFIFO_RD_PTR 		CBUS_REG_ADDR(PFIFO_RD_PTR) 	///../ucode/register.h
#define PFIFO_DATA 0x2968 	///../ucode/register.h
#define P_PFIFO_DATA 		CBUS_REG_ADDR(PFIFO_DATA) 	///../ucode/register.h
#define PARSER_SEARCH_PATTERN 0x2969 	///../ucode/register.h
#define P_PARSER_SEARCH_PATTERN 		CBUS_REG_ADDR(PARSER_SEARCH_PATTERN) 	///../ucode/register.h
#define PARSER_SEARCH_MASK 0x296a 	///../ucode/register.h
#define P_PARSER_SEARCH_MASK 		CBUS_REG_ADDR(PARSER_SEARCH_MASK) 	///../ucode/register.h
#define PARSER_INT_ENABLE 0x296b 	///../ucode/register.h
#define P_PARSER_INT_ENABLE 		CBUS_REG_ADDR(PARSER_INT_ENABLE) 	///../ucode/register.h
#define PARSER_INT_STATUS 0x296c 	///../ucode/register.h
#define P_PARSER_INT_STATUS 		CBUS_REG_ADDR(PARSER_INT_STATUS) 	///../ucode/register.h
#define PARSER_SCR_CTL 0x296d 	///../ucode/register.h
#define P_PARSER_SCR_CTL 		CBUS_REG_ADDR(PARSER_SCR_CTL) 	///../ucode/register.h
#define PARSER_SCR 0x296e 	///../ucode/register.h
#define P_PARSER_SCR 		CBUS_REG_ADDR(PARSER_SCR) 	///../ucode/register.h
#define PARSER_PARAMETER 0x296f 	///../ucode/register.h
#define P_PARSER_PARAMETER 		CBUS_REG_ADDR(PARSER_PARAMETER) 	///../ucode/register.h
#define PARSER_INSERT_DATA 0x2970 	///../ucode/register.h
#define P_PARSER_INSERT_DATA 		CBUS_REG_ADDR(PARSER_INSERT_DATA) 	///../ucode/register.h
#define VAS_STREAM_ID 0x2971 	///../ucode/register.h
#define P_VAS_STREAM_ID 		CBUS_REG_ADDR(VAS_STREAM_ID) 	///../ucode/register.h
#define VIDEO_DTS 0x2972 	///../ucode/register.h
#define P_VIDEO_DTS 		CBUS_REG_ADDR(VIDEO_DTS) 	///../ucode/register.h
#define VIDEO_PTS 0x2973 	///../ucode/register.h
#define P_VIDEO_PTS 		CBUS_REG_ADDR(VIDEO_PTS) 	///../ucode/register.h
#define VIDEO_PTS_DTS_WR_PTR 0x2974 	///../ucode/register.h
#define P_VIDEO_PTS_DTS_WR_PTR 		CBUS_REG_ADDR(VIDEO_PTS_DTS_WR_PTR) 	///../ucode/register.h
#define AUDIO_PTS 0x2975 	///../ucode/register.h
#define P_AUDIO_PTS 		CBUS_REG_ADDR(AUDIO_PTS) 	///../ucode/register.h
#define AUDIO_PTS_WR_PTR 0x2976 	///../ucode/register.h
#define P_AUDIO_PTS_WR_PTR 		CBUS_REG_ADDR(AUDIO_PTS_WR_PTR) 	///../ucode/register.h
#define PARSER_ES_CONTROL 0x2977 	///../ucode/register.h
#define P_PARSER_ES_CONTROL 		CBUS_REG_ADDR(PARSER_ES_CONTROL) 	///../ucode/register.h
#define PFIFO_MONITOR 0x2978 	///../ucode/register.h
#define P_PFIFO_MONITOR 		CBUS_REG_ADDR(PFIFO_MONITOR) 	///../ucode/register.h
#define PARSER_VIDEO_START_PTR 0x2980 	///../ucode/register.h
#define P_PARSER_VIDEO_START_PTR 		CBUS_REG_ADDR(PARSER_VIDEO_START_PTR) 	///../ucode/register.h
#define PARSER_VIDEO_END_PTR 0x2981 	///../ucode/register.h
#define P_PARSER_VIDEO_END_PTR 		CBUS_REG_ADDR(PARSER_VIDEO_END_PTR) 	///../ucode/register.h
#define PARSER_VIDEO_WP 0x2982 	///../ucode/register.h
#define P_PARSER_VIDEO_WP 		CBUS_REG_ADDR(PARSER_VIDEO_WP) 	///../ucode/register.h
#define PARSER_VIDEO_RP 0x2983 	///../ucode/register.h
#define P_PARSER_VIDEO_RP 		CBUS_REG_ADDR(PARSER_VIDEO_RP) 	///../ucode/register.h
#define PARSER_VIDEO_HOLE 0x2984 	///../ucode/register.h
#define P_PARSER_VIDEO_HOLE 		CBUS_REG_ADDR(PARSER_VIDEO_HOLE) 	///../ucode/register.h
#define PARSER_AUDIO_START_PTR 0x2985 	///../ucode/register.h
#define P_PARSER_AUDIO_START_PTR 		CBUS_REG_ADDR(PARSER_AUDIO_START_PTR) 	///../ucode/register.h
#define PARSER_AUDIO_END_PTR 0x2986 	///../ucode/register.h
#define P_PARSER_AUDIO_END_PTR 		CBUS_REG_ADDR(PARSER_AUDIO_END_PTR) 	///../ucode/register.h
#define PARSER_AUDIO_WP 0x2987 	///../ucode/register.h
#define P_PARSER_AUDIO_WP 		CBUS_REG_ADDR(PARSER_AUDIO_WP) 	///../ucode/register.h
#define PARSER_AUDIO_RP 0x2988 	///../ucode/register.h
#define P_PARSER_AUDIO_RP 		CBUS_REG_ADDR(PARSER_AUDIO_RP) 	///../ucode/register.h
#define PARSER_AUDIO_HOLE 0x2989 	///../ucode/register.h
#define P_PARSER_AUDIO_HOLE 		CBUS_REG_ADDR(PARSER_AUDIO_HOLE) 	///../ucode/register.h
#define PARSER_SUB_START_PTR 0x298a 	///../ucode/register.h
#define P_PARSER_SUB_START_PTR 		CBUS_REG_ADDR(PARSER_SUB_START_PTR) 	///../ucode/register.h
#define PARSER_SUB_END_PTR 0x298b 	///../ucode/register.h
#define P_PARSER_SUB_END_PTR 		CBUS_REG_ADDR(PARSER_SUB_END_PTR) 	///../ucode/register.h
#define PARSER_SUB_WP 0x298c 	///../ucode/register.h
#define P_PARSER_SUB_WP 		CBUS_REG_ADDR(PARSER_SUB_WP) 	///../ucode/register.h
#define PARSER_SUB_RP 0x298d 	///../ucode/register.h
#define P_PARSER_SUB_RP 		CBUS_REG_ADDR(PARSER_SUB_RP) 	///../ucode/register.h
#define PARSER_SUB_HOLE 0x298e 	///../ucode/register.h
#define P_PARSER_SUB_HOLE 		CBUS_REG_ADDR(PARSER_SUB_HOLE) 	///../ucode/register.h
#define PARSER_FETCH_INFO 0x298f 	///../ucode/register.h
#define P_PARSER_FETCH_INFO 		CBUS_REG_ADDR(PARSER_FETCH_INFO) 	///../ucode/register.h
#define PARSER_STATUS 0x2990 	///../ucode/register.h
#define P_PARSER_STATUS 		CBUS_REG_ADDR(PARSER_STATUS) 	///../ucode/register.h
#define PARSER_AV_WRAP_COUNT 0x2991 	///../ucode/register.h
#define P_PARSER_AV_WRAP_COUNT 		CBUS_REG_ADDR(PARSER_AV_WRAP_COUNT) 	///../ucode/register.h
#define WRRSP_PARSER 0x2992 	///../ucode/register.h
#define P_WRRSP_PARSER 		CBUS_REG_ADDR(WRRSP_PARSER) 	///../ucode/register.h
#define PARSER_VIDEO2_START_PTR 0x2993 	///../ucode/register.h
#define P_PARSER_VIDEO2_START_PTR 		CBUS_REG_ADDR(PARSER_VIDEO2_START_PTR) 	///../ucode/register.h
#define PARSER_VIDEO2_END_PTR 0x2994 	///../ucode/register.h
#define P_PARSER_VIDEO2_END_PTR 		CBUS_REG_ADDR(PARSER_VIDEO2_END_PTR) 	///../ucode/register.h
#define PARSER_VIDEO2_WP 0x2995 	///../ucode/register.h
#define P_PARSER_VIDEO2_WP 		CBUS_REG_ADDR(PARSER_VIDEO2_WP) 	///../ucode/register.h
#define PARSER_VIDEO2_RP 0x2996 	///../ucode/register.h
#define P_PARSER_VIDEO2_RP 		CBUS_REG_ADDR(PARSER_VIDEO2_RP) 	///../ucode/register.h
#define PARSER_VIDEO2_HOLE 0x2997 	///../ucode/register.h
#define P_PARSER_VIDEO2_HOLE 		CBUS_REG_ADDR(PARSER_VIDEO2_HOLE) 	///../ucode/register.h
#define PARSER_AV2_WRAP_COUNT 0x2998 	///../ucode/register.h
#define P_PARSER_AV2_WRAP_COUNT 		CBUS_REG_ADDR(PARSER_AV2_WRAP_COUNT) 	///../ucode/register.h
#define VDIN0_OFFSET 0x00 	///../ucode/register.h
#define P_VDIN0_OFFSET 		CBUS_REG_ADDR(VDIN0_OFFSET) 	///../ucode/register.h
#define VDIN1_OFFSET 0x70 	///../ucode/register.h
#define P_VDIN1_OFFSET 		CBUS_REG_ADDR(VDIN1_OFFSET) 	///../ucode/register.h
#define VDIN_SCALE_COEF_IDX 0x1200 	///../ucode/register.h
#define P_VDIN_SCALE_COEF_IDX 		CBUS_REG_ADDR(VDIN_SCALE_COEF_IDX) 	///../ucode/register.h
#define VDIN_SCALE_COEF 0x1201 	///../ucode/register.h
#define P_VDIN_SCALE_COEF 		CBUS_REG_ADDR(VDIN_SCALE_COEF) 	///../ucode/register.h
#define VDIN_COM_CTRL0 0x1202 	///../ucode/register.h
#define P_VDIN_COM_CTRL0 		CBUS_REG_ADDR(VDIN_COM_CTRL0) 	///../ucode/register.h
#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS 0x1203 	///../ucode/register.h
#define P_VDIN_ACTIVE_MAX_PIX_CNT_STATUS 		CBUS_REG_ADDR(VDIN_ACTIVE_MAX_PIX_CNT_STATUS) 	///../ucode/register.h
#define VDIN_LCNT_STATUS 0x1204 	///../ucode/register.h
#define P_VDIN_LCNT_STATUS 		CBUS_REG_ADDR(VDIN_LCNT_STATUS) 	///../ucode/register.h
#define VDIN_COM_STATUS0 0x1205 	///../ucode/register.h
#define P_VDIN_COM_STATUS0 		CBUS_REG_ADDR(VDIN_COM_STATUS0) 	///../ucode/register.h
#define VDIN_COM_STATUS1 0x1206 	///../ucode/register.h
#define P_VDIN_COM_STATUS1 		CBUS_REG_ADDR(VDIN_COM_STATUS1) 	///../ucode/register.h
#define VDIN_LCNT_SHADOW_STATUS 0x1207 	///../ucode/register.h
#define P_VDIN_LCNT_SHADOW_STATUS 		CBUS_REG_ADDR(VDIN_LCNT_SHADOW_STATUS) 	///../ucode/register.h
#define VDIN_ASFIFO_CTRL0 0x1208 	///../ucode/register.h
#define P_VDIN_ASFIFO_CTRL0 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL0) 	///../ucode/register.h
#define VDIN_ASFIFO_CTRL1 0x1209 	///../ucode/register.h
#define P_VDIN_ASFIFO_CTRL1 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL1) 	///../ucode/register.h
#define VDIN_WIDTHM1I_WIDTHM1O 0x120a 	///../ucode/register.h
#define P_VDIN_WIDTHM1I_WIDTHM1O 		CBUS_REG_ADDR(VDIN_WIDTHM1I_WIDTHM1O) 	///../ucode/register.h
#define VDIN_SC_MISC_CTRL 0x120b 	///../ucode/register.h
#define P_VDIN_SC_MISC_CTRL 		CBUS_REG_ADDR(VDIN_SC_MISC_CTRL) 	///../ucode/register.h
#define VDIN_HSC_PHASE_STEP 0x120c 	///../ucode/register.h
#define P_VDIN_HSC_PHASE_STEP 		CBUS_REG_ADDR(VDIN_HSC_PHASE_STEP) 	///../ucode/register.h
#define VDIN_HSC_INI_CTRL 0x120d 	///../ucode/register.h
#define P_VDIN_HSC_INI_CTRL 		CBUS_REG_ADDR(VDIN_HSC_INI_CTRL) 	///../ucode/register.h
#define VDIN_COM_STATUS2 0x120e 	///../ucode/register.h
#define P_VDIN_COM_STATUS2 		CBUS_REG_ADDR(VDIN_COM_STATUS2) 	///../ucode/register.h
#define VDIN_ASFIFO_CTRL2 0x120f 	///../ucode/register.h
#define P_VDIN_ASFIFO_CTRL2 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL2) 	///../ucode/register.h
#define VDIN_MATRIX_CTRL 0x1210 	///../ucode/register.h
#define P_VDIN_MATRIX_CTRL 		CBUS_REG_ADDR(VDIN_MATRIX_CTRL) 	///../ucode/register.h
#define VDIN_MATRIX_COEF00_01 0x1211 	///../ucode/register.h
#define P_VDIN_MATRIX_COEF00_01 		CBUS_REG_ADDR(VDIN_MATRIX_COEF00_01) 	///../ucode/register.h
#define VDIN_MATRIX_COEF02_10 0x1212 	///../ucode/register.h
#define P_VDIN_MATRIX_COEF02_10 		CBUS_REG_ADDR(VDIN_MATRIX_COEF02_10) 	///../ucode/register.h
#define VDIN_MATRIX_COEF11_12 0x1213 	///../ucode/register.h
#define P_VDIN_MATRIX_COEF11_12 		CBUS_REG_ADDR(VDIN_MATRIX_COEF11_12) 	///../ucode/register.h
#define VDIN_MATRIX_COEF20_21 0x1214 	///../ucode/register.h
#define P_VDIN_MATRIX_COEF20_21 		CBUS_REG_ADDR(VDIN_MATRIX_COEF20_21) 	///../ucode/register.h
#define VDIN_MATRIX_COEF22 0x1215 	///../ucode/register.h
#define P_VDIN_MATRIX_COEF22 		CBUS_REG_ADDR(VDIN_MATRIX_COEF22) 	///../ucode/register.h
#define VDIN_MATRIX_OFFSET0_1 0x1216 	///../ucode/register.h
#define P_VDIN_MATRIX_OFFSET0_1 		CBUS_REG_ADDR(VDIN_MATRIX_OFFSET0_1) 	///../ucode/register.h
#define VDIN_MATRIX_OFFSET2 0x1217 	///../ucode/register.h
#define P_VDIN_MATRIX_OFFSET2 		CBUS_REG_ADDR(VDIN_MATRIX_OFFSET2) 	///../ucode/register.h
#define VDIN_MATRIX_PRE_OFFSET0_1 0x1218 	///../ucode/register.h
#define P_VDIN_MATRIX_PRE_OFFSET0_1 		CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET0_1) 	///../ucode/register.h
#define VDIN_MATRIX_PRE_OFFSET2 0x1219 	///../ucode/register.h
#define P_VDIN_MATRIX_PRE_OFFSET2 		CBUS_REG_ADDR(VDIN_MATRIX_PRE_OFFSET2) 	///../ucode/register.h
#define VDIN_LFIFO_CTRL 0x121a 	///../ucode/register.h
#define P_VDIN_LFIFO_CTRL 		CBUS_REG_ADDR(VDIN_LFIFO_CTRL) 	///../ucode/register.h
#define VDIN_COM_GCLK_CTRL 0x121b 	///../ucode/register.h
#define P_VDIN_COM_GCLK_CTRL 		CBUS_REG_ADDR(VDIN_COM_GCLK_CTRL) 	///../ucode/register.h
#define VDIN_INTF_WIDTHM1 0x121c 	///../ucode/register.h
#define P_VDIN_INTF_WIDTHM1 		CBUS_REG_ADDR(VDIN_INTF_WIDTHM1) 	///../ucode/register.h
#define VDIN_WR_CTRL2 0x121f 	///../ucode/register.h
#define P_VDIN_WR_CTRL2 		CBUS_REG_ADDR(VDIN_WR_CTRL2) 	///../ucode/register.h
#define VDIN_WR_CTRL 0x1220 	///../ucode/register.h
#define P_VDIN_WR_CTRL 		CBUS_REG_ADDR(VDIN_WR_CTRL) 	///../ucode/register.h
#define VDIN_WR_H_START_END 0x1221 	///../ucode/register.h
#define P_VDIN_WR_H_START_END 		CBUS_REG_ADDR(VDIN_WR_H_START_END) 	///../ucode/register.h
#define VDIN_WR_V_START_END 0x1222 	///../ucode/register.h
#define P_VDIN_WR_V_START_END 		CBUS_REG_ADDR(VDIN_WR_V_START_END) 	///../ucode/register.h
#define VDIN_HIST_CTRL 0x1230 	///../ucode/register.h
#define P_VDIN_HIST_CTRL 		CBUS_REG_ADDR(VDIN_HIST_CTRL) 	///../ucode/register.h
#define VDIN_HIST_H_START_END 0x1231 	///../ucode/register.h
#define P_VDIN_HIST_H_START_END 		CBUS_REG_ADDR(VDIN_HIST_H_START_END) 	///../ucode/register.h
#define VDIN_HIST_V_START_END 0x1232 	///../ucode/register.h
#define P_VDIN_HIST_V_START_END 		CBUS_REG_ADDR(VDIN_HIST_V_START_END) 	///../ucode/register.h
#define VDIN_HIST_MAX_MIN 0x1233 	///../ucode/register.h
#define P_VDIN_HIST_MAX_MIN 		CBUS_REG_ADDR(VDIN_HIST_MAX_MIN) 	///../ucode/register.h
#define VDIN_HIST_SPL_VAL 0x1234 	///../ucode/register.h
#define P_VDIN_HIST_SPL_VAL 		CBUS_REG_ADDR(VDIN_HIST_SPL_VAL) 	///../ucode/register.h
#define VDIN_HIST_SPL_PIX_CNT 0x1235 	///../ucode/register.h
#define P_VDIN_HIST_SPL_PIX_CNT 		CBUS_REG_ADDR(VDIN_HIST_SPL_PIX_CNT) 	///../ucode/register.h
#define VDIN_HIST_CHROMA_SUM 0x1236 	///../ucode/register.h
#define P_VDIN_HIST_CHROMA_SUM 		CBUS_REG_ADDR(VDIN_HIST_CHROMA_SUM) 	///../ucode/register.h
#define VDIN_DNLP_HIST00 0x1237 	///../ucode/register.h
#define P_VDIN_DNLP_HIST00 		CBUS_REG_ADDR(VDIN_DNLP_HIST00) 	///../ucode/register.h
#define VDIN_DNLP_HIST01 0x1238 	///../ucode/register.h
#define P_VDIN_DNLP_HIST01 		CBUS_REG_ADDR(VDIN_DNLP_HIST01) 	///../ucode/register.h
#define VDIN_DNLP_HIST02 0x1239 	///../ucode/register.h
#define P_VDIN_DNLP_HIST02 		CBUS_REG_ADDR(VDIN_DNLP_HIST02) 	///../ucode/register.h
#define VDIN_DNLP_HIST03 0x123a 	///../ucode/register.h
#define P_VDIN_DNLP_HIST03 		CBUS_REG_ADDR(VDIN_DNLP_HIST03) 	///../ucode/register.h
#define VDIN_DNLP_HIST04 0x123b 	///../ucode/register.h
#define P_VDIN_DNLP_HIST04 		CBUS_REG_ADDR(VDIN_DNLP_HIST04) 	///../ucode/register.h
#define VDIN_DNLP_HIST05 0x123c 	///../ucode/register.h
#define P_VDIN_DNLP_HIST05 		CBUS_REG_ADDR(VDIN_DNLP_HIST05) 	///../ucode/register.h
#define VDIN_DNLP_HIST06 0x123d 	///../ucode/register.h
#define P_VDIN_DNLP_HIST06 		CBUS_REG_ADDR(VDIN_DNLP_HIST06) 	///../ucode/register.h
#define VDIN_DNLP_HIST07 0x123e 	///../ucode/register.h
#define P_VDIN_DNLP_HIST07 		CBUS_REG_ADDR(VDIN_DNLP_HIST07) 	///../ucode/register.h
#define VDIN_DNLP_HIST08 0x123f 	///../ucode/register.h
#define P_VDIN_DNLP_HIST08 		CBUS_REG_ADDR(VDIN_DNLP_HIST08) 	///../ucode/register.h
#define VDIN_DNLP_HIST09 0x1240 	///../ucode/register.h
#define P_VDIN_DNLP_HIST09 		CBUS_REG_ADDR(VDIN_DNLP_HIST09) 	///../ucode/register.h
#define VDIN_DNLP_HIST10 0x1241 	///../ucode/register.h
#define P_VDIN_DNLP_HIST10 		CBUS_REG_ADDR(VDIN_DNLP_HIST10) 	///../ucode/register.h
#define VDIN_DNLP_HIST11 0x1242 	///../ucode/register.h
#define P_VDIN_DNLP_HIST11 		CBUS_REG_ADDR(VDIN_DNLP_HIST11) 	///../ucode/register.h
#define VDIN_DNLP_HIST12 0x1243 	///../ucode/register.h
#define P_VDIN_DNLP_HIST12 		CBUS_REG_ADDR(VDIN_DNLP_HIST12) 	///../ucode/register.h
#define VDIN_DNLP_HIST13 0x1244 	///../ucode/register.h
#define P_VDIN_DNLP_HIST13 		CBUS_REG_ADDR(VDIN_DNLP_HIST13) 	///../ucode/register.h
#define VDIN_DNLP_HIST14 0x1245 	///../ucode/register.h
#define P_VDIN_DNLP_HIST14 		CBUS_REG_ADDR(VDIN_DNLP_HIST14) 	///../ucode/register.h
#define VDIN_DNLP_HIST15 0x1246 	///../ucode/register.h
#define P_VDIN_DNLP_HIST15 		CBUS_REG_ADDR(VDIN_DNLP_HIST15) 	///../ucode/register.h
#define VDIN_DNLP_HIST16 0x1247 	///../ucode/register.h
#define P_VDIN_DNLP_HIST16 		CBUS_REG_ADDR(VDIN_DNLP_HIST16) 	///../ucode/register.h
#define VDIN_DNLP_HIST17 0x1248 	///../ucode/register.h
#define P_VDIN_DNLP_HIST17 		CBUS_REG_ADDR(VDIN_DNLP_HIST17) 	///../ucode/register.h
#define VDIN_DNLP_HIST18 0x1249 	///../ucode/register.h
#define P_VDIN_DNLP_HIST18 		CBUS_REG_ADDR(VDIN_DNLP_HIST18) 	///../ucode/register.h
#define VDIN_DNLP_HIST19 0x124a 	///../ucode/register.h
#define P_VDIN_DNLP_HIST19 		CBUS_REG_ADDR(VDIN_DNLP_HIST19) 	///../ucode/register.h
#define VDIN_DNLP_HIST20 0x124b 	///../ucode/register.h
#define P_VDIN_DNLP_HIST20 		CBUS_REG_ADDR(VDIN_DNLP_HIST20) 	///../ucode/register.h
#define VDIN_DNLP_HIST21 0x124c 	///../ucode/register.h
#define P_VDIN_DNLP_HIST21 		CBUS_REG_ADDR(VDIN_DNLP_HIST21) 	///../ucode/register.h
#define VDIN_DNLP_HIST22 0x124d 	///../ucode/register.h
#define P_VDIN_DNLP_HIST22 		CBUS_REG_ADDR(VDIN_DNLP_HIST22) 	///../ucode/register.h
#define VDIN_DNLP_HIST23 0x124e 	///../ucode/register.h
#define P_VDIN_DNLP_HIST23 		CBUS_REG_ADDR(VDIN_DNLP_HIST23) 	///../ucode/register.h
#define VDIN_DNLP_HIST24 0x124f 	///../ucode/register.h
#define P_VDIN_DNLP_HIST24 		CBUS_REG_ADDR(VDIN_DNLP_HIST24) 	///../ucode/register.h
#define VDIN_DNLP_HIST25 0x1250 	///../ucode/register.h
#define P_VDIN_DNLP_HIST25 		CBUS_REG_ADDR(VDIN_DNLP_HIST25) 	///../ucode/register.h
#define VDIN_DNLP_HIST26 0x1251 	///../ucode/register.h
#define P_VDIN_DNLP_HIST26 		CBUS_REG_ADDR(VDIN_DNLP_HIST26) 	///../ucode/register.h
#define VDIN_DNLP_HIST27 0x1252 	///../ucode/register.h
#define P_VDIN_DNLP_HIST27 		CBUS_REG_ADDR(VDIN_DNLP_HIST27) 	///../ucode/register.h
#define VDIN_DNLP_HIST28 0x1253 	///../ucode/register.h
#define P_VDIN_DNLP_HIST28 		CBUS_REG_ADDR(VDIN_DNLP_HIST28) 	///../ucode/register.h
#define VDIN_DNLP_HIST29 0x1254 	///../ucode/register.h
#define P_VDIN_DNLP_HIST29 		CBUS_REG_ADDR(VDIN_DNLP_HIST29) 	///../ucode/register.h
#define VDIN_DNLP_HIST30 0x1255 	///../ucode/register.h
#define P_VDIN_DNLP_HIST30 		CBUS_REG_ADDR(VDIN_DNLP_HIST30) 	///../ucode/register.h
#define VDIN_DNLP_HIST31 0x1256 	///../ucode/register.h
#define P_VDIN_DNLP_HIST31 		CBUS_REG_ADDR(VDIN_DNLP_HIST31) 	///../ucode/register.h
#define VDIN_MEAS_CTRL0 0x125a 	///../ucode/register.h
#define P_VDIN_MEAS_CTRL0 		CBUS_REG_ADDR(VDIN_MEAS_CTRL0) 	///../ucode/register.h
#define VDIN_MEAS_VS_COUNT_HI 0x125b 	///../ucode/register.h
#define P_VDIN_MEAS_VS_COUNT_HI 		CBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_HI) 	///../ucode/register.h
#define VDIN_MEAS_VS_COUNT_LO 0x125c 	///../ucode/register.h
#define P_VDIN_MEAS_VS_COUNT_LO 		CBUS_REG_ADDR(VDIN_MEAS_VS_COUNT_LO) 	///../ucode/register.h
#define VDIN_MEAS_HS_RANGE 0x125d 	///../ucode/register.h
#define P_VDIN_MEAS_HS_RANGE 		CBUS_REG_ADDR(VDIN_MEAS_HS_RANGE) 	///../ucode/register.h
#define VDIN_MEAS_HS_COUNT 0x125e 	///../ucode/register.h
#define P_VDIN_MEAS_HS_COUNT 		CBUS_REG_ADDR(VDIN_MEAS_HS_COUNT) 	///../ucode/register.h
#define VDIN_BLKBAR_CTRL1 0x125f 	///../ucode/register.h
#define P_VDIN_BLKBAR_CTRL1 		CBUS_REG_ADDR(VDIN_BLKBAR_CTRL1) 	///../ucode/register.h
#define VDIN_BLKBAR_CTRL0 0x1260 	///../ucode/register.h
#define P_VDIN_BLKBAR_CTRL0 		CBUS_REG_ADDR(VDIN_BLKBAR_CTRL0) 	///../ucode/register.h
#define VDIN_BLKBAR_H_START_END 0x1261 	///../ucode/register.h
#define P_VDIN_BLKBAR_H_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_H_START_END) 	///../ucode/register.h
#define VDIN_BLKBAR_V_START_END 0x1262 	///../ucode/register.h
#define P_VDIN_BLKBAR_V_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_V_START_END) 	///../ucode/register.h
#define VDIN_BLKBAR_CNT_THRESHOLD 0x1263 	///../ucode/register.h
#define P_VDIN_BLKBAR_CNT_THRESHOLD 		CBUS_REG_ADDR(VDIN_BLKBAR_CNT_THRESHOLD) 	///../ucode/register.h
#define VDIN_BLKBAR_ROW_TH1_TH2 0x1264 	///../ucode/register.h
#define P_VDIN_BLKBAR_ROW_TH1_TH2 		CBUS_REG_ADDR(VDIN_BLKBAR_ROW_TH1_TH2) 	///../ucode/register.h
#define VDIN_BLKBAR_IND_LEFT_START_END 0x1265 	///../ucode/register.h
#define P_VDIN_BLKBAR_IND_LEFT_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT_START_END) 	///../ucode/register.h
#define VDIN_BLKBAR_IND_RIGHT_START_END 0x1266 	///../ucode/register.h
#define P_VDIN_BLKBAR_IND_RIGHT_START_END 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT_START_END) 	///../ucode/register.h
#define VDIN_BLKBAR_IND_LEFT1_CNT 0x1267 	///../ucode/register.h
#define P_VDIN_BLKBAR_IND_LEFT1_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT1_CNT) 	///../ucode/register.h
#define VDIN_BLKBAR_IND_LEFT2_CNT 0x1268 	///../ucode/register.h
#define P_VDIN_BLKBAR_IND_LEFT2_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_LEFT2_CNT) 	///../ucode/register.h
#define VDIN_BLKBAR_IND_RIGHT1_CNT 0x1269 	///../ucode/register.h
#define P_VDIN_BLKBAR_IND_RIGHT1_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT1_CNT) 	///../ucode/register.h
#define VDIN_BLKBAR_IND_RIGHT2_CNT 0x126a 	///../ucode/register.h
#define P_VDIN_BLKBAR_IND_RIGHT2_CNT 		CBUS_REG_ADDR(VDIN_BLKBAR_IND_RIGHT2_CNT) 	///../ucode/register.h
#define VDIN_BLKBAR_STATUS0 0x126b 	///../ucode/register.h
#define P_VDIN_BLKBAR_STATUS0 		CBUS_REG_ADDR(VDIN_BLKBAR_STATUS0) 	///../ucode/register.h
#define VDIN_BLKBAR_STATUS1 0x126c 	///../ucode/register.h
#define P_VDIN_BLKBAR_STATUS1 		CBUS_REG_ADDR(VDIN_BLKBAR_STATUS1) 	///../ucode/register.h
#define VDIN_WIN_H_START_END 0x126d 	///../ucode/register.h
#define P_VDIN_WIN_H_START_END 		CBUS_REG_ADDR(VDIN_WIN_H_START_END) 	///../ucode/register.h
#define VDIN_WIN_V_START_END 0x126e 	///../ucode/register.h
#define P_VDIN_WIN_V_START_END 		CBUS_REG_ADDR(VDIN_WIN_V_START_END) 	///../ucode/register.h
#define VDIN_ASFIFO_CTRL3 0x126f 	///../ucode/register.h
#define P_VDIN_ASFIFO_CTRL3 		CBUS_REG_ADDR(VDIN_ASFIFO_CTRL3) 	///../ucode/register.h
#define DVIN_FRONT_END_CTRL 0x12e0 	///../ucode/register.h
#define P_DVIN_FRONT_END_CTRL 		CBUS_REG_ADDR(DVIN_FRONT_END_CTRL) 	///../ucode/register.h
#define DVIN_HS_LEAD_VS_ODD 0x12e1 	///../ucode/register.h
#define P_DVIN_HS_LEAD_VS_ODD 		CBUS_REG_ADDR(DVIN_HS_LEAD_VS_ODD) 	///../ucode/register.h
#define DVIN_ACTIVE_START_PIX 0x12e2 	///../ucode/register.h
#define P_DVIN_ACTIVE_START_PIX 		CBUS_REG_ADDR(DVIN_ACTIVE_START_PIX) 	///../ucode/register.h
#define DVIN_ACTIVE_START_LINE 0x12e3 	///../ucode/register.h
#define P_DVIN_ACTIVE_START_LINE 		CBUS_REG_ADDR(DVIN_ACTIVE_START_LINE) 	///../ucode/register.h
#define DVIN_DISPLAY_SIZE 0x12e4 	///../ucode/register.h
#define P_DVIN_DISPLAY_SIZE 		CBUS_REG_ADDR(DVIN_DISPLAY_SIZE) 	///../ucode/register.h
#define DVIN_CTRL_STAT 0x12e5 	///../ucode/register.h
#define P_DVIN_CTRL_STAT 		CBUS_REG_ADDR(DVIN_CTRL_STAT) 	///../ucode/register.h
#define VDEC_ASSIST_MMC_CTRL0 0x0001 	///../ucode/register.h
#define P_VDEC_ASSIST_MMC_CTRL0 		DOS_REG_ADDR(VDEC_ASSIST_MMC_CTRL0) 	///../ucode/register.h
#define VDEC_ASSIST_MMC_CTRL1 0x0002 	///../ucode/register.h
#define P_VDEC_ASSIST_MMC_CTRL1 		DOS_REG_ADDR(VDEC_ASSIST_MMC_CTRL1) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT0 0x0025 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT0 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT0) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT1 0x0026 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT1 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT1) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT2 0x0027 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT2 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT2) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT3 0x0028 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT3 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT3) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT4 0x0029 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT4 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT4) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT5 0x002a 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT5 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT5) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT6 0x002b 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT6 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT6) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT7 0x002c 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT7 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT7) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT8 0x002d 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT8 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT8) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INT9 0x002e 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INT9 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INT9) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INTA 0x002f 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INTA 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTA) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INTB 0x0030 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INTB 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTB) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INTC 0x0031 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INTC 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTC) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INTD 0x0032 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INTD 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTD) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INTE 0x0033 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INTE 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTE) 	///../ucode/register.h
#define VDEC_ASSIST_AMR1_INTF 0x0034 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR1_INTF 		DOS_REG_ADDR(VDEC_ASSIST_AMR1_INTF) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT0 0x0035 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT0 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT0) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT1 0x0036 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT1 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT1) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT2 0x0037 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT2 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT2) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT3 0x0038 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT3 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT3) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT4 0x0039 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT4 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT4) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT5 0x003a 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT5 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT5) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT6 0x003b 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT6 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT6) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT7 0x003c 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT7 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT7) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT8 0x003d 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT8 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT8) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INT9 0x003e 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INT9 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INT9) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INTA 0x003f 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INTA 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTA) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INTB 0x0040 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INTB 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTB) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INTC 0x0041 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INTC 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTC) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INTD 0x0042 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INTD 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTD) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INTE 0x0043 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INTE 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTE) 	///../ucode/register.h
#define VDEC_ASSIST_AMR2_INTF 0x0044 	///../ucode/register.h
#define P_VDEC_ASSIST_AMR2_INTF 		DOS_REG_ADDR(VDEC_ASSIST_AMR2_INTF) 	///../ucode/register.h
#define VDEC_ASSIST_TIMER0_LO 0x0060 	///../ucode/register.h
#define P_VDEC_ASSIST_TIMER0_LO 		DOS_REG_ADDR(VDEC_ASSIST_TIMER0_LO) 	///../ucode/register.h
#define VDEC_ASSIST_TIMER0_HI 0x0061 	///../ucode/register.h
#define P_VDEC_ASSIST_TIMER0_HI 		DOS_REG_ADDR(VDEC_ASSIST_TIMER0_HI) 	///../ucode/register.h
#define VDEC_ASSIST_TIMER1_LO 0x0062 	///../ucode/register.h
#define P_VDEC_ASSIST_TIMER1_LO 		DOS_REG_ADDR(VDEC_ASSIST_TIMER1_LO) 	///../ucode/register.h
#define VDEC_ASSIST_TIMER1_HI 0x0063 	///../ucode/register.h
#define P_VDEC_ASSIST_TIMER1_HI 		DOS_REG_ADDR(VDEC_ASSIST_TIMER1_HI) 	///../ucode/register.h
#define VDEC_ASSIST_DMA_INT 0x0064 	///../ucode/register.h
#define P_VDEC_ASSIST_DMA_INT 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT) 	///../ucode/register.h
#define VDEC_ASSIST_DMA_INT_MSK 0x0065 	///../ucode/register.h
#define P_VDEC_ASSIST_DMA_INT_MSK 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT_MSK) 	///../ucode/register.h
#define VDEC_ASSIST_DMA_INT2 0x0066 	///../ucode/register.h
#define P_VDEC_ASSIST_DMA_INT2 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT2) 	///../ucode/register.h
#define VDEC_ASSIST_DMA_INT_MSK2 0x0067 	///../ucode/register.h
#define P_VDEC_ASSIST_DMA_INT_MSK2 		DOS_REG_ADDR(VDEC_ASSIST_DMA_INT_MSK2) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX0_IRQ_REG 0x0070 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX0_IRQ_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_IRQ_REG) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX0_CLR_REG 0x0071 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX0_CLR_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_CLR_REG) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX0_MASK 0x0072 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX0_MASK 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_MASK) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX0_FIQ_SEL 0x0073 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX0_FIQ_SEL 		DOS_REG_ADDR(VDEC_ASSIST_MBOX0_FIQ_SEL) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX1_IRQ_REG 0x0074 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX1_IRQ_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_IRQ_REG) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX1_CLR_REG 0x0075 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX1_CLR_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_CLR_REG) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX1_MASK 0x0076 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX1_MASK 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_MASK) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX1_FIQ_SEL 0x0077 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX1_FIQ_SEL 		DOS_REG_ADDR(VDEC_ASSIST_MBOX1_FIQ_SEL) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX2_IRQ_REG 0x0078 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX2_IRQ_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_IRQ_REG) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX2_CLR_REG 0x0079 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX2_CLR_REG 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_CLR_REG) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX2_MASK 0x007a 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX2_MASK 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_MASK) 	///../ucode/register.h
#define VDEC_ASSIST_MBOX2_FIQ_SEL 0x007b 	///../ucode/register.h
#define P_VDEC_ASSIST_MBOX2_FIQ_SEL 		DOS_REG_ADDR(VDEC_ASSIST_MBOX2_FIQ_SEL) 	///../ucode/register.h
#define MC_CTRL_REG 0x0900 	///../ucode/register.h
#define P_MC_CTRL_REG 		DOS_REG_ADDR(MC_CTRL_REG) 	///../ucode/register.h
#define MC_MB_INFO 0x0901 	///../ucode/register.h
#define P_MC_MB_INFO 		DOS_REG_ADDR(MC_MB_INFO) 	///../ucode/register.h
#define MC_PIC_INFO 0x0902 	///../ucode/register.h
#define P_MC_PIC_INFO 		DOS_REG_ADDR(MC_PIC_INFO) 	///../ucode/register.h
#define MC_HALF_PEL_ONE 0x0903 	///../ucode/register.h
#define P_MC_HALF_PEL_ONE 		DOS_REG_ADDR(MC_HALF_PEL_ONE) 	///../ucode/register.h
#define MC_HALF_PEL_TWO 0x0904 	///../ucode/register.h
#define P_MC_HALF_PEL_TWO 		DOS_REG_ADDR(MC_HALF_PEL_TWO) 	///../ucode/register.h
#define POWER_CTL_MC 0x0905 	///../ucode/register.h
#define P_POWER_CTL_MC 		DOS_REG_ADDR(POWER_CTL_MC) 	///../ucode/register.h
#define MC_CMD 0x0906 	///../ucode/register.h
#define P_MC_CMD 		DOS_REG_ADDR(MC_CMD) 	///../ucode/register.h
#define MC_CTRL0 0x0907 	///../ucode/register.h
#define P_MC_CTRL0 		DOS_REG_ADDR(MC_CTRL0) 	///../ucode/register.h
#define MC_PIC_W_H 0x0908 	///../ucode/register.h
#define P_MC_PIC_W_H 		DOS_REG_ADDR(MC_PIC_W_H) 	///../ucode/register.h
#define MC_STATUS0 0x0909 	///../ucode/register.h
#define P_MC_STATUS0 		DOS_REG_ADDR(MC_STATUS0) 	///../ucode/register.h
#define MC_STATUS1 0x090a 	///../ucode/register.h
#define P_MC_STATUS1 		DOS_REG_ADDR(MC_STATUS1) 	///../ucode/register.h
#define MC_CTRL1 0x090b 	///../ucode/register.h
#define P_MC_CTRL1 		DOS_REG_ADDR(MC_CTRL1) 	///../ucode/register.h
#define MC_MIX_RATIO0 0x090c 	///../ucode/register.h
#define P_MC_MIX_RATIO0 		DOS_REG_ADDR(MC_MIX_RATIO0) 	///../ucode/register.h
#define MC_MIX_RATIO1 0x090d 	///../ucode/register.h
#define P_MC_MIX_RATIO1 		DOS_REG_ADDR(MC_MIX_RATIO1) 	///../ucode/register.h
#define MC_DP_MB_XY 0x090e 	///../ucode/register.h
#define P_MC_DP_MB_XY 		DOS_REG_ADDR(MC_DP_MB_XY) 	///../ucode/register.h
#define MC_OM_MB_XY 0x090f 	///../ucode/register.h
#define P_MC_OM_MB_XY 		DOS_REG_ADDR(MC_OM_MB_XY) 	///../ucode/register.h
#define PSCALE_RST 0x0910 	///../ucode/register.h
#define P_PSCALE_RST 		DOS_REG_ADDR(PSCALE_RST) 	///../ucode/register.h
#define PSCALE_CTRL 0x0911 	///../ucode/register.h
#define P_PSCALE_CTRL 		DOS_REG_ADDR(PSCALE_CTRL) 	///../ucode/register.h
#define PSCALE_PICI_W 0x0912 	///../ucode/register.h
#define P_PSCALE_PICI_W 		DOS_REG_ADDR(PSCALE_PICI_W) 	///../ucode/register.h
#define PSCALE_PICI_H 0x0913 	///../ucode/register.h
#define P_PSCALE_PICI_H 		DOS_REG_ADDR(PSCALE_PICI_H) 	///../ucode/register.h
#define PSCALE_PICO_W 0x0914 	///../ucode/register.h
#define P_PSCALE_PICO_W 		DOS_REG_ADDR(PSCALE_PICO_W) 	///../ucode/register.h
#define PSCALE_PICO_H 0x0915 	///../ucode/register.h
#define P_PSCALE_PICO_H 		DOS_REG_ADDR(PSCALE_PICO_H) 	///../ucode/register.h
#define PSCALE_PICO_START_X 0x0916 	///../ucode/register.h
#define P_PSCALE_PICO_START_X 		DOS_REG_ADDR(PSCALE_PICO_START_X) 	///../ucode/register.h
#define PSCALE_PICO_START_Y 0x0917 	///../ucode/register.h
#define P_PSCALE_PICO_START_Y 		DOS_REG_ADDR(PSCALE_PICO_START_Y) 	///../ucode/register.h
#define PSCALE_DUMMY 0x0918 	///../ucode/register.h
#define P_PSCALE_DUMMY 		DOS_REG_ADDR(PSCALE_DUMMY) 	///../ucode/register.h
#define PSCALE_FILT0_COEF0 0x0919 	///../ucode/register.h
#define P_PSCALE_FILT0_COEF0 		DOS_REG_ADDR(PSCALE_FILT0_COEF0) 	///../ucode/register.h
#define PSCALE_FILT0_COEF1 0x091a 	///../ucode/register.h
#define P_PSCALE_FILT0_COEF1 		DOS_REG_ADDR(PSCALE_FILT0_COEF1) 	///../ucode/register.h
#define PSCALE_CMD_CTRL 0x091b 	///../ucode/register.h
#define P_PSCALE_CMD_CTRL 		DOS_REG_ADDR(PSCALE_CMD_CTRL) 	///../ucode/register.h
#define PSCALE_CMD_BLK_X 0x091c 	///../ucode/register.h
#define P_PSCALE_CMD_BLK_X 		DOS_REG_ADDR(PSCALE_CMD_BLK_X) 	///../ucode/register.h
#define PSCALE_CMD_BLK_Y 0x091d 	///../ucode/register.h
#define P_PSCALE_CMD_BLK_Y 		DOS_REG_ADDR(PSCALE_CMD_BLK_Y) 	///../ucode/register.h
#define PSCALE_STATUS 0x091e 	///../ucode/register.h
#define P_PSCALE_STATUS 		DOS_REG_ADDR(PSCALE_STATUS) 	///../ucode/register.h
#define PSCALE_BMEM_ADDR 0x091f 	///../ucode/register.h
#define P_PSCALE_BMEM_ADDR 		DOS_REG_ADDR(PSCALE_BMEM_ADDR) 	///../ucode/register.h
#define PSCALE_BMEM_DAT 0x0920 	///../ucode/register.h
#define P_PSCALE_BMEM_DAT 		DOS_REG_ADDR(PSCALE_BMEM_DAT) 	///../ucode/register.h
#define PSCALE_DRAM_BUF_CTRL 0x0921 	///../ucode/register.h
#define P_PSCALE_DRAM_BUF_CTRL 		DOS_REG_ADDR(PSCALE_DRAM_BUF_CTRL) 	///../ucode/register.h
#define PSCALE_MCMD_CTRL 0x0922 	///../ucode/register.h
#define P_PSCALE_MCMD_CTRL 		DOS_REG_ADDR(PSCALE_MCMD_CTRL) 	///../ucode/register.h
#define PSCALE_MCMD_XSIZE 0x0923 	///../ucode/register.h
#define P_PSCALE_MCMD_XSIZE 		DOS_REG_ADDR(PSCALE_MCMD_XSIZE) 	///../ucode/register.h
#define PSCALE_MCMD_YSIZE 0x0924 	///../ucode/register.h
#define P_PSCALE_MCMD_YSIZE 		DOS_REG_ADDR(PSCALE_MCMD_YSIZE) 	///../ucode/register.h
#define PSCALE_RBUF_START_BLKX 0x0925 	///../ucode/register.h
#define P_PSCALE_RBUF_START_BLKX 		DOS_REG_ADDR(PSCALE_RBUF_START_BLKX) 	///../ucode/register.h
#define PSCALE_RBUF_START_BLKY 0x0926 	///../ucode/register.h
#define P_PSCALE_RBUF_START_BLKY 		DOS_REG_ADDR(PSCALE_RBUF_START_BLKY) 	///../ucode/register.h
#define PSCALE_PICO_SHIFT_XY 0x0928 	///../ucode/register.h
#define P_PSCALE_PICO_SHIFT_XY 		DOS_REG_ADDR(PSCALE_PICO_SHIFT_XY) 	///../ucode/register.h
#define PSCALE_CTRL1 0x0929 	///../ucode/register.h
#define P_PSCALE_CTRL1 		DOS_REG_ADDR(PSCALE_CTRL1) 	///../ucode/register.h
#define PSCALE_SRCKEY_CTRL0 0x092a 	///../ucode/register.h
#define P_PSCALE_SRCKEY_CTRL0 		DOS_REG_ADDR(PSCALE_SRCKEY_CTRL0) 	///../ucode/register.h
#define PSCALE_SRCKEY_CTRL1 0x092b 	///../ucode/register.h
#define P_PSCALE_SRCKEY_CTRL1 		DOS_REG_ADDR(PSCALE_SRCKEY_CTRL1) 	///../ucode/register.h
#define PSCALE_CANVAS_RD_ADDR 0x092c 	///../ucode/register.h
#define P_PSCALE_CANVAS_RD_ADDR 		DOS_REG_ADDR(PSCALE_CANVAS_RD_ADDR) 	///../ucode/register.h
#define PSCALE_CANVAS_WR_ADDR 0x092d 	///../ucode/register.h
#define P_PSCALE_CANVAS_WR_ADDR 		DOS_REG_ADDR(PSCALE_CANVAS_WR_ADDR) 	///../ucode/register.h
#define PSCALE_CTRL2 0x092e 	///../ucode/register.h
#define P_PSCALE_CTRL2 		DOS_REG_ADDR(PSCALE_CTRL2) 	///../ucode/register.h
#define MC_MPORT_CTRL 0x0940 	///../ucode/register.h
#define P_MC_MPORT_CTRL 		DOS_REG_ADDR(MC_MPORT_CTRL) 	///../ucode/register.h
#define MC_MPORT_DAT 0x0941 	///../ucode/register.h
#define P_MC_MPORT_DAT 		DOS_REG_ADDR(MC_MPORT_DAT) 	///../ucode/register.h
#define MC_WT_PRED_CTRL 0x0942 	///../ucode/register.h
#define P_MC_WT_PRED_CTRL 		DOS_REG_ADDR(MC_WT_PRED_CTRL) 	///../ucode/register.h
#define MC_MBBOT_ST_EVEN_ADDR 0x0944 	///../ucode/register.h
#define P_MC_MBBOT_ST_EVEN_ADDR 		DOS_REG_ADDR(MC_MBBOT_ST_EVEN_ADDR) 	///../ucode/register.h
#define MC_MBBOT_ST_ODD_ADDR 0x0945 	///../ucode/register.h
#define P_MC_MBBOT_ST_ODD_ADDR 		DOS_REG_ADDR(MC_MBBOT_ST_ODD_ADDR) 	///../ucode/register.h
#define MC_DPDN_MB_XY 0x0946 	///../ucode/register.h
#define P_MC_DPDN_MB_XY 		DOS_REG_ADDR(MC_DPDN_MB_XY) 	///../ucode/register.h
#define MC_OMDN_MB_XY 0x0947 	///../ucode/register.h
#define P_MC_OMDN_MB_XY 		DOS_REG_ADDR(MC_OMDN_MB_XY) 	///../ucode/register.h
#define MC_HCMDBUF_H 0x0948 	///../ucode/register.h
#define P_MC_HCMDBUF_H 		DOS_REG_ADDR(MC_HCMDBUF_H) 	///../ucode/register.h
#define MC_HCMDBUF_L 0x0949 	///../ucode/register.h
#define P_MC_HCMDBUF_L 		DOS_REG_ADDR(MC_HCMDBUF_L) 	///../ucode/register.h
#define MC_HCMD_H 0x094a 	///../ucode/register.h
#define P_MC_HCMD_H 		DOS_REG_ADDR(MC_HCMD_H) 	///../ucode/register.h
#define MC_HCMD_L 0x094b 	///../ucode/register.h
#define P_MC_HCMD_L 		DOS_REG_ADDR(MC_HCMD_L) 	///../ucode/register.h
#define MC_IDCT_DAT 0x094c 	///../ucode/register.h
#define P_MC_IDCT_DAT 		DOS_REG_ADDR(MC_IDCT_DAT) 	///../ucode/register.h
#define MC_CTRL_GCLK_CTRL 0x094d 	///../ucode/register.h
#define P_MC_CTRL_GCLK_CTRL 		DOS_REG_ADDR(MC_CTRL_GCLK_CTRL) 	///../ucode/register.h
#define MC_OTHER_GCLK_CTRL 0x094e 	///../ucode/register.h
#define P_MC_OTHER_GCLK_CTRL 		DOS_REG_ADDR(MC_OTHER_GCLK_CTRL) 	///../ucode/register.h
#define MC_CTRL2 0x094f 	///../ucode/register.h
#define P_MC_CTRL2 		DOS_REG_ADDR(MC_CTRL2) 	///../ucode/register.h
#define MDEC_PIC_DC_CTRL 0x098e 	///../ucode/register.h
#define P_MDEC_PIC_DC_CTRL 		DOS_REG_ADDR(MDEC_PIC_DC_CTRL) 	///../ucode/register.h
#define MDEC_PIC_DC_STATUS 0x098f 	///../ucode/register.h
#define P_MDEC_PIC_DC_STATUS 		DOS_REG_ADDR(MDEC_PIC_DC_STATUS) 	///../ucode/register.h
#define ANC0_CANVAS_ADDR 0x0990 	///../ucode/register.h
#define P_ANC0_CANVAS_ADDR 		DOS_REG_ADDR(ANC0_CANVAS_ADDR) 	///../ucode/register.h
#define ANC1_CANVAS_ADDR 0x0991 	///../ucode/register.h
#define P_ANC1_CANVAS_ADDR 		DOS_REG_ADDR(ANC1_CANVAS_ADDR) 	///../ucode/register.h
#define ANC2_CANVAS_ADDR 0x0992 	///../ucode/register.h
#define P_ANC2_CANVAS_ADDR 		DOS_REG_ADDR(ANC2_CANVAS_ADDR) 	///../ucode/register.h
#define ANC3_CANVAS_ADDR 0x0993 	///../ucode/register.h
#define P_ANC3_CANVAS_ADDR 		DOS_REG_ADDR(ANC3_CANVAS_ADDR) 	///../ucode/register.h
#define ANC4_CANVAS_ADDR 0x0994 	///../ucode/register.h
#define P_ANC4_CANVAS_ADDR 		DOS_REG_ADDR(ANC4_CANVAS_ADDR) 	///../ucode/register.h
#define ANC5_CANVAS_ADDR 0x0995 	///../ucode/register.h
#define P_ANC5_CANVAS_ADDR 		DOS_REG_ADDR(ANC5_CANVAS_ADDR) 	///../ucode/register.h
#define ANC6_CANVAS_ADDR 0x0996 	///../ucode/register.h
#define P_ANC6_CANVAS_ADDR 		DOS_REG_ADDR(ANC6_CANVAS_ADDR) 	///../ucode/register.h
#define ANC7_CANVAS_ADDR 0x0997 	///../ucode/register.h
#define P_ANC7_CANVAS_ADDR 		DOS_REG_ADDR(ANC7_CANVAS_ADDR) 	///../ucode/register.h
#define ANC8_CANVAS_ADDR 0x0998 	///../ucode/register.h
#define P_ANC8_CANVAS_ADDR 		DOS_REG_ADDR(ANC8_CANVAS_ADDR) 	///../ucode/register.h
#define ANC9_CANVAS_ADDR 0x0999 	///../ucode/register.h
#define P_ANC9_CANVAS_ADDR 		DOS_REG_ADDR(ANC9_CANVAS_ADDR) 	///../ucode/register.h
#define ANC10_CANVAS_ADDR 0x099a 	///../ucode/register.h
#define P_ANC10_CANVAS_ADDR 		DOS_REG_ADDR(ANC10_CANVAS_ADDR) 	///../ucode/register.h
#define ANC11_CANVAS_ADDR 0x099b 	///../ucode/register.h
#define P_ANC11_CANVAS_ADDR 		DOS_REG_ADDR(ANC11_CANVAS_ADDR) 	///../ucode/register.h
#define ANC12_CANVAS_ADDR 0x099c 	///../ucode/register.h
#define P_ANC12_CANVAS_ADDR 		DOS_REG_ADDR(ANC12_CANVAS_ADDR) 	///../ucode/register.h
#define ANC13_CANVAS_ADDR 0x099d 	///../ucode/register.h
#define P_ANC13_CANVAS_ADDR 		DOS_REG_ADDR(ANC13_CANVAS_ADDR) 	///../ucode/register.h
#define ANC14_CANVAS_ADDR 0x099e 	///../ucode/register.h
#define P_ANC14_CANVAS_ADDR 		DOS_REG_ADDR(ANC14_CANVAS_ADDR) 	///../ucode/register.h
#define ANC15_CANVAS_ADDR 0x099f 	///../ucode/register.h
#define P_ANC15_CANVAS_ADDR 		DOS_REG_ADDR(ANC15_CANVAS_ADDR) 	///../ucode/register.h
#define ANC16_CANVAS_ADDR 0x09a0 	///../ucode/register.h
#define P_ANC16_CANVAS_ADDR 		DOS_REG_ADDR(ANC16_CANVAS_ADDR) 	///../ucode/register.h
#define ANC17_CANVAS_ADDR 0x09a1 	///../ucode/register.h
#define P_ANC17_CANVAS_ADDR 		DOS_REG_ADDR(ANC17_CANVAS_ADDR) 	///../ucode/register.h
#define ANC18_CANVAS_ADDR 0x09a2 	///../ucode/register.h
#define P_ANC18_CANVAS_ADDR 		DOS_REG_ADDR(ANC18_CANVAS_ADDR) 	///../ucode/register.h
#define ANC19_CANVAS_ADDR 0x09a3 	///../ucode/register.h
#define P_ANC19_CANVAS_ADDR 		DOS_REG_ADDR(ANC19_CANVAS_ADDR) 	///../ucode/register.h
#define ANC20_CANVAS_ADDR 0x09a4 	///../ucode/register.h
#define P_ANC20_CANVAS_ADDR 		DOS_REG_ADDR(ANC20_CANVAS_ADDR) 	///../ucode/register.h
#define ANC21_CANVAS_ADDR 0x09a5 	///../ucode/register.h
#define P_ANC21_CANVAS_ADDR 		DOS_REG_ADDR(ANC21_CANVAS_ADDR) 	///../ucode/register.h
#define ANC22_CANVAS_ADDR 0x09a6 	///../ucode/register.h
#define P_ANC22_CANVAS_ADDR 		DOS_REG_ADDR(ANC22_CANVAS_ADDR) 	///../ucode/register.h
#define ANC23_CANVAS_ADDR 0x09a7 	///../ucode/register.h
#define P_ANC23_CANVAS_ADDR 		DOS_REG_ADDR(ANC23_CANVAS_ADDR) 	///../ucode/register.h
#define ANC24_CANVAS_ADDR 0x09a8 	///../ucode/register.h
#define P_ANC24_CANVAS_ADDR 		DOS_REG_ADDR(ANC24_CANVAS_ADDR) 	///../ucode/register.h
#define ANC25_CANVAS_ADDR 0x09a9 	///../ucode/register.h
#define P_ANC25_CANVAS_ADDR 		DOS_REG_ADDR(ANC25_CANVAS_ADDR) 	///../ucode/register.h
#define ANC26_CANVAS_ADDR 0x09aa 	///../ucode/register.h
#define P_ANC26_CANVAS_ADDR 		DOS_REG_ADDR(ANC26_CANVAS_ADDR) 	///../ucode/register.h
#define ANC27_CANVAS_ADDR 0x09ab 	///../ucode/register.h
#define P_ANC27_CANVAS_ADDR 		DOS_REG_ADDR(ANC27_CANVAS_ADDR) 	///../ucode/register.h
#define ANC28_CANVAS_ADDR 0x09ac 	///../ucode/register.h
#define P_ANC28_CANVAS_ADDR 		DOS_REG_ADDR(ANC28_CANVAS_ADDR) 	///../ucode/register.h
#define ANC29_CANVAS_ADDR 0x09ad 	///../ucode/register.h
#define P_ANC29_CANVAS_ADDR 		DOS_REG_ADDR(ANC29_CANVAS_ADDR) 	///../ucode/register.h
#define ANC30_CANVAS_ADDR 0x09ae 	///../ucode/register.h
#define P_ANC30_CANVAS_ADDR 		DOS_REG_ADDR(ANC30_CANVAS_ADDR) 	///../ucode/register.h
#define ANC31_CANVAS_ADDR 0x09af 	///../ucode/register.h
#define P_ANC31_CANVAS_ADDR 		DOS_REG_ADDR(ANC31_CANVAS_ADDR) 	///../ucode/register.h
#define DBKR_CANVAS_ADDR 0x09b0 	///../ucode/register.h
#define P_DBKR_CANVAS_ADDR 		DOS_REG_ADDR(DBKR_CANVAS_ADDR) 	///../ucode/register.h
#define DBKW_CANVAS_ADDR 0x09b1 	///../ucode/register.h
#define P_DBKW_CANVAS_ADDR 		DOS_REG_ADDR(DBKW_CANVAS_ADDR) 	///../ucode/register.h
#define REC_CANVAS_ADDR 0x09b2 	///../ucode/register.h
#define P_REC_CANVAS_ADDR 		DOS_REG_ADDR(REC_CANVAS_ADDR) 	///../ucode/register.h
#define CURR_CANVAS_CTRL 0x09b3 	///../ucode/register.h
#define P_CURR_CANVAS_CTRL 		DOS_REG_ADDR(CURR_CANVAS_CTRL) 	///../ucode/register.h
#define MDEC_PIC_DC_THRESH 0x09b8 	///../ucode/register.h
#define P_MDEC_PIC_DC_THRESH 		DOS_REG_ADDR(MDEC_PIC_DC_THRESH) 	///../ucode/register.h
#define MDEC_PICR_BUF_STATUS 0x09b9 	///../ucode/register.h
#define P_MDEC_PICR_BUF_STATUS 		DOS_REG_ADDR(MDEC_PICR_BUF_STATUS) 	///../ucode/register.h
#define MDEC_PICW_BUF_STATUS 0x09ba 	///../ucode/register.h
#define P_MDEC_PICW_BUF_STATUS 		DOS_REG_ADDR(MDEC_PICW_BUF_STATUS) 	///../ucode/register.h
#define MCW_DBLK_WRRSP_CNT 0x09bb 	///../ucode/register.h
#define P_MCW_DBLK_WRRSP_CNT 		DOS_REG_ADDR(MCW_DBLK_WRRSP_CNT) 	///../ucode/register.h
#define AV_SCRATCH_0 0x09c0 	///../ucode/register.h
#define P_AV_SCRATCH_0 		DOS_REG_ADDR(AV_SCRATCH_0) 	///../ucode/register.h
#define AV_SCRATCH_1 0x09c1 	///../ucode/register.h
#define P_AV_SCRATCH_1 		DOS_REG_ADDR(AV_SCRATCH_1) 	///../ucode/register.h
#define AV_SCRATCH_2 0x09c2 	///../ucode/register.h
#define P_AV_SCRATCH_2 		DOS_REG_ADDR(AV_SCRATCH_2) 	///../ucode/register.h
#define AV_SCRATCH_3 0x09c3 	///../ucode/register.h
#define P_AV_SCRATCH_3 		DOS_REG_ADDR(AV_SCRATCH_3) 	///../ucode/register.h
#define AV_SCRATCH_4 0x09c4 	///../ucode/register.h
#define P_AV_SCRATCH_4 		DOS_REG_ADDR(AV_SCRATCH_4) 	///../ucode/register.h
#define AV_SCRATCH_5 0x09c5 	///../ucode/register.h
#define P_AV_SCRATCH_5 		DOS_REG_ADDR(AV_SCRATCH_5) 	///../ucode/register.h
#define AV_SCRATCH_6 0x09c6 	///../ucode/register.h
#define P_AV_SCRATCH_6 		DOS_REG_ADDR(AV_SCRATCH_6) 	///../ucode/register.h
#define AV_SCRATCH_7 0x09c7 	///../ucode/register.h
#define P_AV_SCRATCH_7 		DOS_REG_ADDR(AV_SCRATCH_7) 	///../ucode/register.h
#define AV_SCRATCH_8 0x09c8 	///../ucode/register.h
#define P_AV_SCRATCH_8 		DOS_REG_ADDR(AV_SCRATCH_8) 	///../ucode/register.h
#define AV_SCRATCH_9 0x09c9 	///../ucode/register.h
#define P_AV_SCRATCH_9 		DOS_REG_ADDR(AV_SCRATCH_9) 	///../ucode/register.h
#define AV_SCRATCH_A 0x09ca 	///../ucode/register.h
#define P_AV_SCRATCH_A 		DOS_REG_ADDR(AV_SCRATCH_A) 	///../ucode/register.h
#define AV_SCRATCH_B 0x09cb 	///../ucode/register.h
#define P_AV_SCRATCH_B 		DOS_REG_ADDR(AV_SCRATCH_B) 	///../ucode/register.h
#define AV_SCRATCH_C 0x09cc 	///../ucode/register.h
#define P_AV_SCRATCH_C 		DOS_REG_ADDR(AV_SCRATCH_C) 	///../ucode/register.h
#define AV_SCRATCH_D 0x09cd 	///../ucode/register.h
#define P_AV_SCRATCH_D 		DOS_REG_ADDR(AV_SCRATCH_D) 	///../ucode/register.h
#define AV_SCRATCH_E 0x09ce 	///../ucode/register.h
#define P_AV_SCRATCH_E 		DOS_REG_ADDR(AV_SCRATCH_E) 	///../ucode/register.h
#define AV_SCRATCH_F 0x09cf 	///../ucode/register.h
#define P_AV_SCRATCH_F 		DOS_REG_ADDR(AV_SCRATCH_F) 	///../ucode/register.h
#define AV_SCRATCH_G 0x09d0 	///../ucode/register.h
#define P_AV_SCRATCH_G 		DOS_REG_ADDR(AV_SCRATCH_G) 	///../ucode/register.h
#define AV_SCRATCH_H 0x09d1 	///../ucode/register.h
#define P_AV_SCRATCH_H 		DOS_REG_ADDR(AV_SCRATCH_H) 	///../ucode/register.h
#define AV_SCRATCH_I 0x09d2 	///../ucode/register.h
#define P_AV_SCRATCH_I 		DOS_REG_ADDR(AV_SCRATCH_I) 	///../ucode/register.h
#define AV_SCRATCH_J 0x09d3 	///../ucode/register.h
#define P_AV_SCRATCH_J 		DOS_REG_ADDR(AV_SCRATCH_J) 	///../ucode/register.h
#define AV_SCRATCH_K 0x09d4 	///../ucode/register.h
#define P_AV_SCRATCH_K 		DOS_REG_ADDR(AV_SCRATCH_K) 	///../ucode/register.h
#define AV_SCRATCH_L 0x09d5 	///../ucode/register.h
#define P_AV_SCRATCH_L 		DOS_REG_ADDR(AV_SCRATCH_L) 	///../ucode/register.h
#define AV_SCRATCH_M 0x09d6 	///../ucode/register.h
#define P_AV_SCRATCH_M 		DOS_REG_ADDR(AV_SCRATCH_M) 	///../ucode/register.h
#define AV_SCRATCH_N 0x09d7 	///../ucode/register.h
#define P_AV_SCRATCH_N 		DOS_REG_ADDR(AV_SCRATCH_N) 	///../ucode/register.h
#define WRRSP_CO_MB 0x09d8 	///../ucode/register.h
#define P_WRRSP_CO_MB 		DOS_REG_ADDR(WRRSP_CO_MB) 	///../ucode/register.h
#define WRRSP_DCAC 0x09d9 	///../ucode/register.h
#define P_WRRSP_DCAC 		DOS_REG_ADDR(WRRSP_DCAC) 	///../ucode/register.h
#define DBLK_RST 0x0950 	///../ucode/register.h
#define P_DBLK_RST 		DOS_REG_ADDR(DBLK_RST) 	///../ucode/register.h
#define DBLK_CTRL 0x0951 	///../ucode/register.h
#define P_DBLK_CTRL 		DOS_REG_ADDR(DBLK_CTRL) 	///../ucode/register.h
#define DBLK_MB_WID_HEIGHT 0x0952 	///../ucode/register.h
#define P_DBLK_MB_WID_HEIGHT 		DOS_REG_ADDR(DBLK_MB_WID_HEIGHT) 	///../ucode/register.h
#define DBLK_STATUS 0x0953 	///../ucode/register.h
#define P_DBLK_STATUS 		DOS_REG_ADDR(DBLK_STATUS) 	///../ucode/register.h
#define DBLK_CMD_CTRL 0x0954 	///../ucode/register.h
#define P_DBLK_CMD_CTRL 		DOS_REG_ADDR(DBLK_CMD_CTRL) 	///../ucode/register.h
#define DBLK_MB_XY 0x0955 	///../ucode/register.h
#define P_DBLK_MB_XY 		DOS_REG_ADDR(DBLK_MB_XY) 	///../ucode/register.h
#define DBLK_QP 0x0956 	///../ucode/register.h
#define P_DBLK_QP 		DOS_REG_ADDR(DBLK_QP) 	///../ucode/register.h
#define DBLK_Y_BHFILT 0x0957 	///../ucode/register.h
#define P_DBLK_Y_BHFILT 		DOS_REG_ADDR(DBLK_Y_BHFILT) 	///../ucode/register.h
#define DBLK_Y_BHFILT_HIGH 0x0958 	///../ucode/register.h
#define P_DBLK_Y_BHFILT_HIGH 		DOS_REG_ADDR(DBLK_Y_BHFILT_HIGH) 	///../ucode/register.h
#define DBLK_Y_BVFILT 0x0959 	///../ucode/register.h
#define P_DBLK_Y_BVFILT 		DOS_REG_ADDR(DBLK_Y_BVFILT) 	///../ucode/register.h
#define DBLK_CB_BFILT 0x095a 	///../ucode/register.h
#define P_DBLK_CB_BFILT 		DOS_REG_ADDR(DBLK_CB_BFILT) 	///../ucode/register.h
#define DBLK_CR_BFILT 0x095b 	///../ucode/register.h
#define P_DBLK_CR_BFILT 		DOS_REG_ADDR(DBLK_CR_BFILT) 	///../ucode/register.h
#define DBLK_Y_HFILT 0x095c 	///../ucode/register.h
#define P_DBLK_Y_HFILT 		DOS_REG_ADDR(DBLK_Y_HFILT) 	///../ucode/register.h
#define DBLK_Y_HFILT_HIGH 0x095d 	///../ucode/register.h
#define P_DBLK_Y_HFILT_HIGH 		DOS_REG_ADDR(DBLK_Y_HFILT_HIGH) 	///../ucode/register.h
#define DBLK_Y_VFILT 0x095e 	///../ucode/register.h
#define P_DBLK_Y_VFILT 		DOS_REG_ADDR(DBLK_Y_VFILT) 	///../ucode/register.h
#define DBLK_CB_FILT 0x095f 	///../ucode/register.h
#define P_DBLK_CB_FILT 		DOS_REG_ADDR(DBLK_CB_FILT) 	///../ucode/register.h
#define DBLK_CR_FILT 0x0960 	///../ucode/register.h
#define P_DBLK_CR_FILT 		DOS_REG_ADDR(DBLK_CR_FILT) 	///../ucode/register.h
#define DBLK_BETAX_QP_SEL 0x0961 	///../ucode/register.h
#define P_DBLK_BETAX_QP_SEL 		DOS_REG_ADDR(DBLK_BETAX_QP_SEL) 	///../ucode/register.h
#define DBLK_CLIP_CTRL0 0x0962 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL0 		DOS_REG_ADDR(DBLK_CLIP_CTRL0) 	///../ucode/register.h
#define DBLK_CLIP_CTRL1 0x0963 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL1 		DOS_REG_ADDR(DBLK_CLIP_CTRL1) 	///../ucode/register.h
#define DBLK_CLIP_CTRL2 0x0964 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL2 		DOS_REG_ADDR(DBLK_CLIP_CTRL2) 	///../ucode/register.h
#define DBLK_CLIP_CTRL3 0x0965 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL3 		DOS_REG_ADDR(DBLK_CLIP_CTRL3) 	///../ucode/register.h
#define DBLK_CLIP_CTRL4 0x0966 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL4 		DOS_REG_ADDR(DBLK_CLIP_CTRL4) 	///../ucode/register.h
#define DBLK_CLIP_CTRL5 0x0967 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL5 		DOS_REG_ADDR(DBLK_CLIP_CTRL5) 	///../ucode/register.h
#define DBLK_CLIP_CTRL6 0x0968 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL6 		DOS_REG_ADDR(DBLK_CLIP_CTRL6) 	///../ucode/register.h
#define DBLK_CLIP_CTRL7 0x0969 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL7 		DOS_REG_ADDR(DBLK_CLIP_CTRL7) 	///../ucode/register.h
#define DBLK_CLIP_CTRL8 0x096a 	///../ucode/register.h
#define P_DBLK_CLIP_CTRL8 		DOS_REG_ADDR(DBLK_CLIP_CTRL8) 	///../ucode/register.h
#define DBLK_STATUS1 0x096b 	///../ucode/register.h
#define P_DBLK_STATUS1 		DOS_REG_ADDR(DBLK_STATUS1) 	///../ucode/register.h
#define DBLK_GCLK_FREE 0x096c 	///../ucode/register.h
#define P_DBLK_GCLK_FREE 		DOS_REG_ADDR(DBLK_GCLK_FREE) 	///../ucode/register.h
#define DBLK_GCLK_OFF 0x096d 	///../ucode/register.h
#define P_DBLK_GCLK_OFF 		DOS_REG_ADDR(DBLK_GCLK_OFF) 	///../ucode/register.h
#define DBLK_AVSFLAGS 0x096e 	///../ucode/register.h
#define P_DBLK_AVSFLAGS 		DOS_REG_ADDR(DBLK_AVSFLAGS) 	///../ucode/register.h
#define DBLK_CBPY 0x0970 	///../ucode/register.h
#define P_DBLK_CBPY 		DOS_REG_ADDR(DBLK_CBPY) 	///../ucode/register.h
#define DBLK_CBPY_ADJ 0x0971 	///../ucode/register.h
#define P_DBLK_CBPY_ADJ 		DOS_REG_ADDR(DBLK_CBPY_ADJ) 	///../ucode/register.h
#define DBLK_CBPC 0x0972 	///../ucode/register.h
#define P_DBLK_CBPC 		DOS_REG_ADDR(DBLK_CBPC) 	///../ucode/register.h
#define DBLK_CBPC_ADJ 0x0973 	///../ucode/register.h
#define P_DBLK_CBPC_ADJ 		DOS_REG_ADDR(DBLK_CBPC_ADJ) 	///../ucode/register.h
#define DBLK_VHMVD 0x0974 	///../ucode/register.h
#define P_DBLK_VHMVD 		DOS_REG_ADDR(DBLK_VHMVD) 	///../ucode/register.h
#define DBLK_STRONG 0x0975 	///../ucode/register.h
#define P_DBLK_STRONG 		DOS_REG_ADDR(DBLK_STRONG) 	///../ucode/register.h
#define DBLK_RV8_QUANT 0x0976 	///../ucode/register.h
#define P_DBLK_RV8_QUANT 		DOS_REG_ADDR(DBLK_RV8_QUANT) 	///../ucode/register.h
#define DBLK_CBUS_HCMD2 0x0977 	///../ucode/register.h
#define P_DBLK_CBUS_HCMD2 		DOS_REG_ADDR(DBLK_CBUS_HCMD2) 	///../ucode/register.h
#define DBLK_CBUS_HCMD1 0x0978 	///../ucode/register.h
#define P_DBLK_CBUS_HCMD1 		DOS_REG_ADDR(DBLK_CBUS_HCMD1) 	///../ucode/register.h
#define DBLK_CBUS_HCMD0 0x0979 	///../ucode/register.h
#define P_DBLK_CBUS_HCMD0 		DOS_REG_ADDR(DBLK_CBUS_HCMD0) 	///../ucode/register.h
#define DBLK_VLD_HCMD2 0x097a 	///../ucode/register.h
#define P_DBLK_VLD_HCMD2 		DOS_REG_ADDR(DBLK_VLD_HCMD2) 	///../ucode/register.h
#define DBLK_VLD_HCMD1 0x097b 	///../ucode/register.h
#define P_DBLK_VLD_HCMD1 		DOS_REG_ADDR(DBLK_VLD_HCMD1) 	///../ucode/register.h
#define DBLK_VLD_HCMD0 0x097c 	///../ucode/register.h
#define P_DBLK_VLD_HCMD0 		DOS_REG_ADDR(DBLK_VLD_HCMD0) 	///../ucode/register.h
#define DBLK_OST_YBASE 0x097d 	///../ucode/register.h
#define P_DBLK_OST_YBASE 		DOS_REG_ADDR(DBLK_OST_YBASE) 	///../ucode/register.h
#define DBLK_OST_CBCRDIFF 0x097e 	///../ucode/register.h
#define P_DBLK_OST_CBCRDIFF 		DOS_REG_ADDR(DBLK_OST_CBCRDIFF) 	///../ucode/register.h
#define DBLK_CTRL1 0x097f 	///../ucode/register.h
#define P_DBLK_CTRL1 		DOS_REG_ADDR(DBLK_CTRL1) 	///../ucode/register.h
#define VLD_STATUS_CTRL 0x0c00 	///../ucode/register.h
#define P_VLD_STATUS_CTRL 		DOS_REG_ADDR(VLD_STATUS_CTRL) 	///../ucode/register.h
#define MPEG1_2_REG 0x0c01 	///../ucode/register.h
#define P_MPEG1_2_REG 		DOS_REG_ADDR(MPEG1_2_REG) 	///../ucode/register.h
#define F_CODE_REG 0x0c02 	///../ucode/register.h
#define P_F_CODE_REG 		DOS_REG_ADDR(F_CODE_REG) 	///../ucode/register.h
#define PIC_HEAD_INFO 0x0c03 	///../ucode/register.h
#define P_PIC_HEAD_INFO 		DOS_REG_ADDR(PIC_HEAD_INFO) 	///../ucode/register.h
#define SLICE_VER_POS_PIC_TYPE 0x0c04 	///../ucode/register.h
#define P_SLICE_VER_POS_PIC_TYPE 		DOS_REG_ADDR(SLICE_VER_POS_PIC_TYPE) 	///../ucode/register.h
#define QP_VALUE_REG 0x0c05 	///../ucode/register.h
#define P_QP_VALUE_REG 		DOS_REG_ADDR(QP_VALUE_REG) 	///../ucode/register.h
#define MBA_INC 0x0c06 	///../ucode/register.h
#define P_MBA_INC 		DOS_REG_ADDR(MBA_INC) 	///../ucode/register.h
#define MB_MOTION_MODE 0x0c07 	///../ucode/register.h
#define P_MB_MOTION_MODE 		DOS_REG_ADDR(MB_MOTION_MODE) 	///../ucode/register.h
#define POWER_CTL_VLD 0x0c08 	///../ucode/register.h
#define P_POWER_CTL_VLD 		DOS_REG_ADDR(POWER_CTL_VLD) 	///../ucode/register.h
#define MB_WIDTH 0x0c09 	///../ucode/register.h
#define P_MB_WIDTH 		DOS_REG_ADDR(MB_WIDTH) 	///../ucode/register.h
#define SLICE_QP 0x0c0a 	///../ucode/register.h
#define P_SLICE_QP 		DOS_REG_ADDR(SLICE_QP) 	///../ucode/register.h
#define PRE_START_CODE 0x0c0b 	///../ucode/register.h
#define P_PRE_START_CODE 		DOS_REG_ADDR(PRE_START_CODE) 	///../ucode/register.h
#define SLICE_START_BYTE_01 0x0c0c 	///../ucode/register.h
#define P_SLICE_START_BYTE_01 		DOS_REG_ADDR(SLICE_START_BYTE_01) 	///../ucode/register.h
#define SLICE_START_BYTE_23 0x0c0d 	///../ucode/register.h
#define P_SLICE_START_BYTE_23 		DOS_REG_ADDR(SLICE_START_BYTE_23) 	///../ucode/register.h
#define RESYNC_MARKER_LENGTH 0x0c0e 	///../ucode/register.h
#define P_RESYNC_MARKER_LENGTH 		DOS_REG_ADDR(RESYNC_MARKER_LENGTH) 	///../ucode/register.h
#define DECODER_BUFFER_INFO 0x0c0f 	///../ucode/register.h
#define P_DECODER_BUFFER_INFO 		DOS_REG_ADDR(DECODER_BUFFER_INFO) 	///../ucode/register.h
#define FST_FOR_MV_X 0x0c10 	///../ucode/register.h
#define P_FST_FOR_MV_X 		DOS_REG_ADDR(FST_FOR_MV_X) 	///../ucode/register.h
#define FST_FOR_MV_Y 0x0c11 	///../ucode/register.h
#define P_FST_FOR_MV_Y 		DOS_REG_ADDR(FST_FOR_MV_Y) 	///../ucode/register.h
#define SCD_FOR_MV_X 0x0c12 	///../ucode/register.h
#define P_SCD_FOR_MV_X 		DOS_REG_ADDR(SCD_FOR_MV_X) 	///../ucode/register.h
#define SCD_FOR_MV_Y 0x0c13 	///../ucode/register.h
#define P_SCD_FOR_MV_Y 		DOS_REG_ADDR(SCD_FOR_MV_Y) 	///../ucode/register.h
#define FST_BAK_MV_X 0x0c14 	///../ucode/register.h
#define P_FST_BAK_MV_X 		DOS_REG_ADDR(FST_BAK_MV_X) 	///../ucode/register.h
#define FST_BAK_MV_Y 0x0c15 	///../ucode/register.h
#define P_FST_BAK_MV_Y 		DOS_REG_ADDR(FST_BAK_MV_Y) 	///../ucode/register.h
#define SCD_BAK_MV_X 0x0c16 	///../ucode/register.h
#define P_SCD_BAK_MV_X 		DOS_REG_ADDR(SCD_BAK_MV_X) 	///../ucode/register.h
#define SCD_BAK_MV_Y 0x0c17 	///../ucode/register.h
#define P_SCD_BAK_MV_Y 		DOS_REG_ADDR(SCD_BAK_MV_Y) 	///../ucode/register.h
#define VLD_DECODE_CONTROL 0x0c18 	///../ucode/register.h
#define P_VLD_DECODE_CONTROL 		DOS_REG_ADDR(VLD_DECODE_CONTROL) 	///../ucode/register.h
#define VLD_REVERVED_19 0x0c19 	///../ucode/register.h
#define P_VLD_REVERVED_19 		DOS_REG_ADDR(VLD_REVERVED_19) 	///../ucode/register.h
#define VIFF_BIT_CNT 0x0c1a 	///../ucode/register.h
#define P_VIFF_BIT_CNT 		DOS_REG_ADDR(VIFF_BIT_CNT) 	///../ucode/register.h
#define BYTE_ALIGN_PEAK_HI 0x0c1b 	///../ucode/register.h
#define P_BYTE_ALIGN_PEAK_HI 		DOS_REG_ADDR(BYTE_ALIGN_PEAK_HI) 	///../ucode/register.h
#define BYTE_ALIGN_PEAK_LO 0x0c1c 	///../ucode/register.h
#define P_BYTE_ALIGN_PEAK_LO 		DOS_REG_ADDR(BYTE_ALIGN_PEAK_LO) 	///../ucode/register.h
#define NEXT_ALIGN_PEAK 0x0c1d 	///../ucode/register.h
#define P_NEXT_ALIGN_PEAK 		DOS_REG_ADDR(NEXT_ALIGN_PEAK) 	///../ucode/register.h
#define VC1_CONTROL_REG 0x0c1e 	///../ucode/register.h
#define P_VC1_CONTROL_REG 		DOS_REG_ADDR(VC1_CONTROL_REG) 	///../ucode/register.h
#define PMV1_X 0x0c20 	///../ucode/register.h
#define P_PMV1_X 		DOS_REG_ADDR(PMV1_X) 	///../ucode/register.h
#define PMV1_Y 0x0c21 	///../ucode/register.h
#define P_PMV1_Y 		DOS_REG_ADDR(PMV1_Y) 	///../ucode/register.h
#define PMV2_X 0x0c22 	///../ucode/register.h
#define P_PMV2_X 		DOS_REG_ADDR(PMV2_X) 	///../ucode/register.h
#define PMV2_Y 0x0c23 	///../ucode/register.h
#define P_PMV2_Y 		DOS_REG_ADDR(PMV2_Y) 	///../ucode/register.h
#define PMV3_X 0x0c24 	///../ucode/register.h
#define P_PMV3_X 		DOS_REG_ADDR(PMV3_X) 	///../ucode/register.h
#define PMV3_Y 0x0c25 	///../ucode/register.h
#define P_PMV3_Y 		DOS_REG_ADDR(PMV3_Y) 	///../ucode/register.h
#define PMV4_X 0x0c26 	///../ucode/register.h
#define P_PMV4_X 		DOS_REG_ADDR(PMV4_X) 	///../ucode/register.h
#define PMV4_Y 0x0c27 	///../ucode/register.h
#define P_PMV4_Y 		DOS_REG_ADDR(PMV4_Y) 	///../ucode/register.h
#define M4_TABLE_SELECT 0x0c28 	///../ucode/register.h
#define P_M4_TABLE_SELECT 		DOS_REG_ADDR(M4_TABLE_SELECT) 	///../ucode/register.h
#define M4_CONTROL_REG 0x0c29 	///../ucode/register.h
#define P_M4_CONTROL_REG 		DOS_REG_ADDR(M4_CONTROL_REG) 	///../ucode/register.h
#define BLOCK_NUM 0x0c2a 	///../ucode/register.h
#define P_BLOCK_NUM 		DOS_REG_ADDR(BLOCK_NUM) 	///../ucode/register.h
#define PATTERN_CODE 0x0c2b 	///../ucode/register.h
#define P_PATTERN_CODE 		DOS_REG_ADDR(PATTERN_CODE) 	///../ucode/register.h
#define MB_INFO 0x0c2c 	///../ucode/register.h
#define P_MB_INFO 		DOS_REG_ADDR(MB_INFO) 	///../ucode/register.h
#define VLD_DC_PRED 0x0c2d 	///../ucode/register.h
#define P_VLD_DC_PRED 		DOS_REG_ADDR(VLD_DC_PRED) 	///../ucode/register.h
#define VLD_ERROR_MASK 0x0c2e 	///../ucode/register.h
#define P_VLD_ERROR_MASK 		DOS_REG_ADDR(VLD_ERROR_MASK) 	///../ucode/register.h
#define VLD_DC_PRED_C 0x0c2f 	///../ucode/register.h
#define P_VLD_DC_PRED_C 		DOS_REG_ADDR(VLD_DC_PRED_C) 	///../ucode/register.h
#define LAST_SLICE_MV_ADDR 0x0c30 	///../ucode/register.h
#define P_LAST_SLICE_MV_ADDR 		DOS_REG_ADDR(LAST_SLICE_MV_ADDR) 	///../ucode/register.h
#define LAST_MVX 0x0c31 	///../ucode/register.h
#define P_LAST_MVX 		DOS_REG_ADDR(LAST_MVX) 	///../ucode/register.h
#define LAST_MVY 0x0c32 	///../ucode/register.h
#define P_LAST_MVY 		DOS_REG_ADDR(LAST_MVY) 	///../ucode/register.h
#define VLD_C38 0x0c38 	///../ucode/register.h
#define P_VLD_C38 		DOS_REG_ADDR(VLD_C38) 	///../ucode/register.h
#define VLD_C39 0x0c39 	///../ucode/register.h
#define P_VLD_C39 		DOS_REG_ADDR(VLD_C39) 	///../ucode/register.h
#define VLD_STATUS 0x0c3a 	///../ucode/register.h
#define P_VLD_STATUS 		DOS_REG_ADDR(VLD_STATUS) 	///../ucode/register.h
#define VLD_SHIFT_STATUS 0x0c3b 	///../ucode/register.h
#define P_VLD_SHIFT_STATUS 		DOS_REG_ADDR(VLD_SHIFT_STATUS) 	///../ucode/register.h
#define VOFF_STATUS 0x0c3c 	///../ucode/register.h
#define P_VOFF_STATUS 		DOS_REG_ADDR(VOFF_STATUS) 	///../ucode/register.h
#define VLD_C3D 0x0c3d 	///../ucode/register.h
#define P_VLD_C3D 		DOS_REG_ADDR(VLD_C3D) 	///../ucode/register.h
#define VLD_DBG_INDEX 0x0c3e 	///../ucode/register.h
#define P_VLD_DBG_INDEX 		DOS_REG_ADDR(VLD_DBG_INDEX) 	///../ucode/register.h
#define VLD_DBG_DATA 0x0c3f 	///../ucode/register.h
#define P_VLD_DBG_DATA 		DOS_REG_ADDR(VLD_DBG_DATA) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_START_PTR 0x0c40 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_START_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_START_PTR) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_CURR_PTR 0x0c41 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_CURR_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_CURR_PTR) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_END_PTR 0x0c42 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_END_PTR 		DOS_REG_ADDR(VLD_MEM_VIFIFO_END_PTR) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_BYTES_AVAIL 0x0c43 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_BYTES_AVAIL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_BYTES_AVAIL) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_CONTROL 0x0c44 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_CONTROL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_CONTROL) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_WP 0x0c45 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_WP 		DOS_REG_ADDR(VLD_MEM_VIFIFO_WP) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_RP 0x0c46 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_RP 		DOS_REG_ADDR(VLD_MEM_VIFIFO_RP) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_LEVEL 0x0c47 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_LEVEL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_LEVEL) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_BUF_CNTL 0x0c48 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_BUF_CNTL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_BUF_CNTL) 	///../ucode/register.h
#define VLD_TIME_STAMP_CNTL 0x0c49 	///../ucode/register.h
#define P_VLD_TIME_STAMP_CNTL 		DOS_REG_ADDR(VLD_TIME_STAMP_CNTL) 	///../ucode/register.h
#define VLD_TIME_STAMP_SYNC_0 0x0c4a 	///../ucode/register.h
#define P_VLD_TIME_STAMP_SYNC_0 		DOS_REG_ADDR(VLD_TIME_STAMP_SYNC_0) 	///../ucode/register.h
#define VLD_TIME_STAMP_SYNC_1 0x0c4b 	///../ucode/register.h
#define P_VLD_TIME_STAMP_SYNC_1 		DOS_REG_ADDR(VLD_TIME_STAMP_SYNC_1) 	///../ucode/register.h
#define VLD_TIME_STAMP_0 0x0c4c 	///../ucode/register.h
#define P_VLD_TIME_STAMP_0 		DOS_REG_ADDR(VLD_TIME_STAMP_0) 	///../ucode/register.h
#define VLD_TIME_STAMP_1 0x0c4d 	///../ucode/register.h
#define P_VLD_TIME_STAMP_1 		DOS_REG_ADDR(VLD_TIME_STAMP_1) 	///../ucode/register.h
#define VLD_TIME_STAMP_2 0x0c4e 	///../ucode/register.h
#define P_VLD_TIME_STAMP_2 		DOS_REG_ADDR(VLD_TIME_STAMP_2) 	///../ucode/register.h
#define VLD_TIME_STAMP_3 0x0c4f 	///../ucode/register.h
#define P_VLD_TIME_STAMP_3 		DOS_REG_ADDR(VLD_TIME_STAMP_3) 	///../ucode/register.h
#define VLD_TIME_STAMP_LENGTH 0x0c50 	///../ucode/register.h
#define P_VLD_TIME_STAMP_LENGTH 		DOS_REG_ADDR(VLD_TIME_STAMP_LENGTH) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_WRAP_COUNT 0x0c51 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_WRAP_COUNT 		DOS_REG_ADDR(VLD_MEM_VIFIFO_WRAP_COUNT) 	///../ucode/register.h
#define VLD_MEM_VIFIFO_MEM_CTL 0x0c52 	///../ucode/register.h
#define P_VLD_MEM_VIFIFO_MEM_CTL 		DOS_REG_ADDR(VLD_MEM_VIFIFO_MEM_CTL) 	///../ucode/register.h
#define VLD_MEM_VBUF_RD_PTR 0x0c53 	///../ucode/register.h
#define P_VLD_MEM_VBUF_RD_PTR 		DOS_REG_ADDR(VLD_MEM_VBUF_RD_PTR) 	///../ucode/register.h
#define VLD_MEM_VBUF2_RD_PTR 0x0c54 	///../ucode/register.h
#define P_VLD_MEM_VBUF2_RD_PTR 		DOS_REG_ADDR(VLD_MEM_VBUF2_RD_PTR) 	///../ucode/register.h
#define VLD_MEM_SWAP_ADDR 0x0c55 	///../ucode/register.h
#define P_VLD_MEM_SWAP_ADDR 		DOS_REG_ADDR(VLD_MEM_SWAP_ADDR) 	///../ucode/register.h
#define VLD_MEM_SWAP_CTL 0x0c56 	///../ucode/register.h
#define P_VLD_MEM_SWAP_CTL 		DOS_REG_ADDR(VLD_MEM_SWAP_CTL) 	///../ucode/register.h
#define VCOP_CTRL_REG 0x0e00 	///../ucode/register.h
#define P_VCOP_CTRL_REG 		DOS_REG_ADDR(VCOP_CTRL_REG) 	///../ucode/register.h
#define QP_CTRL_REG 0x0e01 	///../ucode/register.h
#define P_QP_CTRL_REG 		DOS_REG_ADDR(QP_CTRL_REG) 	///../ucode/register.h
#define INTRA_QUANT_MATRIX 0x0e02 	///../ucode/register.h
#define P_INTRA_QUANT_MATRIX 		DOS_REG_ADDR(INTRA_QUANT_MATRIX) 	///../ucode/register.h
#define NON_I_QUANT_MATRIX 0x0e03 	///../ucode/register.h
#define P_NON_I_QUANT_MATRIX 		DOS_REG_ADDR(NON_I_QUANT_MATRIX) 	///../ucode/register.h
#define DC_SCALER 0x0e04 	///../ucode/register.h
#define P_DC_SCALER 		DOS_REG_ADDR(DC_SCALER) 	///../ucode/register.h
#define DC_AC_CTRL 0x0e05 	///../ucode/register.h
#define P_DC_AC_CTRL 		DOS_REG_ADDR(DC_AC_CTRL) 	///../ucode/register.h
#define DC_AC_SCALE_MUL 0x0e06 	///../ucode/register.h
#define P_DC_AC_SCALE_MUL 		DOS_REG_ADDR(DC_AC_SCALE_MUL) 	///../ucode/register.h
#define DC_AC_SCALE_DIV 0x0e07 	///../ucode/register.h
#define P_DC_AC_SCALE_DIV 		DOS_REG_ADDR(DC_AC_SCALE_DIV) 	///../ucode/register.h
#define POWER_CTL_IQIDCT 0x0e08 	///../ucode/register.h
#define P_POWER_CTL_IQIDCT 		DOS_REG_ADDR(POWER_CTL_IQIDCT) 	///../ucode/register.h
#define RV_AI_Y_X 0x0e09 	///../ucode/register.h
#define P_RV_AI_Y_X 		DOS_REG_ADDR(RV_AI_Y_X) 	///../ucode/register.h
#define RV_AI_U_X 0x0e0a 	///../ucode/register.h
#define P_RV_AI_U_X 		DOS_REG_ADDR(RV_AI_U_X) 	///../ucode/register.h
#define RV_AI_V_X 0x0e0b 	///../ucode/register.h
#define P_RV_AI_V_X 		DOS_REG_ADDR(RV_AI_V_X) 	///../ucode/register.h
#define RV_AI_MB_COUNT 0x0e0c 	///../ucode/register.h
#define P_RV_AI_MB_COUNT 		DOS_REG_ADDR(RV_AI_MB_COUNT) 	///../ucode/register.h
#define NEXT_INTRA_DMA_ADDRESS 0x0e0d 	///../ucode/register.h
#define P_NEXT_INTRA_DMA_ADDRESS 		DOS_REG_ADDR(NEXT_INTRA_DMA_ADDRESS) 	///../ucode/register.h
#define IQIDCT_CONTROL 0x0e0e 	///../ucode/register.h
#define P_IQIDCT_CONTROL 		DOS_REG_ADDR(IQIDCT_CONTROL) 	///../ucode/register.h
#define IQIDCT_DEBUG_INFO_0 0x0e0f 	///../ucode/register.h
#define P_IQIDCT_DEBUG_INFO_0 		DOS_REG_ADDR(IQIDCT_DEBUG_INFO_0) 	///../ucode/register.h
#define DEBLK_CMD 0x0e10 	///../ucode/register.h
#define P_DEBLK_CMD 		DOS_REG_ADDR(DEBLK_CMD) 	///../ucode/register.h
#define IQIDCT_DEBUG_IDCT 0x0e11 	///../ucode/register.h
#define P_IQIDCT_DEBUG_IDCT 		DOS_REG_ADDR(IQIDCT_DEBUG_IDCT) 	///../ucode/register.h
#define DCAC_DMA_CTRL 0x0e12 	///../ucode/register.h
#define P_DCAC_DMA_CTRL 		DOS_REG_ADDR(DCAC_DMA_CTRL) 	///../ucode/register.h
#define DCAC_DMA_ADDRESS 0x0e13 	///../ucode/register.h
#define P_DCAC_DMA_ADDRESS 		DOS_REG_ADDR(DCAC_DMA_ADDRESS) 	///../ucode/register.h
#define DCAC_CPU_ADDRESS 0x0e14 	///../ucode/register.h
#define P_DCAC_CPU_ADDRESS 		DOS_REG_ADDR(DCAC_CPU_ADDRESS) 	///../ucode/register.h
#define DCAC_CPU_DATA 0x0e15 	///../ucode/register.h
#define P_DCAC_CPU_DATA 		DOS_REG_ADDR(DCAC_CPU_DATA) 	///../ucode/register.h
#define DCAC_MB_COUNT 0x0e16 	///../ucode/register.h
#define P_DCAC_MB_COUNT 		DOS_REG_ADDR(DCAC_MB_COUNT) 	///../ucode/register.h
#define IQ_QUANT 0x0e17 	///../ucode/register.h
#define P_IQ_QUANT 		DOS_REG_ADDR(IQ_QUANT) 	///../ucode/register.h
#define VC1_BITPLANE_CTL 0x0e18 	///../ucode/register.h
#define P_VC1_BITPLANE_CTL 		DOS_REG_ADDR(VC1_BITPLANE_CTL) 	///../ucode/register.h
#define MSP 0x0300 	///../ucode/register.h
#define P_MSP 		DOS_REG_ADDR(MSP) 	///../ucode/register.h
#define MPSR 0x0301 	///../ucode/register.h
#define P_MPSR 		DOS_REG_ADDR(MPSR) 	///../ucode/register.h
#define MINT_VEC_BASE 0x0302 	///../ucode/register.h
#define P_MINT_VEC_BASE 		DOS_REG_ADDR(MINT_VEC_BASE) 	///../ucode/register.h
#define MCPU_INTR_GRP 0x0303 	///../ucode/register.h
#define P_MCPU_INTR_GRP 		DOS_REG_ADDR(MCPU_INTR_GRP) 	///../ucode/register.h
#define MCPU_INTR_MSK 0x0304 	///../ucode/register.h
#define P_MCPU_INTR_MSK 		DOS_REG_ADDR(MCPU_INTR_MSK) 	///../ucode/register.h
#define MCPU_INTR_REQ 0x0305 	///../ucode/register.h
#define P_MCPU_INTR_REQ 		DOS_REG_ADDR(MCPU_INTR_REQ) 	///../ucode/register.h
#define MPC_P 0x0306 	///../ucode/register.h
#define P_MPC_P 		DOS_REG_ADDR(MPC_P) 	///../ucode/register.h
#define MPC_D 0x0307 	///../ucode/register.h
#define P_MPC_D 		DOS_REG_ADDR(MPC_D) 	///../ucode/register.h
#define MPC_E 0x0308 	///../ucode/register.h
#define P_MPC_E 		DOS_REG_ADDR(MPC_E) 	///../ucode/register.h
#define MPC_W 0x0309 	///../ucode/register.h
#define P_MPC_W 		DOS_REG_ADDR(MPC_W) 	///../ucode/register.h
#define MINDEX0_REG 0x030a 	///../ucode/register.h
#define P_MINDEX0_REG 		DOS_REG_ADDR(MINDEX0_REG) 	///../ucode/register.h
#define MINDEX1_REG 0x030b 	///../ucode/register.h
#define P_MINDEX1_REG 		DOS_REG_ADDR(MINDEX1_REG) 	///../ucode/register.h
#define MINDEX2_REG 0x030c 	///../ucode/register.h
#define P_MINDEX2_REG 		DOS_REG_ADDR(MINDEX2_REG) 	///../ucode/register.h
#define MINDEX3_REG 0x030d 	///../ucode/register.h
#define P_MINDEX3_REG 		DOS_REG_ADDR(MINDEX3_REG) 	///../ucode/register.h
#define MINDEX4_REG 0x030e 	///../ucode/register.h
#define P_MINDEX4_REG 		DOS_REG_ADDR(MINDEX4_REG) 	///../ucode/register.h
#define MINDEX5_REG 0x030f 	///../ucode/register.h
#define P_MINDEX5_REG 		DOS_REG_ADDR(MINDEX5_REG) 	///../ucode/register.h
#define MINDEX6_REG 0x0310 	///../ucode/register.h
#define P_MINDEX6_REG 		DOS_REG_ADDR(MINDEX6_REG) 	///../ucode/register.h
#define MINDEX7_REG 0x0311 	///../ucode/register.h
#define P_MINDEX7_REG 		DOS_REG_ADDR(MINDEX7_REG) 	///../ucode/register.h
#define MMIN_REG 0x0312 	///../ucode/register.h
#define P_MMIN_REG 		DOS_REG_ADDR(MMIN_REG) 	///../ucode/register.h
#define MMAX_REG 0x0313 	///../ucode/register.h
#define P_MMAX_REG 		DOS_REG_ADDR(MMAX_REG) 	///../ucode/register.h
#define MBREAK0_REG 0x0314 	///../ucode/register.h
#define P_MBREAK0_REG 		DOS_REG_ADDR(MBREAK0_REG) 	///../ucode/register.h
#define MBREAK1_REG 0x0315 	///../ucode/register.h
#define P_MBREAK1_REG 		DOS_REG_ADDR(MBREAK1_REG) 	///../ucode/register.h
#define MBREAK2_REG 0x0316 	///../ucode/register.h
#define P_MBREAK2_REG 		DOS_REG_ADDR(MBREAK2_REG) 	///../ucode/register.h
#define MBREAK3_REG 0x0317 	///../ucode/register.h
#define P_MBREAK3_REG 		DOS_REG_ADDR(MBREAK3_REG) 	///../ucode/register.h
#define MBREAK_TYPE 0x0318 	///../ucode/register.h
#define P_MBREAK_TYPE 		DOS_REG_ADDR(MBREAK_TYPE) 	///../ucode/register.h
#define MBREAK_CTRL 0x0319 	///../ucode/register.h
#define P_MBREAK_CTRL 		DOS_REG_ADDR(MBREAK_CTRL) 	///../ucode/register.h
#define MBREAK_STAUTS 0x031a 	///../ucode/register.h
#define P_MBREAK_STAUTS 		DOS_REG_ADDR(MBREAK_STAUTS) 	///../ucode/register.h
#define MDB_ADDR_REG 0x031b 	///../ucode/register.h
#define P_MDB_ADDR_REG 		DOS_REG_ADDR(MDB_ADDR_REG) 	///../ucode/register.h
#define MDB_DATA_REG 0x031c 	///../ucode/register.h
#define P_MDB_DATA_REG 		DOS_REG_ADDR(MDB_DATA_REG) 	///../ucode/register.h
#define MDB_CTRL 0x031d 	///../ucode/register.h
#define P_MDB_CTRL 		DOS_REG_ADDR(MDB_CTRL) 	///../ucode/register.h
#define MSFTINT0 0x031e 	///../ucode/register.h
#define P_MSFTINT0 		DOS_REG_ADDR(MSFTINT0) 	///../ucode/register.h
#define MSFTINT1 0x031f 	///../ucode/register.h
#define P_MSFTINT1 		DOS_REG_ADDR(MSFTINT1) 	///../ucode/register.h
#define CSP 0x0320 	///../ucode/register.h
#define P_CSP 		DOS_REG_ADDR(CSP) 	///../ucode/register.h
#define CPSR 0x0321 	///../ucode/register.h
#define P_CPSR 		DOS_REG_ADDR(CPSR) 	///../ucode/register.h
#define CINT_VEC_BASE 0x0322 	///../ucode/register.h
#define P_CINT_VEC_BASE 		DOS_REG_ADDR(CINT_VEC_BASE) 	///../ucode/register.h
#define CCPU_INTR_GRP 0x0323 	///../ucode/register.h
#define P_CCPU_INTR_GRP 		DOS_REG_ADDR(CCPU_INTR_GRP) 	///../ucode/register.h
#define CCPU_INTR_MSK 0x0324 	///../ucode/register.h
#define P_CCPU_INTR_MSK 		DOS_REG_ADDR(CCPU_INTR_MSK) 	///../ucode/register.h
#define CCPU_INTR_REQ 0x0325 	///../ucode/register.h
#define P_CCPU_INTR_REQ 		DOS_REG_ADDR(CCPU_INTR_REQ) 	///../ucode/register.h
#define CPC_P 0x0326 	///../ucode/register.h
#define P_CPC_P 		DOS_REG_ADDR(CPC_P) 	///../ucode/register.h
#define CPC_D 0x0327 	///../ucode/register.h
#define P_CPC_D 		DOS_REG_ADDR(CPC_D) 	///../ucode/register.h
#define CPC_E 0x0328 	///../ucode/register.h
#define P_CPC_E 		DOS_REG_ADDR(CPC_E) 	///../ucode/register.h
#define CPC_W 0x0329 	///../ucode/register.h
#define P_CPC_W 		DOS_REG_ADDR(CPC_W) 	///../ucode/register.h
#define CINDEX0_REG 0x032a 	///../ucode/register.h
#define P_CINDEX0_REG 		DOS_REG_ADDR(CINDEX0_REG) 	///../ucode/register.h
#define CINDEX1_REG 0x032b 	///../ucode/register.h
#define P_CINDEX1_REG 		DOS_REG_ADDR(CINDEX1_REG) 	///../ucode/register.h
#define CINDEX2_REG 0x032c 	///../ucode/register.h
#define P_CINDEX2_REG 		DOS_REG_ADDR(CINDEX2_REG) 	///../ucode/register.h
#define CINDEX3_REG 0x032d 	///../ucode/register.h
#define P_CINDEX3_REG 		DOS_REG_ADDR(CINDEX3_REG) 	///../ucode/register.h
#define CINDEX4_REG 0x032e 	///../ucode/register.h
#define P_CINDEX4_REG 		DOS_REG_ADDR(CINDEX4_REG) 	///../ucode/register.h
#define CINDEX5_REG 0x032f 	///../ucode/register.h
#define P_CINDEX5_REG 		DOS_REG_ADDR(CINDEX5_REG) 	///../ucode/register.h
#define CINDEX6_REG 0x0330 	///../ucode/register.h
#define P_CINDEX6_REG 		DOS_REG_ADDR(CINDEX6_REG) 	///../ucode/register.h
#define CINDEX7_REG 0x0331 	///../ucode/register.h
#define P_CINDEX7_REG 		DOS_REG_ADDR(CINDEX7_REG) 	///../ucode/register.h
#define CMIN_REG 0x0332 	///../ucode/register.h
#define P_CMIN_REG 		DOS_REG_ADDR(CMIN_REG) 	///../ucode/register.h
#define CMAX_REG 0x0333 	///../ucode/register.h
#define P_CMAX_REG 		DOS_REG_ADDR(CMAX_REG) 	///../ucode/register.h
#define CBREAK0_REG 0x0334 	///../ucode/register.h
#define P_CBREAK0_REG 		DOS_REG_ADDR(CBREAK0_REG) 	///../ucode/register.h
#define CBREAK1_REG 0x0335 	///../ucode/register.h
#define P_CBREAK1_REG 		DOS_REG_ADDR(CBREAK1_REG) 	///../ucode/register.h
#define CBREAK2_REG 0x0336 	///../ucode/register.h
#define P_CBREAK2_REG 		DOS_REG_ADDR(CBREAK2_REG) 	///../ucode/register.h
#define CBREAK3_REG 0x0337 	///../ucode/register.h
#define P_CBREAK3_REG 		DOS_REG_ADDR(CBREAK3_REG) 	///../ucode/register.h
#define CBREAK_TYPE 0x0338 	///../ucode/register.h
#define P_CBREAK_TYPE 		DOS_REG_ADDR(CBREAK_TYPE) 	///../ucode/register.h
#define CBREAK_CTRL 0x0339 	///../ucode/register.h
#define P_CBREAK_CTRL 		DOS_REG_ADDR(CBREAK_CTRL) 	///../ucode/register.h
#define CBREAK_STAUTS 0x033a 	///../ucode/register.h
#define P_CBREAK_STAUTS 		DOS_REG_ADDR(CBREAK_STAUTS) 	///../ucode/register.h
#define CDB_ADDR_REG 0x033b 	///../ucode/register.h
#define P_CDB_ADDR_REG 		DOS_REG_ADDR(CDB_ADDR_REG) 	///../ucode/register.h
#define CDB_DATA_REG 0x033c 	///../ucode/register.h
#define P_CDB_DATA_REG 		DOS_REG_ADDR(CDB_DATA_REG) 	///../ucode/register.h
#define CDB_CTRL 0x033d 	///../ucode/register.h
#define P_CDB_CTRL 		DOS_REG_ADDR(CDB_CTRL) 	///../ucode/register.h
#define CSFTINT0 0x033e 	///../ucode/register.h
#define P_CSFTINT0 		DOS_REG_ADDR(CSFTINT0) 	///../ucode/register.h
#define CSFTINT1 0x033f 	///../ucode/register.h
#define P_CSFTINT1 		DOS_REG_ADDR(CSFTINT1) 	///../ucode/register.h
#define IMEM_DMA_CTRL 0x0340 	///../ucode/register.h
#define P_IMEM_DMA_CTRL 		DOS_REG_ADDR(IMEM_DMA_CTRL) 	///../ucode/register.h
#define IMEM_DMA_ADR 0x0341 	///../ucode/register.h
#define P_IMEM_DMA_ADR 		DOS_REG_ADDR(IMEM_DMA_ADR) 	///../ucode/register.h
#define IMEM_DMA_COUNT 0x0342 	///../ucode/register.h
#define P_IMEM_DMA_COUNT 		DOS_REG_ADDR(IMEM_DMA_COUNT) 	///../ucode/register.h
#define WRRSP_IMEM 0x0343 	///../ucode/register.h
#define P_WRRSP_IMEM 		DOS_REG_ADDR(WRRSP_IMEM) 	///../ucode/register.h
#define LMEM_DMA_CTRL 0x0350 	///../ucode/register.h
#define P_LMEM_DMA_CTRL 		DOS_REG_ADDR(LMEM_DMA_CTRL) 	///../ucode/register.h
#define LMEM_DMA_ADR 0x0351 	///../ucode/register.h
#define P_LMEM_DMA_ADR 		DOS_REG_ADDR(LMEM_DMA_ADR) 	///../ucode/register.h
#define LMEM_DMA_COUNT 0x0352 	///../ucode/register.h
#define P_LMEM_DMA_COUNT 		DOS_REG_ADDR(LMEM_DMA_COUNT) 	///../ucode/register.h
#define WRRSP_LMEM 0x0353 	///../ucode/register.h
#define P_WRRSP_LMEM 		DOS_REG_ADDR(WRRSP_LMEM) 	///../ucode/register.h
#define MAC_CTRL1 0x0360 	///../ucode/register.h
#define P_MAC_CTRL1 		DOS_REG_ADDR(MAC_CTRL1) 	///../ucode/register.h
#define ACC0REG1 0x0361 	///../ucode/register.h
#define P_ACC0REG1 		DOS_REG_ADDR(ACC0REG1) 	///../ucode/register.h
#define ACC1REG1 0x0362 	///../ucode/register.h
#define P_ACC1REG1 		DOS_REG_ADDR(ACC1REG1) 	///../ucode/register.h
#define MAC_CTRL2 0x0370 	///../ucode/register.h
#define P_MAC_CTRL2 		DOS_REG_ADDR(MAC_CTRL2) 	///../ucode/register.h
#define ACC0REG2 0x0371 	///../ucode/register.h
#define P_ACC0REG2 		DOS_REG_ADDR(ACC0REG2) 	///../ucode/register.h
#define ACC1REG2 0x0372 	///../ucode/register.h
#define P_ACC1REG2 		DOS_REG_ADDR(ACC1REG2) 	///../ucode/register.h
#define CPU_TRACE 0x0380 	///../ucode/register.h
#define P_CPU_TRACE 		DOS_REG_ADDR(CPU_TRACE) 	///../ucode/register.h
#define DOS_SW_RESET0 0x3f00 	///../ucode/register.h
#define P_DOS_SW_RESET0 		DOS_REG_ADDR(DOS_SW_RESET0) 	///../ucode/register.h
#define DOS_GCLK_EN0 0x3f01 	///../ucode/register.h
#define P_DOS_GCLK_EN0 		DOS_REG_ADDR(DOS_GCLK_EN0) 	///../ucode/register.h
#define DOS_GEN_CTRL0 0x3f02 	///../ucode/register.h
#define P_DOS_GEN_CTRL0 		DOS_REG_ADDR(DOS_GEN_CTRL0) 	///../ucode/register.h
#define DOS_APB_ERR_CTRL 0x3f03 	///../ucode/register.h
#define P_DOS_APB_ERR_CTRL 		DOS_REG_ADDR(DOS_APB_ERR_CTRL) 	///../ucode/register.h
#define DOS_APB_ERR_STAT 0x3f04 	///../ucode/register.h
#define P_DOS_APB_ERR_STAT 		DOS_REG_ADDR(DOS_APB_ERR_STAT) 	///../ucode/register.h
#define DOS_SCRATCH0 0x3f10 	///../ucode/register.h
#define P_DOS_SCRATCH0 		DOS_REG_ADDR(DOS_SCRATCH0) 	///../ucode/register.h
#define DOS_SCRATCH1 0x3f11 	///../ucode/register.h
#define P_DOS_SCRATCH1 		DOS_REG_ADDR(DOS_SCRATCH1) 	///../ucode/register.h
#define DOS_SCRATCH2 0x3f12 	///../ucode/register.h
#define P_DOS_SCRATCH2 		DOS_REG_ADDR(DOS_SCRATCH2) 	///../ucode/register.h
#define DOS_SCRATCH3 0x3f13 	///../ucode/register.h
#define P_DOS_SCRATCH3 		DOS_REG_ADDR(DOS_SCRATCH3) 	///../ucode/register.h
#define DOS_SCRATCH4 0x3f14 	///../ucode/register.h
#define P_DOS_SCRATCH4 		DOS_REG_ADDR(DOS_SCRATCH4) 	///../ucode/register.h
#define DOS_SCRATCH5 0x3f15 	///../ucode/register.h
#define P_DOS_SCRATCH5 		DOS_REG_ADDR(DOS_SCRATCH5) 	///../ucode/register.h
#define DOS_SCRATCH6 0x3f16 	///../ucode/register.h
#define P_DOS_SCRATCH6 		DOS_REG_ADDR(DOS_SCRATCH6) 	///../ucode/register.h
#define DOS_SCRATCH7 0x3f17 	///../ucode/register.h
#define P_DOS_SCRATCH7 		DOS_REG_ADDR(DOS_SCRATCH7) 	///../ucode/register.h
#define DOS_SCRATCH8 0x3f18 	///../ucode/register.h
#define P_DOS_SCRATCH8 		DOS_REG_ADDR(DOS_SCRATCH8) 	///../ucode/register.h
#define DOS_SCRATCH9 0x3f19 	///../ucode/register.h
#define P_DOS_SCRATCH9 		DOS_REG_ADDR(DOS_SCRATCH9) 	///../ucode/register.h
#define DOS_SCRATCH10 0x3f1a 	///../ucode/register.h
#define P_DOS_SCRATCH10 		DOS_REG_ADDR(DOS_SCRATCH10) 	///../ucode/register.h
#define DOS_SCRATCH11 0x3f1b 	///../ucode/register.h
#define P_DOS_SCRATCH11 		DOS_REG_ADDR(DOS_SCRATCH11) 	///../ucode/register.h
#define DOS_SCRATCH12 0x3f1c 	///../ucode/register.h
#define P_DOS_SCRATCH12 		DOS_REG_ADDR(DOS_SCRATCH12) 	///../ucode/register.h
#define DOS_SCRATCH13 0x3f1d 	///../ucode/register.h
#define P_DOS_SCRATCH13 		DOS_REG_ADDR(DOS_SCRATCH13) 	///../ucode/register.h
#define DOS_SCRATCH14 0x3f1e 	///../ucode/register.h
#define P_DOS_SCRATCH14 		DOS_REG_ADDR(DOS_SCRATCH14) 	///../ucode/register.h
#define DOS_SCRATCH15 0x3f1f 	///../ucode/register.h
#define P_DOS_SCRATCH15 		DOS_REG_ADDR(DOS_SCRATCH15) 	///../ucode/register.h
#define DOS_SCRATCH16 0x3f20 	///../ucode/register.h
#define P_DOS_SCRATCH16 		DOS_REG_ADDR(DOS_SCRATCH16) 	///../ucode/register.h
#define DOS_SCRATCH17 0x3f21 	///../ucode/register.h
#define P_DOS_SCRATCH17 		DOS_REG_ADDR(DOS_SCRATCH17) 	///../ucode/register.h
#define DOS_SCRATCH18 0x3f22 	///../ucode/register.h
#define P_DOS_SCRATCH18 		DOS_REG_ADDR(DOS_SCRATCH18) 	///../ucode/register.h
#define DOS_SCRATCH19 0x3f23 	///../ucode/register.h
#define P_DOS_SCRATCH19 		DOS_REG_ADDR(DOS_SCRATCH19) 	///../ucode/register.h
#define DOS_SCRATCH20 0x3f24 	///../ucode/register.h
#define P_DOS_SCRATCH20 		DOS_REG_ADDR(DOS_SCRATCH20) 	///../ucode/register.h
#define DOS_SCRATCH21 0x3f25 	///../ucode/register.h
#define P_DOS_SCRATCH21 		DOS_REG_ADDR(DOS_SCRATCH21) 	///../ucode/register.h
#define DOS_SCRATCH22 0x3f26 	///../ucode/register.h
#define P_DOS_SCRATCH22 		DOS_REG_ADDR(DOS_SCRATCH22) 	///../ucode/register.h
#define DOS_SCRATCH23 0x3f27 	///../ucode/register.h
#define P_DOS_SCRATCH23 		DOS_REG_ADDR(DOS_SCRATCH23) 	///../ucode/register.h
#define DOS_SCRATCH24 0x3f28 	///../ucode/register.h
#define P_DOS_SCRATCH24 		DOS_REG_ADDR(DOS_SCRATCH24) 	///../ucode/register.h
#define DOS_SCRATCH25 0x3f29 	///../ucode/register.h
#define P_DOS_SCRATCH25 		DOS_REG_ADDR(DOS_SCRATCH25) 	///../ucode/register.h
#define DOS_SCRATCH26 0x3f2a 	///../ucode/register.h
#define P_DOS_SCRATCH26 		DOS_REG_ADDR(DOS_SCRATCH26) 	///../ucode/register.h
#define DOS_SCRATCH27 0x3f2b 	///../ucode/register.h
#define P_DOS_SCRATCH27 		DOS_REG_ADDR(DOS_SCRATCH27) 	///../ucode/register.h
#define DOS_SCRATCH28 0x3f2c 	///../ucode/register.h
#define P_DOS_SCRATCH28 		DOS_REG_ADDR(DOS_SCRATCH28) 	///../ucode/register.h
#define DOS_SCRATCH29 0x3f2d 	///../ucode/register.h
#define P_DOS_SCRATCH29 		DOS_REG_ADDR(DOS_SCRATCH29) 	///../ucode/register.h
#define DOS_SCRATCH30 0x3f2e 	///../ucode/register.h
#define P_DOS_SCRATCH30 		DOS_REG_ADDR(DOS_SCRATCH30) 	///../ucode/register.h
#define DOS_SCRATCH31 0x3f2f 	///../ucode/register.h
#define P_DOS_SCRATCH31 		DOS_REG_ADDR(DOS_SCRATCH31) 	///../ucode/register.h
#define AIU_958_BPF 0x1500 	///../ucode/register.h
#define P_AIU_958_BPF 		CBUS_REG_ADDR(AIU_958_BPF) 	///../ucode/register.h
#define AIU_958_BRST 0x1501 	///../ucode/register.h
#define P_AIU_958_BRST 		CBUS_REG_ADDR(AIU_958_BRST) 	///../ucode/register.h
#define AIU_958_LENGTH 0x1502 	///../ucode/register.h
#define P_AIU_958_LENGTH 		CBUS_REG_ADDR(AIU_958_LENGTH) 	///../ucode/register.h
#define AIU_958_PADDSIZE 0x1503 	///../ucode/register.h
#define P_AIU_958_PADDSIZE 		CBUS_REG_ADDR(AIU_958_PADDSIZE) 	///../ucode/register.h
#define AIU_958_MISC 0x1504 	///../ucode/register.h
#define P_AIU_958_MISC 		CBUS_REG_ADDR(AIU_958_MISC) 	///../ucode/register.h
#define AIU_958_FORCE_LEFT 0x1505 	///../ucode/register.h
#define P_AIU_958_FORCE_LEFT 		CBUS_REG_ADDR(AIU_958_FORCE_LEFT) 	///../ucode/register.h
#define AIU_958_DISCARD_NUM 0x1506 	///../ucode/register.h
#define P_AIU_958_DISCARD_NUM 		CBUS_REG_ADDR(AIU_958_DISCARD_NUM) 	///../ucode/register.h
#define AIU_958_DCU_FF_CTRL 0x1507 	///../ucode/register.h
#define P_AIU_958_DCU_FF_CTRL 		CBUS_REG_ADDR(AIU_958_DCU_FF_CTRL) 	///../ucode/register.h
#define AIU_958_CHSTAT_L0 0x1508 	///../ucode/register.h
#define P_AIU_958_CHSTAT_L0 		CBUS_REG_ADDR(AIU_958_CHSTAT_L0) 	///../ucode/register.h
#define AIU_958_CHSTAT_L1 0x1509 	///../ucode/register.h
#define P_AIU_958_CHSTAT_L1 		CBUS_REG_ADDR(AIU_958_CHSTAT_L1) 	///../ucode/register.h
#define AIU_958_CTRL 0x150a 	///../ucode/register.h
#define P_AIU_958_CTRL 		CBUS_REG_ADDR(AIU_958_CTRL) 	///../ucode/register.h
#define AIU_958_RPT 0x150b 	///../ucode/register.h
#define P_AIU_958_RPT 		CBUS_REG_ADDR(AIU_958_RPT) 	///../ucode/register.h
#define AIU_I2S_MUTE_SWAP 0x150c 	///../ucode/register.h
#define P_AIU_I2S_MUTE_SWAP 		CBUS_REG_ADDR(AIU_I2S_MUTE_SWAP) 	///../ucode/register.h
#define AIU_I2S_SOURCE_DESC 0x150d 	///../ucode/register.h
#define P_AIU_I2S_SOURCE_DESC 		CBUS_REG_ADDR(AIU_I2S_SOURCE_DESC) 	///../ucode/register.h
#define AIU_I2S_MED_CTRL 0x150e 	///../ucode/register.h
#define P_AIU_I2S_MED_CTRL 		CBUS_REG_ADDR(AIU_I2S_MED_CTRL) 	///../ucode/register.h
#define AIU_I2S_MED_THRESH 0x150f 	///../ucode/register.h
#define P_AIU_I2S_MED_THRESH 		CBUS_REG_ADDR(AIU_I2S_MED_THRESH) 	///../ucode/register.h
#define AIU_I2S_DAC_CFG 0x1510 	///../ucode/register.h
#define P_AIU_I2S_DAC_CFG 		CBUS_REG_ADDR(AIU_I2S_DAC_CFG) 	///../ucode/register.h
#define AIU_I2S_SYNC 0x1511 	///../ucode/register.h
#define P_AIU_I2S_SYNC 		CBUS_REG_ADDR(AIU_I2S_SYNC) 	///../ucode/register.h
#define AIU_I2S_MISC 0x1512 	///../ucode/register.h
#define P_AIU_I2S_MISC 		CBUS_REG_ADDR(AIU_I2S_MISC) 	///../ucode/register.h
#define AIU_I2S_OUT_CFG 0x1513 	///../ucode/register.h
#define P_AIU_I2S_OUT_CFG 		CBUS_REG_ADDR(AIU_I2S_OUT_CFG) 	///../ucode/register.h
#define AIU_I2S_FF_CTRL 0x1514 	///../ucode/register.h
#define P_AIU_I2S_FF_CTRL 		CBUS_REG_ADDR(AIU_I2S_FF_CTRL) 	///../ucode/register.h
#define AIU_RST_SOFT 0x1515 	///../ucode/register.h
#define P_AIU_RST_SOFT 		CBUS_REG_ADDR(AIU_RST_SOFT) 	///../ucode/register.h
#define AIU_CLK_CTRL 0x1516 	///../ucode/register.h
#define P_AIU_CLK_CTRL 		CBUS_REG_ADDR(AIU_CLK_CTRL) 	///../ucode/register.h
#define AIU_MIX_ADCCFG 0x1517 	///../ucode/register.h
#define P_AIU_MIX_ADCCFG 		CBUS_REG_ADDR(AIU_MIX_ADCCFG) 	///../ucode/register.h
#define AIU_MIX_CTRL 0x1518 	///../ucode/register.h
#define P_AIU_MIX_CTRL 		CBUS_REG_ADDR(AIU_MIX_CTRL) 	///../ucode/register.h
#define AIU_CLK_CTRL_MORE 0x1519 	///../ucode/register.h
#define P_AIU_CLK_CTRL_MORE 		CBUS_REG_ADDR(AIU_CLK_CTRL_MORE) 	///../ucode/register.h
#define AIU_958_POP 0x151a 	///../ucode/register.h
#define P_AIU_958_POP 		CBUS_REG_ADDR(AIU_958_POP) 	///../ucode/register.h
#define AIU_MIX_GAIN 0x151b 	///../ucode/register.h
#define P_AIU_MIX_GAIN 		CBUS_REG_ADDR(AIU_MIX_GAIN) 	///../ucode/register.h
#define AIU_958_SYNWORD1 0x151c 	///../ucode/register.h
#define P_AIU_958_SYNWORD1 		CBUS_REG_ADDR(AIU_958_SYNWORD1) 	///../ucode/register.h
#define AIU_958_SYNWORD2 0x151d 	///../ucode/register.h
#define P_AIU_958_SYNWORD2 		CBUS_REG_ADDR(AIU_958_SYNWORD2) 	///../ucode/register.h
#define AIU_958_SYNWORD3 0x151e 	///../ucode/register.h
#define P_AIU_958_SYNWORD3 		CBUS_REG_ADDR(AIU_958_SYNWORD3) 	///../ucode/register.h
#define AIU_958_SYNWORD1_MASK 0x151f 	///../ucode/register.h
#define P_AIU_958_SYNWORD1_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD1_MASK) 	///../ucode/register.h
#define AIU_958_SYNWORD2_MASK 0x1520 	///../ucode/register.h
#define P_AIU_958_SYNWORD2_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD2_MASK) 	///../ucode/register.h
#define AIU_958_SYNWORD3_MASK 0x1521 	///../ucode/register.h
#define P_AIU_958_SYNWORD3_MASK 		CBUS_REG_ADDR(AIU_958_SYNWORD3_MASK) 	///../ucode/register.h
#define AIU_958_FFRDOUT_THD 0x1522 	///../ucode/register.h
#define P_AIU_958_FFRDOUT_THD 		CBUS_REG_ADDR(AIU_958_FFRDOUT_THD) 	///../ucode/register.h
#define AIU_958_LENGTH_PER_PAUSE 0x1523 	///../ucode/register.h
#define P_AIU_958_LENGTH_PER_PAUSE 		CBUS_REG_ADDR(AIU_958_LENGTH_PER_PAUSE) 	///../ucode/register.h
#define AIU_958_PAUSE_NUM 0x1524 	///../ucode/register.h
#define P_AIU_958_PAUSE_NUM 		CBUS_REG_ADDR(AIU_958_PAUSE_NUM) 	///../ucode/register.h
#define AIU_958_PAUSE_PAYLOAD 0x1525 	///../ucode/register.h
#define P_AIU_958_PAUSE_PAYLOAD 		CBUS_REG_ADDR(AIU_958_PAUSE_PAYLOAD) 	///../ucode/register.h
#define AIU_958_AUTO_PAUSE 0x1526 	///../ucode/register.h
#define P_AIU_958_AUTO_PAUSE 		CBUS_REG_ADDR(AIU_958_AUTO_PAUSE) 	///../ucode/register.h
#define AIU_958_PAUSE_PD_LENGTH 0x1527 	///../ucode/register.h
#define P_AIU_958_PAUSE_PD_LENGTH 		CBUS_REG_ADDR(AIU_958_PAUSE_PD_LENGTH) 	///../ucode/register.h
#define AIU_CODEC_DAC_LRCLK_CTRL 0x1528 	///../ucode/register.h
#define P_AIU_CODEC_DAC_LRCLK_CTRL 		CBUS_REG_ADDR(AIU_CODEC_DAC_LRCLK_CTRL) 	///../ucode/register.h
#define AIU_CODEC_ADC_LRCLK_CTRL 0x1529 	///../ucode/register.h
#define P_AIU_CODEC_ADC_LRCLK_CTRL 		CBUS_REG_ADDR(AIU_CODEC_ADC_LRCLK_CTRL) 	///../ucode/register.h
#define AIU_HDMI_CLK_DATA_CTRL 0x152a 	///../ucode/register.h
#define P_AIU_HDMI_CLK_DATA_CTRL 		CBUS_REG_ADDR(AIU_HDMI_CLK_DATA_CTRL) 	///../ucode/register.h
#define AIU_CODEC_CLK_DATA_CTRL 0x152b 	///../ucode/register.h
#define P_AIU_CODEC_CLK_DATA_CTRL 		CBUS_REG_ADDR(AIU_CODEC_CLK_DATA_CTRL) 	///../ucode/register.h
#define AIU_958_CHSTAT_R0 0x1530 	///../ucode/register.h
#define P_AIU_958_CHSTAT_R0 		CBUS_REG_ADDR(AIU_958_CHSTAT_R0) 	///../ucode/register.h
#define AIU_958_CHSTAT_R1 0x1531 	///../ucode/register.h
#define P_AIU_958_CHSTAT_R1 		CBUS_REG_ADDR(AIU_958_CHSTAT_R1) 	///../ucode/register.h
#define AIU_958_VALID_CTRL 0x1532 	///../ucode/register.h
#define P_AIU_958_VALID_CTRL 		CBUS_REG_ADDR(AIU_958_VALID_CTRL) 	///../ucode/register.h
#define AIU_AUDIO_AMP_REG0 0x153c 	///../ucode/register.h
#define P_AIU_AUDIO_AMP_REG0 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG0) 	///../ucode/register.h
#define AIU_AUDIO_AMP_REG1 0x153d 	///../ucode/register.h
#define P_AIU_AUDIO_AMP_REG1 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG1) 	///../ucode/register.h
#define AIU_AUDIO_AMP_REG2 0x153e 	///../ucode/register.h
#define P_AIU_AUDIO_AMP_REG2 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG2) 	///../ucode/register.h
#define AIU_AUDIO_AMP_REG3 0x153f 	///../ucode/register.h
#define P_AIU_AUDIO_AMP_REG3 		CBUS_REG_ADDR(AIU_AUDIO_AMP_REG3) 	///../ucode/register.h
#define AIU_AIFIFO2_CTRL 0x1540 	///../ucode/register.h
#define P_AIU_AIFIFO2_CTRL 		CBUS_REG_ADDR(AIU_AIFIFO2_CTRL) 	///../ucode/register.h
#define AIU_AIFIFO2_STATUS 0x1541 	///../ucode/register.h
#define P_AIU_AIFIFO2_STATUS 		CBUS_REG_ADDR(AIU_AIFIFO2_STATUS) 	///../ucode/register.h
#define AIU_AIFIFO2_GBIT 0x1542 	///../ucode/register.h
#define P_AIU_AIFIFO2_GBIT 		CBUS_REG_ADDR(AIU_AIFIFO2_GBIT) 	///../ucode/register.h
#define AIU_AIFIFO2_CLB 0x1543 	///../ucode/register.h
#define P_AIU_AIFIFO2_CLB 		CBUS_REG_ADDR(AIU_AIFIFO2_CLB) 	///../ucode/register.h
#define AIU_CRC_CTRL 0x1544 	///../ucode/register.h
#define P_AIU_CRC_CTRL 		CBUS_REG_ADDR(AIU_CRC_CTRL) 	///../ucode/register.h
#define AIU_CRC_STATUS 0x1545 	///../ucode/register.h
#define P_AIU_CRC_STATUS 		CBUS_REG_ADDR(AIU_CRC_STATUS) 	///../ucode/register.h
#define AIU_CRC_SHIFT_REG 0x1546 	///../ucode/register.h
#define P_AIU_CRC_SHIFT_REG 		CBUS_REG_ADDR(AIU_CRC_SHIFT_REG) 	///../ucode/register.h
#define AIU_CRC_IREG 0x1547 	///../ucode/register.h
#define P_AIU_CRC_IREG 		CBUS_REG_ADDR(AIU_CRC_IREG) 	///../ucode/register.h
#define AIU_CRC_CAL_REG1 0x1548 	///../ucode/register.h
#define P_AIU_CRC_CAL_REG1 		CBUS_REG_ADDR(AIU_CRC_CAL_REG1) 	///../ucode/register.h
#define AIU_CRC_CAL_REG0 0x1549 	///../ucode/register.h
#define P_AIU_CRC_CAL_REG0 		CBUS_REG_ADDR(AIU_CRC_CAL_REG0) 	///../ucode/register.h
#define AIU_CRC_POLY_COEF1 0x154a 	///../ucode/register.h
#define P_AIU_CRC_POLY_COEF1 		CBUS_REG_ADDR(AIU_CRC_POLY_COEF1) 	///../ucode/register.h
#define AIU_CRC_POLY_COEF0 0x154b 	///../ucode/register.h
#define P_AIU_CRC_POLY_COEF0 		CBUS_REG_ADDR(AIU_CRC_POLY_COEF0) 	///../ucode/register.h
#define AIU_CRC_BIT_SIZE1 0x154c 	///../ucode/register.h
#define P_AIU_CRC_BIT_SIZE1 		CBUS_REG_ADDR(AIU_CRC_BIT_SIZE1) 	///../ucode/register.h
#define AIU_CRC_BIT_SIZE0 0x154d 	///../ucode/register.h
#define P_AIU_CRC_BIT_SIZE0 		CBUS_REG_ADDR(AIU_CRC_BIT_SIZE0) 	///../ucode/register.h
#define AIU_CRC_BIT_CNT1 0x154e 	///../ucode/register.h
#define P_AIU_CRC_BIT_CNT1 		CBUS_REG_ADDR(AIU_CRC_BIT_CNT1) 	///../ucode/register.h
#define AIU_CRC_BIT_CNT0 0x154f 	///../ucode/register.h
#define P_AIU_CRC_BIT_CNT0 		CBUS_REG_ADDR(AIU_CRC_BIT_CNT0) 	///../ucode/register.h
#define AIU_AMCLK_GATE_HI 0x1550 	///../ucode/register.h
#define P_AIU_AMCLK_GATE_HI 		CBUS_REG_ADDR(AIU_AMCLK_GATE_HI) 	///../ucode/register.h
#define AIU_AMCLK_GATE_LO 0x1551 	///../ucode/register.h
#define P_AIU_AMCLK_GATE_LO 		CBUS_REG_ADDR(AIU_AMCLK_GATE_LO) 	///../ucode/register.h
#define AIU_AMCLK_MSR 0x1552 	///../ucode/register.h
#define P_AIU_AMCLK_MSR 		CBUS_REG_ADDR(AIU_AMCLK_MSR) 	///../ucode/register.h
#define AIU_AUDAC_CTRL0 0x1553 	///../ucode/register.h
#define P_AIU_AUDAC_CTRL0 		CBUS_REG_ADDR(AIU_AUDAC_CTRL0) 	///../ucode/register.h
#define AIU_AUDAC_CTRL1 0x1554 	///../ucode/register.h
#define P_AIU_AUDAC_CTRL1 		CBUS_REG_ADDR(AIU_AUDAC_CTRL1) 	///../ucode/register.h
#define AIU_DELTA_SIGMA0 0x1555 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA0 		CBUS_REG_ADDR(AIU_DELTA_SIGMA0) 	///../ucode/register.h
#define AIU_DELTA_SIGMA1 0x1556 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA1 		CBUS_REG_ADDR(AIU_DELTA_SIGMA1) 	///../ucode/register.h
#define AIU_DELTA_SIGMA2 0x1557 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA2 		CBUS_REG_ADDR(AIU_DELTA_SIGMA2) 	///../ucode/register.h
#define AIU_DELTA_SIGMA3 0x1558 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA3 		CBUS_REG_ADDR(AIU_DELTA_SIGMA3) 	///../ucode/register.h
#define AIU_DELTA_SIGMA4 0x1559 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA4 		CBUS_REG_ADDR(AIU_DELTA_SIGMA4) 	///../ucode/register.h
#define AIU_DELTA_SIGMA5 0x155a 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA5 		CBUS_REG_ADDR(AIU_DELTA_SIGMA5) 	///../ucode/register.h
#define AIU_DELTA_SIGMA6 0x155b 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA6 		CBUS_REG_ADDR(AIU_DELTA_SIGMA6) 	///../ucode/register.h
#define AIU_DELTA_SIGMA7 0x155c 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA7 		CBUS_REG_ADDR(AIU_DELTA_SIGMA7) 	///../ucode/register.h
#define AIU_DELTA_SIGMA_LCNTS 0x155d 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA_LCNTS 		CBUS_REG_ADDR(AIU_DELTA_SIGMA_LCNTS) 	///../ucode/register.h
#define AIU_DELTA_SIGMA_RCNTS 0x155e 	///../ucode/register.h
#define P_AIU_DELTA_SIGMA_RCNTS 		CBUS_REG_ADDR(AIU_DELTA_SIGMA_RCNTS) 	///../ucode/register.h
#define AIU_MEM_I2S_START_PTR 0x1560 	///../ucode/register.h
#define P_AIU_MEM_I2S_START_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_START_PTR) 	///../ucode/register.h
#define AIU_MEM_I2S_RD_PTR 0x1561 	///../ucode/register.h
#define P_AIU_MEM_I2S_RD_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_RD_PTR) 	///../ucode/register.h
#define AIU_MEM_I2S_END_PTR 0x1562 	///../ucode/register.h
#define P_AIU_MEM_I2S_END_PTR 		CBUS_REG_ADDR(AIU_MEM_I2S_END_PTR) 	///../ucode/register.h
#define AIU_MEM_I2S_MASKS 0x1563 	///../ucode/register.h
#define P_AIU_MEM_I2S_MASKS 		CBUS_REG_ADDR(AIU_MEM_I2S_MASKS) 	///../ucode/register.h
#define AIU_MEM_I2S_CONTROL 0x1564 	///../ucode/register.h
#define P_AIU_MEM_I2S_CONTROL 		CBUS_REG_ADDR(AIU_MEM_I2S_CONTROL) 	///../ucode/register.h
#define AIU_MEM_IEC958_START_PTR 0x1565 	///../ucode/register.h
#define P_AIU_MEM_IEC958_START_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_START_PTR) 	///../ucode/register.h
#define AIU_MEM_IEC958_RD_PTR 0x1566 	///../ucode/register.h
#define P_AIU_MEM_IEC958_RD_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_RD_PTR) 	///../ucode/register.h
#define AIU_MEM_IEC958_END_PTR 0x1567 	///../ucode/register.h
#define P_AIU_MEM_IEC958_END_PTR 		CBUS_REG_ADDR(AIU_MEM_IEC958_END_PTR) 	///../ucode/register.h
#define AIU_MEM_IEC958_MASKS 0x1568 	///../ucode/register.h
#define P_AIU_MEM_IEC958_MASKS 		CBUS_REG_ADDR(AIU_MEM_IEC958_MASKS) 	///../ucode/register.h
#define AIU_MEM_IEC958_CONTROL 0x1569 	///../ucode/register.h
#define P_AIU_MEM_IEC958_CONTROL 		CBUS_REG_ADDR(AIU_MEM_IEC958_CONTROL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_START_PTR 0x156a 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_START_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_START_PTR) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_CURR_PTR 0x156b 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_CURR_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CURR_PTR) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_END_PTR 0x156c 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_END_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_END_PTR) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_BYTES_AVAIL 0x156d 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_BYTES_AVAIL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BYTES_AVAIL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_CONTROL 0x156e 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_CONTROL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_CONTROL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_MAN_WP 0x156f 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_WP) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_MAN_RP 0x1570 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MAN_RP) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_LEVEL 0x1571 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_LEVEL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_LEVEL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_BUF_CNTL 0x1572 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_CNTL) 	///../ucode/register.h
#define AIU_MEM_I2S_MAN_WP 0x1573 	///../ucode/register.h
#define P_AIU_MEM_I2S_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_I2S_MAN_WP) 	///../ucode/register.h
#define AIU_MEM_I2S_MAN_RP 0x1574 	///../ucode/register.h
#define P_AIU_MEM_I2S_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_I2S_MAN_RP) 	///../ucode/register.h
#define AIU_MEM_I2S_LEVEL 0x1575 	///../ucode/register.h
#define P_AIU_MEM_I2S_LEVEL 		CBUS_REG_ADDR(AIU_MEM_I2S_LEVEL) 	///../ucode/register.h
#define AIU_MEM_I2S_BUF_CNTL 0x1576 	///../ucode/register.h
#define P_AIU_MEM_I2S_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_I2S_BUF_CNTL) 	///../ucode/register.h
#define AIU_MEM_I2S_BUF_WRAP_COUNT 0x1577 	///../ucode/register.h
#define P_AIU_MEM_I2S_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_I2S_BUF_WRAP_COUNT) 	///../ucode/register.h
#define AIU_MEM_I2S_MEM_CTL 0x1578 	///../ucode/register.h
#define P_AIU_MEM_I2S_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_I2S_MEM_CTL) 	///../ucode/register.h
#define AIU_MEM_IEC958_MEM_CTL 0x1579 	///../ucode/register.h
#define P_AIU_MEM_IEC958_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_IEC958_MEM_CTL) 	///../ucode/register.h
#define AIU_MEM_IEC958_WRAP_COUNT 0x157a 	///../ucode/register.h
#define P_AIU_MEM_IEC958_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_IEC958_WRAP_COUNT) 	///../ucode/register.h
#define AIU_MEM_IEC958_IRQ_LEVEL 0x157b 	///../ucode/register.h
#define P_AIU_MEM_IEC958_IRQ_LEVEL 		CBUS_REG_ADDR(AIU_MEM_IEC958_IRQ_LEVEL) 	///../ucode/register.h
#define AIU_MEM_IEC958_MAN_WP 0x157c 	///../ucode/register.h
#define P_AIU_MEM_IEC958_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_WP) 	///../ucode/register.h
#define AIU_MEM_IEC958_MAN_RP 0x157d 	///../ucode/register.h
#define P_AIU_MEM_IEC958_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_IEC958_MAN_RP) 	///../ucode/register.h
#define AIU_MEM_IEC958_LEVEL 0x157e 	///../ucode/register.h
#define P_AIU_MEM_IEC958_LEVEL 		CBUS_REG_ADDR(AIU_MEM_IEC958_LEVEL) 	///../ucode/register.h
#define AIU_MEM_IEC958_BUF_CNTL 0x157f 	///../ucode/register.h
#define P_AIU_MEM_IEC958_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_IEC958_BUF_CNTL) 	///../ucode/register.h
#define AIU_AIFIFO_CTRL 0x1580 	///../ucode/register.h
#define P_AIU_AIFIFO_CTRL 		CBUS_REG_ADDR(AIU_AIFIFO_CTRL) 	///../ucode/register.h
#define AIU_AIFIFO_STATUS 0x1581 	///../ucode/register.h
#define P_AIU_AIFIFO_STATUS 		CBUS_REG_ADDR(AIU_AIFIFO_STATUS) 	///../ucode/register.h
#define AIU_AIFIFO_GBIT 0x1582 	///../ucode/register.h
#define P_AIU_AIFIFO_GBIT 		CBUS_REG_ADDR(AIU_AIFIFO_GBIT) 	///../ucode/register.h
#define AIU_AIFIFO_CLB 0x1583 	///../ucode/register.h
#define P_AIU_AIFIFO_CLB 		CBUS_REG_ADDR(AIU_AIFIFO_CLB) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_START_PTR 0x1584 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_START_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_START_PTR) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_CURR_PTR 0x1585 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_CURR_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_CURR_PTR) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_END_PTR 0x1586 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_END_PTR 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_END_PTR) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_BYTES_AVAIL 0x1587 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_BYTES_AVAIL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BYTES_AVAIL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_CONTROL 0x1588 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_CONTROL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_CONTROL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_MAN_WP 0x1589 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_MAN_WP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_WP) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_MAN_RP 0x158a 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_MAN_RP 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MAN_RP) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_LEVEL 0x158b 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_LEVEL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_LEVEL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_BUF_CNTL 0x158c 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_BUF_CNTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_CNTL) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT 0x158d 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_BUF_WRAP_COUNT) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 0x158e 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_BUF_WRAP_COUNT 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_BUF_WRAP_COUNT) 	///../ucode/register.h
#define AIU_MEM_AIFIFO_MEM_CTL 0x158f 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO_MEM_CTL) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_CNTL 0x1590 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_CNTL 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_CNTL) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_SYNC_0 0x1591 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_0) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_SYNC_1 0x1592 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_SYNC_1) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_0 0x1593 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_0 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_0) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_1 0x1594 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_1 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_1) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_2 0x1595 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_2 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_2) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_3 0x1596 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_3 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_3) 	///../ucode/register.h
#define AIFIFO_TIME_STAMP_LENGTH 0x1597 	///../ucode/register.h
#define P_AIFIFO_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(AIFIFO_TIME_STAMP_LENGTH) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_CNTL 0x1598 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_CNTL 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_CNTL) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_SYNC_0 0x1599 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_0) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_SYNC_1 0x159a 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_SYNC_1) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_0 0x159b 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_0 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_0) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_1 0x159c 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_1 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_1) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_2 0x159d 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_2 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_2) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_3 0x159e 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_3 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_3) 	///../ucode/register.h
#define AIFIFO2_TIME_STAMP_LENGTH 0x159f 	///../ucode/register.h
#define P_AIFIFO2_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(AIFIFO2_TIME_STAMP_LENGTH) 	///../ucode/register.h
#define IEC958_TIME_STAMP_CNTL 0x15a0 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_CNTL 		CBUS_REG_ADDR(IEC958_TIME_STAMP_CNTL) 	///../ucode/register.h
#define IEC958_TIME_STAMP_SYNC_0 0x15a1 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_SYNC_0 		CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_0) 	///../ucode/register.h
#define IEC958_TIME_STAMP_SYNC_1 0x15a2 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_SYNC_1 		CBUS_REG_ADDR(IEC958_TIME_STAMP_SYNC_1) 	///../ucode/register.h
#define IEC958_TIME_STAMP_0 0x15a3 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_0 		CBUS_REG_ADDR(IEC958_TIME_STAMP_0) 	///../ucode/register.h
#define IEC958_TIME_STAMP_1 0x15a4 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_1 		CBUS_REG_ADDR(IEC958_TIME_STAMP_1) 	///../ucode/register.h
#define IEC958_TIME_STAMP_2 0x15a5 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_2 		CBUS_REG_ADDR(IEC958_TIME_STAMP_2) 	///../ucode/register.h
#define IEC958_TIME_STAMP_3 0x15a6 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_3 		CBUS_REG_ADDR(IEC958_TIME_STAMP_3) 	///../ucode/register.h
#define IEC958_TIME_STAMP_LENGTH 0x15a7 	///../ucode/register.h
#define P_IEC958_TIME_STAMP_LENGTH 		CBUS_REG_ADDR(IEC958_TIME_STAMP_LENGTH) 	///../ucode/register.h
#define AIU_MEM_AIFIFO2_MEM_CTL 0x15a8 	///../ucode/register.h
#define P_AIU_MEM_AIFIFO2_MEM_CTL 		CBUS_REG_ADDR(AIU_MEM_AIFIFO2_MEM_CTL) 	///../ucode/register.h
#define AIU_I2S_CBUS_DDR_CNTL 0x15a9 	///../ucode/register.h
#define P_AIU_I2S_CBUS_DDR_CNTL 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_CNTL) 	///../ucode/register.h
#define AIU_I2S_CBUS_DDR_WDATA 0x15aa 	///../ucode/register.h
#define P_AIU_I2S_CBUS_DDR_WDATA 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_WDATA) 	///../ucode/register.h
#define AIU_I2S_CBUS_DDR_ADDR 0x15ab 	///../ucode/register.h
#define P_AIU_I2S_CBUS_DDR_ADDR 		CBUS_REG_ADDR(AIU_I2S_CBUS_DDR_ADDR) 	///../ucode/register.h
#define AIADR 0x1738 	///../ucode/register.h
#define P_AIADR 		CBUS_REG_ADDR(AIADR) 	///../ucode/register.h
#define AICSR 0x1739 	///../ucode/register.h
#define P_AICSR 		CBUS_REG_ADDR(AICSR) 	///../ucode/register.h
#define AIDAT 0x173a 	///../ucode/register.h
#define P_AIDAT 		CBUS_REG_ADDR(AIDAT) 	///../ucode/register.h
#define AIGBIT 0x173b 	///../ucode/register.h
#define P_AIGBIT 		CBUS_REG_ADDR(AIGBIT) 	///../ucode/register.h
#define AICLB 0x173c 	///../ucode/register.h
#define P_AICLB 		CBUS_REG_ADDR(AICLB) 	///../ucode/register.h
#define HD0 0x1780 	///../ucode/register.h
#define P_HD0 		CBUS_REG_ADDR(HD0) 	///../ucode/register.h
#define HD1 0x1781 	///../ucode/register.h
#define P_HD1 		CBUS_REG_ADDR(HD1) 	///../ucode/register.h
#define SHD0 0x1782 	///../ucode/register.h
#define P_SHD0 		CBUS_REG_ADDR(SHD0) 	///../ucode/register.h
#define SHD1 0x1783 	///../ucode/register.h
#define P_SHD1 		CBUS_REG_ADDR(SHD1) 	///../ucode/register.h
#define SYND 0x1784 	///../ucode/register.h
#define P_SYND 		CBUS_REG_ADDR(SYND) 	///../ucode/register.h
#define ECDCT 0x1785 	///../ucode/register.h
#define P_ECDCT 		CBUS_REG_ADDR(ECDCT) 	///../ucode/register.h
#define ECDSTAT 0x1786 	///../ucode/register.h
#define P_ECDSTAT 		CBUS_REG_ADDR(ECDSTAT) 	///../ucode/register.h
#define CTR0 0x1787 	///../ucode/register.h
#define P_CTR0 		CBUS_REG_ADDR(CTR0) 	///../ucode/register.h
#define CTR1 0x1788 	///../ucode/register.h
#define P_CTR1 		CBUS_REG_ADDR(CTR1) 	///../ucode/register.h
#define CTR2 0x1789 	///../ucode/register.h
#define P_CTR2 		CBUS_REG_ADDR(CTR2) 	///../ucode/register.h
#define STAT0 0x178a 	///../ucode/register.h
#define P_STAT0 		CBUS_REG_ADDR(STAT0) 	///../ucode/register.h
#define INT 0x178b 	///../ucode/register.h
#define P_INT 		CBUS_REG_ADDR(INT) 	///../ucode/register.h
#define TCTR0 0x178c 	///../ucode/register.h
#define P_TCTR0 		CBUS_REG_ADDR(TCTR0) 	///../ucode/register.h
#define TSTAT0 0x178d 	///../ucode/register.h
#define P_TSTAT0 		CBUS_REG_ADDR(TSTAT0) 	///../ucode/register.h
#define TSTAT1 0x178e 	///../ucode/register.h
#define P_TSTAT1 		CBUS_REG_ADDR(TSTAT1) 	///../ucode/register.h
#define VPP_DUMMY_DATA 0x1d00 	///../ucode/register.h
#define P_VPP_DUMMY_DATA 		CBUS_REG_ADDR(VPP_DUMMY_DATA) 	///../ucode/register.h
#define VPP_LINE_IN_LENGTH 0x1d01 	///../ucode/register.h
#define P_VPP_LINE_IN_LENGTH 		CBUS_REG_ADDR(VPP_LINE_IN_LENGTH) 	///../ucode/register.h
#define VPP_PIC_IN_HEIGHT 0x1d02 	///../ucode/register.h
#define P_VPP_PIC_IN_HEIGHT 		CBUS_REG_ADDR(VPP_PIC_IN_HEIGHT) 	///../ucode/register.h
#define VPP_SCALE_COEF_IDX 0x1d03 	///../ucode/register.h
#define P_VPP_SCALE_COEF_IDX 		CBUS_REG_ADDR(VPP_SCALE_COEF_IDX) 	///../ucode/register.h
#define VPP_SCALE_COEF 0x1d04 	///../ucode/register.h
#define P_VPP_SCALE_COEF 		CBUS_REG_ADDR(VPP_SCALE_COEF) 	///../ucode/register.h
#define VPP_VSC_REGION12_STARTP 0x1d05 	///../ucode/register.h
#define P_VPP_VSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP_VSC_REGION12_STARTP) 	///../ucode/register.h
#define VPP_VSC_REGION34_STARTP 0x1d06 	///../ucode/register.h
#define P_VPP_VSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP_VSC_REGION34_STARTP) 	///../ucode/register.h
#define VPP_VSC_REGION4_ENDP 0x1d07 	///../ucode/register.h
#define P_VPP_VSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP_VSC_REGION4_ENDP) 	///../ucode/register.h
#define VPP_VSC_START_PHASE_STEP 0x1d08 	///../ucode/register.h
#define P_VPP_VSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP_VSC_START_PHASE_STEP) 	///../ucode/register.h
#define VPP_VSC_REGION0_PHASE_SLOPE 0x1d09 	///../ucode/register.h
#define P_VPP_VSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION0_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_VSC_REGION1_PHASE_SLOPE 0x1d0a 	///../ucode/register.h
#define P_VPP_VSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION1_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_VSC_REGION3_PHASE_SLOPE 0x1d0b 	///../ucode/register.h
#define P_VPP_VSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION3_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_VSC_REGION4_PHASE_SLOPE 0x1d0c 	///../ucode/register.h
#define P_VPP_VSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_VSC_REGION4_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_VSC_PHASE_CTRL 0x1d0d 	///../ucode/register.h
#define P_VPP_VSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP_VSC_PHASE_CTRL) 	///../ucode/register.h
#define VPP_VSC_INI_PHASE 0x1d0e 	///../ucode/register.h
#define P_VPP_VSC_INI_PHASE 		CBUS_REG_ADDR(VPP_VSC_INI_PHASE) 	///../ucode/register.h
#define VPP_HSC_REGION12_STARTP 0x1d10 	///../ucode/register.h
#define P_VPP_HSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP_HSC_REGION12_STARTP) 	///../ucode/register.h
#define VPP_HSC_REGION34_STARTP 0x1d11 	///../ucode/register.h
#define P_VPP_HSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP_HSC_REGION34_STARTP) 	///../ucode/register.h
#define VPP_HSC_REGION4_ENDP 0x1d12 	///../ucode/register.h
#define P_VPP_HSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP_HSC_REGION4_ENDP) 	///../ucode/register.h
#define VPP_HSC_START_PHASE_STEP 0x1d13 	///../ucode/register.h
#define P_VPP_HSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP_HSC_START_PHASE_STEP) 	///../ucode/register.h
#define VPP_HSC_REGION0_PHASE_SLOPE 0x1d14 	///../ucode/register.h
#define P_VPP_HSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION0_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_HSC_REGION1_PHASE_SLOPE 0x1d15 	///../ucode/register.h
#define P_VPP_HSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION1_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_HSC_REGION3_PHASE_SLOPE 0x1d16 	///../ucode/register.h
#define P_VPP_HSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION3_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_HSC_REGION4_PHASE_SLOPE 0x1d17 	///../ucode/register.h
#define P_VPP_HSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP_HSC_REGION4_PHASE_SLOPE) 	///../ucode/register.h
#define VPP_HSC_PHASE_CTRL 0x1d18 	///../ucode/register.h
#define P_VPP_HSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP_HSC_PHASE_CTRL) 	///../ucode/register.h
#define VPP_SC_MISC 0x1d19 	///../ucode/register.h
#define P_VPP_SC_MISC 		CBUS_REG_ADDR(VPP_SC_MISC) 	///../ucode/register.h
#define VPP_PREBLEND_VD1_H_START_END 0x1d1a 	///../ucode/register.h
#define P_VPP_PREBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP_PREBLEND_VD1_H_START_END) 	///../ucode/register.h
#define VPP_PREBLEND_VD1_V_START_END 0x1d1b 	///../ucode/register.h
#define P_VPP_PREBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP_PREBLEND_VD1_V_START_END) 	///../ucode/register.h
#define VPP_POSTBLEND_VD1_H_START_END 0x1d1c 	///../ucode/register.h
#define P_VPP_POSTBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP_POSTBLEND_VD1_H_START_END) 	///../ucode/register.h
#define VPP_POSTBLEND_VD1_V_START_END 0x1d1d 	///../ucode/register.h
#define P_VPP_POSTBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP_POSTBLEND_VD1_V_START_END) 	///../ucode/register.h
#define VPP_BLEND_VD2_H_START_END 0x1d1e 	///../ucode/register.h
#define P_VPP_BLEND_VD2_H_START_END 		CBUS_REG_ADDR(VPP_BLEND_VD2_H_START_END) 	///../ucode/register.h
#define VPP_BLEND_VD2_V_START_END 0x1d1f 	///../ucode/register.h
#define P_VPP_BLEND_VD2_V_START_END 		CBUS_REG_ADDR(VPP_BLEND_VD2_V_START_END) 	///../ucode/register.h
#define VPP_PREBLEND_H_SIZE 0x1d20 	///../ucode/register.h
#define P_VPP_PREBLEND_H_SIZE 		CBUS_REG_ADDR(VPP_PREBLEND_H_SIZE) 	///../ucode/register.h
#define VPP_POSTBLEND_H_SIZE 0x1d21 	///../ucode/register.h
#define P_VPP_POSTBLEND_H_SIZE 		CBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE) 	///../ucode/register.h
#define VPP_HOLD_LINES 0x1d22 	///../ucode/register.h
#define P_VPP_HOLD_LINES 		CBUS_REG_ADDR(VPP_HOLD_LINES) 	///../ucode/register.h
#define VPP_BLEND_ONECOLOR_CTRL 0x1d23 	///../ucode/register.h
#define P_VPP_BLEND_ONECOLOR_CTRL 		CBUS_REG_ADDR(VPP_BLEND_ONECOLOR_CTRL) 	///../ucode/register.h
#define VPP_PREBLEND_CURRENT_XY 0x1d24 	///../ucode/register.h
#define P_VPP_PREBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP_PREBLEND_CURRENT_XY) 	///../ucode/register.h
#define VPP_POSTBLEND_CURRENT_XY 0x1d25 	///../ucode/register.h
#define P_VPP_POSTBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP_POSTBLEND_CURRENT_XY) 	///../ucode/register.h
#define VPP_MISC 0x1d26 	///../ucode/register.h
#define P_VPP_MISC 		CBUS_REG_ADDR(VPP_MISC) 	///../ucode/register.h
#define VPP_OFIFO_SIZE 0x1d27 	///../ucode/register.h
#define P_VPP_OFIFO_SIZE 		CBUS_REG_ADDR(VPP_OFIFO_SIZE) 	///../ucode/register.h
#define VPP_FIFO_STATUS 0x1d28 	///../ucode/register.h
#define P_VPP_FIFO_STATUS 		CBUS_REG_ADDR(VPP_FIFO_STATUS) 	///../ucode/register.h
#define VPP_SMOKE_CTRL 0x1d29 	///../ucode/register.h
#define P_VPP_SMOKE_CTRL 		CBUS_REG_ADDR(VPP_SMOKE_CTRL) 	///../ucode/register.h
#define VPP_SMOKE1_VAL 0x1d2a 	///../ucode/register.h
#define P_VPP_SMOKE1_VAL 		CBUS_REG_ADDR(VPP_SMOKE1_VAL) 	///../ucode/register.h
#define VPP_SMOKE2_VAL 0x1d2b 	///../ucode/register.h
#define P_VPP_SMOKE2_VAL 		CBUS_REG_ADDR(VPP_SMOKE2_VAL) 	///../ucode/register.h
#define VPP_SMOKE3_VAL 0x1d2c 	///../ucode/register.h
#define P_VPP_SMOKE3_VAL 		CBUS_REG_ADDR(VPP_SMOKE3_VAL) 	///../ucode/register.h
#define VPP_SMOKE1_H_START_END 0x1d2d 	///../ucode/register.h
#define P_VPP_SMOKE1_H_START_END 		CBUS_REG_ADDR(VPP_SMOKE1_H_START_END) 	///../ucode/register.h
#define VPP_SMOKE1_V_START_END 0x1d2e 	///../ucode/register.h
#define P_VPP_SMOKE1_V_START_END 		CBUS_REG_ADDR(VPP_SMOKE1_V_START_END) 	///../ucode/register.h
#define VPP_SMOKE2_H_START_END 0x1d2f 	///../ucode/register.h
#define P_VPP_SMOKE2_H_START_END 		CBUS_REG_ADDR(VPP_SMOKE2_H_START_END) 	///../ucode/register.h
#define VPP_SMOKE2_V_START_END 0x1d30 	///../ucode/register.h
#define P_VPP_SMOKE2_V_START_END 		CBUS_REG_ADDR(VPP_SMOKE2_V_START_END) 	///../ucode/register.h
#define VPP_SMOKE3_H_START_END 0x1d31 	///../ucode/register.h
#define P_VPP_SMOKE3_H_START_END 		CBUS_REG_ADDR(VPP_SMOKE3_H_START_END) 	///../ucode/register.h
#define VPP_SMOKE3_V_START_END 0x1d32 	///../ucode/register.h
#define P_VPP_SMOKE3_V_START_END 		CBUS_REG_ADDR(VPP_SMOKE3_V_START_END) 	///../ucode/register.h
#define VPP_SCO_FIFO_CTRL 0x1d33 	///../ucode/register.h
#define P_VPP_SCO_FIFO_CTRL 		CBUS_REG_ADDR(VPP_SCO_FIFO_CTRL) 	///../ucode/register.h
#define VPP_VADJ_CTRL 0x1d40 	///../ucode/register.h
#define P_VPP_VADJ_CTRL 		CBUS_REG_ADDR(VPP_VADJ_CTRL) 	///../ucode/register.h
#define VPP_VADJ1_Y 0x1d41 	///../ucode/register.h
#define P_VPP_VADJ1_Y 		CBUS_REG_ADDR(VPP_VADJ1_Y) 	///../ucode/register.h
#define VPP_VADJ1_MA_MB 0x1d42 	///../ucode/register.h
#define P_VPP_VADJ1_MA_MB 		CBUS_REG_ADDR(VPP_VADJ1_MA_MB) 	///../ucode/register.h
#define VPP_VADJ1_MC_MD 0x1d43 	///../ucode/register.h
#define P_VPP_VADJ1_MC_MD 		CBUS_REG_ADDR(VPP_VADJ1_MC_MD) 	///../ucode/register.h
#define VPP_VADJ2_Y 0x1d44 	///../ucode/register.h
#define P_VPP_VADJ2_Y 		CBUS_REG_ADDR(VPP_VADJ2_Y) 	///../ucode/register.h
#define VPP_VADJ2_MA_MB 0x1d45 	///../ucode/register.h
#define P_VPP_VADJ2_MA_MB 		CBUS_REG_ADDR(VPP_VADJ2_MA_MB) 	///../ucode/register.h
#define VPP_VADJ2_MC_MD 0x1d46 	///../ucode/register.h
#define P_VPP_VADJ2_MC_MD 		CBUS_REG_ADDR(VPP_VADJ2_MC_MD) 	///../ucode/register.h
#define VPP_HSHARP_CTRL 0x1d50 	///../ucode/register.h
#define P_VPP_HSHARP_CTRL 		CBUS_REG_ADDR(VPP_HSHARP_CTRL) 	///../ucode/register.h
#define VPP_HSHARP_LUMA_THRESH01 0x1d51 	///../ucode/register.h
#define P_VPP_HSHARP_LUMA_THRESH01 		CBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH01) 	///../ucode/register.h
#define VPP_HSHARP_LUMA_THRESH23 0x1d52 	///../ucode/register.h
#define P_VPP_HSHARP_LUMA_THRESH23 		CBUS_REG_ADDR(VPP_HSHARP_LUMA_THRESH23) 	///../ucode/register.h
#define VPP_HSHARP_CHROMA_THRESH01 0x1d53 	///../ucode/register.h
#define P_VPP_HSHARP_CHROMA_THRESH01 		CBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH01) 	///../ucode/register.h
#define VPP_HSHARP_CHROMA_THRESH23 0x1d54 	///../ucode/register.h
#define P_VPP_HSHARP_CHROMA_THRESH23 		CBUS_REG_ADDR(VPP_HSHARP_CHROMA_THRESH23) 	///../ucode/register.h
#define VPP_HSHARP_LUMA_GAIN 0x1d55 	///../ucode/register.h
#define P_VPP_HSHARP_LUMA_GAIN 		CBUS_REG_ADDR(VPP_HSHARP_LUMA_GAIN) 	///../ucode/register.h
#define VPP_HSHARP_CHROMA_GAIN 0x1d56 	///../ucode/register.h
#define P_VPP_HSHARP_CHROMA_GAIN 		CBUS_REG_ADDR(VPP_HSHARP_CHROMA_GAIN) 	///../ucode/register.h
#define VPP_MATRIX_CTRL 0x1d5f 	///../ucode/register.h
#define P_VPP_MATRIX_CTRL 		CBUS_REG_ADDR(VPP_MATRIX_CTRL) 	///../ucode/register.h
#define VPP_MATRIX_COEF00_01 0x1d60 	///../ucode/register.h
#define P_VPP_MATRIX_COEF00_01 		CBUS_REG_ADDR(VPP_MATRIX_COEF00_01) 	///../ucode/register.h
#define VPP_MATRIX_COEF02_10 0x1d61 	///../ucode/register.h
#define P_VPP_MATRIX_COEF02_10 		CBUS_REG_ADDR(VPP_MATRIX_COEF02_10) 	///../ucode/register.h
#define VPP_MATRIX_COEF11_12 0x1d62 	///../ucode/register.h
#define P_VPP_MATRIX_COEF11_12 		CBUS_REG_ADDR(VPP_MATRIX_COEF11_12) 	///../ucode/register.h
#define VPP_MATRIX_COEF20_21 0x1d63 	///../ucode/register.h
#define P_VPP_MATRIX_COEF20_21 		CBUS_REG_ADDR(VPP_MATRIX_COEF20_21) 	///../ucode/register.h
#define VPP_MATRIX_COEF22 0x1d64 	///../ucode/register.h
#define P_VPP_MATRIX_COEF22 		CBUS_REG_ADDR(VPP_MATRIX_COEF22) 	///../ucode/register.h
#define VPP_MATRIX_OFFSET0_1 0x1d65 	///../ucode/register.h
#define P_VPP_MATRIX_OFFSET0_1 		CBUS_REG_ADDR(VPP_MATRIX_OFFSET0_1) 	///../ucode/register.h
#define VPP_MATRIX_OFFSET2 0x1d66 	///../ucode/register.h
#define P_VPP_MATRIX_OFFSET2 		CBUS_REG_ADDR(VPP_MATRIX_OFFSET2) 	///../ucode/register.h
#define VPP_MATRIX_PRE_OFFSET0_1 0x1d67 	///../ucode/register.h
#define P_VPP_MATRIX_PRE_OFFSET0_1 		CBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET0_1) 	///../ucode/register.h
#define VPP_MATRIX_PRE_OFFSET2 0x1d68 	///../ucode/register.h
#define P_VPP_MATRIX_PRE_OFFSET2 		CBUS_REG_ADDR(VPP_MATRIX_PRE_OFFSET2) 	///../ucode/register.h
#define VPP_DUMMY_DATA1 0x1d69 	///../ucode/register.h
#define P_VPP_DUMMY_DATA1 		CBUS_REG_ADDR(VPP_DUMMY_DATA1) 	///../ucode/register.h
#define VPP_GAINOFF_CTRL0 0x1d6a 	///../ucode/register.h
#define P_VPP_GAINOFF_CTRL0 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL0) 	///../ucode/register.h
#define VPP_GAINOFF_CTRL1 0x1d6b 	///../ucode/register.h
#define P_VPP_GAINOFF_CTRL1 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL1) 	///../ucode/register.h
#define VPP_GAINOFF_CTRL2 0x1d6c 	///../ucode/register.h
#define P_VPP_GAINOFF_CTRL2 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL2) 	///../ucode/register.h
#define VPP_GAINOFF_CTRL3 0x1d6d 	///../ucode/register.h
#define P_VPP_GAINOFF_CTRL3 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL3) 	///../ucode/register.h
#define VPP_GAINOFF_CTRL4 0x1d6e 	///../ucode/register.h
#define P_VPP_GAINOFF_CTRL4 		CBUS_REG_ADDR(VPP_GAINOFF_CTRL4) 	///../ucode/register.h
#define VPP_CHROMA_ADDR_PORT 0x1d70 	///../ucode/register.h
#define P_VPP_CHROMA_ADDR_PORT 		CBUS_REG_ADDR(VPP_CHROMA_ADDR_PORT) 	///../ucode/register.h
#define VPP_CHROMA_DATA_PORT 0x1d71 	///../ucode/register.h
#define P_VPP_CHROMA_DATA_PORT 		CBUS_REG_ADDR(VPP_CHROMA_DATA_PORT) 	///../ucode/register.h
#define VPP_GCLK_CTRL0 0x1d72 	///../ucode/register.h
#define P_VPP_GCLK_CTRL0 		CBUS_REG_ADDR(VPP_GCLK_CTRL0) 	///../ucode/register.h
#define VPP_GCLK_CTRL1 0x1d73 	///../ucode/register.h
#define P_VPP_GCLK_CTRL1 		CBUS_REG_ADDR(VPP_GCLK_CTRL1) 	///../ucode/register.h
#define VPP_SC_GCLK_CTRL 0x1d74 	///../ucode/register.h
#define P_VPP_SC_GCLK_CTRL 		CBUS_REG_ADDR(VPP_SC_GCLK_CTRL) 	///../ucode/register.h
#define VPP_BLACKEXT_CTRL 0x1d80 	///../ucode/register.h
#define P_VPP_BLACKEXT_CTRL 		CBUS_REG_ADDR(VPP_BLACKEXT_CTRL) 	///../ucode/register.h
#define VPP_DNLP_CTRL_00 0x1d81 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_00 		CBUS_REG_ADDR(VPP_DNLP_CTRL_00) 	///../ucode/register.h
#define VPP_DNLP_CTRL_01 0x1d82 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_01 		CBUS_REG_ADDR(VPP_DNLP_CTRL_01) 	///../ucode/register.h
#define VPP_DNLP_CTRL_02 0x1d83 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_02 		CBUS_REG_ADDR(VPP_DNLP_CTRL_02) 	///../ucode/register.h
#define VPP_DNLP_CTRL_03 0x1d84 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_03 		CBUS_REG_ADDR(VPP_DNLP_CTRL_03) 	///../ucode/register.h
#define VPP_DNLP_CTRL_04 0x1d85 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_04 		CBUS_REG_ADDR(VPP_DNLP_CTRL_04) 	///../ucode/register.h
#define VPP_DNLP_CTRL_05 0x1d86 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_05 		CBUS_REG_ADDR(VPP_DNLP_CTRL_05) 	///../ucode/register.h
#define VPP_DNLP_CTRL_06 0x1d87 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_06 		CBUS_REG_ADDR(VPP_DNLP_CTRL_06) 	///../ucode/register.h
#define VPP_DNLP_CTRL_07 0x1d88 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_07 		CBUS_REG_ADDR(VPP_DNLP_CTRL_07) 	///../ucode/register.h
#define VPP_DNLP_CTRL_08 0x1d89 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_08 		CBUS_REG_ADDR(VPP_DNLP_CTRL_08) 	///../ucode/register.h
#define VPP_DNLP_CTRL_09 0x1d8a 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_09 		CBUS_REG_ADDR(VPP_DNLP_CTRL_09) 	///../ucode/register.h
#define VPP_DNLP_CTRL_10 0x1d8b 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_10 		CBUS_REG_ADDR(VPP_DNLP_CTRL_10) 	///../ucode/register.h
#define VPP_DNLP_CTRL_11 0x1d8c 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_11 		CBUS_REG_ADDR(VPP_DNLP_CTRL_11) 	///../ucode/register.h
#define VPP_DNLP_CTRL_12 0x1d8d 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_12 		CBUS_REG_ADDR(VPP_DNLP_CTRL_12) 	///../ucode/register.h
#define VPP_DNLP_CTRL_13 0x1d8e 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_13 		CBUS_REG_ADDR(VPP_DNLP_CTRL_13) 	///../ucode/register.h
#define VPP_DNLP_CTRL_14 0x1d8f 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_14 		CBUS_REG_ADDR(VPP_DNLP_CTRL_14) 	///../ucode/register.h
#define VPP_DNLP_CTRL_15 0x1d90 	///../ucode/register.h
#define P_VPP_DNLP_CTRL_15 		CBUS_REG_ADDR(VPP_DNLP_CTRL_15) 	///../ucode/register.h
#define VPP_PEAKING_HGAIN 0x1d91 	///../ucode/register.h
#define P_VPP_PEAKING_HGAIN 		CBUS_REG_ADDR(VPP_PEAKING_HGAIN) 	///../ucode/register.h
#define VPP_PEAKING_VGAIN 0x1d92 	///../ucode/register.h
#define P_VPP_PEAKING_VGAIN 		CBUS_REG_ADDR(VPP_PEAKING_VGAIN) 	///../ucode/register.h
#define VPP_PEAKING_NLP_1 0x1d93 	///../ucode/register.h
#define P_VPP_PEAKING_NLP_1 		CBUS_REG_ADDR(VPP_PEAKING_NLP_1) 	///../ucode/register.h
#define VPP_PEAKING_NLP_2 0x1d94 	///../ucode/register.h
#define P_VPP_PEAKING_NLP_2 		CBUS_REG_ADDR(VPP_PEAKING_NLP_2) 	///../ucode/register.h
#define VPP_PEAKING_NLP_3 0x1d95 	///../ucode/register.h
#define P_VPP_PEAKING_NLP_3 		CBUS_REG_ADDR(VPP_PEAKING_NLP_3) 	///../ucode/register.h
#define VPP_PEAKING_NLP_4 0x1d96 	///../ucode/register.h
#define P_VPP_PEAKING_NLP_4 		CBUS_REG_ADDR(VPP_PEAKING_NLP_4) 	///../ucode/register.h
#define VPP_PEAKING_NLP_5 0x1d97 	///../ucode/register.h
#define P_VPP_PEAKING_NLP_5 		CBUS_REG_ADDR(VPP_PEAKING_NLP_5) 	///../ucode/register.h
#define VPP_SHARP_LIMIT 0x1d98 	///../ucode/register.h
#define P_VPP_SHARP_LIMIT 		CBUS_REG_ADDR(VPP_SHARP_LIMIT) 	///../ucode/register.h
#define VPP_VLTI_CTRL 0x1d99 	///../ucode/register.h
#define P_VPP_VLTI_CTRL 		CBUS_REG_ADDR(VPP_VLTI_CTRL) 	///../ucode/register.h
#define VPP_HLTI_CTRL 0x1d9a 	///../ucode/register.h
#define P_VPP_HLTI_CTRL 		CBUS_REG_ADDR(VPP_HLTI_CTRL) 	///../ucode/register.h
#define VPP_CTI_CTRL 0x1d9b 	///../ucode/register.h
#define P_VPP_CTI_CTRL 		CBUS_REG_ADDR(VPP_CTI_CTRL) 	///../ucode/register.h
#define VPP_BLUE_STRETCH_1 0x1d9c 	///../ucode/register.h
#define P_VPP_BLUE_STRETCH_1 		CBUS_REG_ADDR(VPP_BLUE_STRETCH_1) 	///../ucode/register.h
#define VPP_BLUE_STRETCH_2 0x1d9d 	///../ucode/register.h
#define P_VPP_BLUE_STRETCH_2 		CBUS_REG_ADDR(VPP_BLUE_STRETCH_2) 	///../ucode/register.h
#define VPP_BLUE_STRETCH_3 0x1d9e 	///../ucode/register.h
#define P_VPP_BLUE_STRETCH_3 		CBUS_REG_ADDR(VPP_BLUE_STRETCH_3) 	///../ucode/register.h
#define VPP_CCORING_CTRL 0x1da0 	///../ucode/register.h
#define P_VPP_CCORING_CTRL 		CBUS_REG_ADDR(VPP_CCORING_CTRL) 	///../ucode/register.h
#define VPP_VE_ENABLE_CTRL 0x1da1 	///../ucode/register.h
#define P_VPP_VE_ENABLE_CTRL 		CBUS_REG_ADDR(VPP_VE_ENABLE_CTRL) 	///../ucode/register.h
#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x1da2 	///../ucode/register.h
#define P_VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 		CBUS_REG_ADDR(VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH) 	///../ucode/register.h
#define VPP_VE_DEMO_CENTER_BAR 0x1da3 	///../ucode/register.h
#define P_VPP_VE_DEMO_CENTER_BAR 		CBUS_REG_ADDR(VPP_VE_DEMO_CENTER_BAR) 	///../ucode/register.h
#define VPP_VDO_MEAS_CTRL 0x1da8 	///../ucode/register.h
#define P_VPP_VDO_MEAS_CTRL 		CBUS_REG_ADDR(VPP_VDO_MEAS_CTRL) 	///../ucode/register.h
#define VPP_VDO_MEAS_VS_COUNT_HI 0x1da9 	///../ucode/register.h
#define P_VPP_VDO_MEAS_VS_COUNT_HI 		CBUS_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_HI) 	///../ucode/register.h
#define VPP_VDO_MEAS_VS_COUNT_LO 0x1daa 	///../ucode/register.h
#define P_VPP_VDO_MEAS_VS_COUNT_LO 		CBUS_REG_ADDR(VPP_VDO_MEAS_VS_COUNT_LO) 	///../ucode/register.h
#define VPP2_DUMMY_DATA 0x1900 	///../ucode/register.h
#define P_VPP2_DUMMY_DATA 		CBUS_REG_ADDR(VPP2_DUMMY_DATA) 	///../ucode/register.h
#define VPP2_LINE_IN_LENGTH 0x1901 	///../ucode/register.h
#define P_VPP2_LINE_IN_LENGTH 		CBUS_REG_ADDR(VPP2_LINE_IN_LENGTH) 	///../ucode/register.h
#define VPP2_PIC_IN_HEIGHT 0x1902 	///../ucode/register.h
#define P_VPP2_PIC_IN_HEIGHT 		CBUS_REG_ADDR(VPP2_PIC_IN_HEIGHT) 	///../ucode/register.h
#define VPP2_SCALE_COEF_IDX 0x1903 	///../ucode/register.h
#define P_VPP2_SCALE_COEF_IDX 		CBUS_REG_ADDR(VPP2_SCALE_COEF_IDX) 	///../ucode/register.h
#define VPP2_SCALE_COEF 0x1904 	///../ucode/register.h
#define P_VPP2_SCALE_COEF 		CBUS_REG_ADDR(VPP2_SCALE_COEF) 	///../ucode/register.h
#define VPP2_VSC_REGION12_STARTP 0x1905 	///../ucode/register.h
#define P_VPP2_VSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP2_VSC_REGION12_STARTP) 	///../ucode/register.h
#define VPP2_VSC_REGION34_STARTP 0x1906 	///../ucode/register.h
#define P_VPP2_VSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP2_VSC_REGION34_STARTP) 	///../ucode/register.h
#define VPP2_VSC_REGION4_ENDP 0x1907 	///../ucode/register.h
#define P_VPP2_VSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP2_VSC_REGION4_ENDP) 	///../ucode/register.h
#define VPP2_VSC_START_PHASE_STEP 0x1908 	///../ucode/register.h
#define P_VPP2_VSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP2_VSC_START_PHASE_STEP) 	///../ucode/register.h
#define VPP2_VSC_REGION0_PHASE_SLOPE 0x1909 	///../ucode/register.h
#define P_VPP2_VSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION0_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_VSC_REGION1_PHASE_SLOPE 0x190a 	///../ucode/register.h
#define P_VPP2_VSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION1_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_VSC_REGION3_PHASE_SLOPE 0x190b 	///../ucode/register.h
#define P_VPP2_VSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION3_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_VSC_REGION4_PHASE_SLOPE 0x190c 	///../ucode/register.h
#define P_VPP2_VSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_VSC_REGION4_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_VSC_PHASE_CTRL 0x190d 	///../ucode/register.h
#define P_VPP2_VSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP2_VSC_PHASE_CTRL) 	///../ucode/register.h
#define VPP2_VSC_INI_PHASE 0x190e 	///../ucode/register.h
#define P_VPP2_VSC_INI_PHASE 		CBUS_REG_ADDR(VPP2_VSC_INI_PHASE) 	///../ucode/register.h
#define VPP2_HSC_REGION12_STARTP 0x1910 	///../ucode/register.h
#define P_VPP2_HSC_REGION12_STARTP 		CBUS_REG_ADDR(VPP2_HSC_REGION12_STARTP) 	///../ucode/register.h
#define VPP2_HSC_REGION34_STARTP 0x1911 	///../ucode/register.h
#define P_VPP2_HSC_REGION34_STARTP 		CBUS_REG_ADDR(VPP2_HSC_REGION34_STARTP) 	///../ucode/register.h
#define VPP2_HSC_REGION4_ENDP 0x1912 	///../ucode/register.h
#define P_VPP2_HSC_REGION4_ENDP 		CBUS_REG_ADDR(VPP2_HSC_REGION4_ENDP) 	///../ucode/register.h
#define VPP2_HSC_START_PHASE_STEP 0x1913 	///../ucode/register.h
#define P_VPP2_HSC_START_PHASE_STEP 		CBUS_REG_ADDR(VPP2_HSC_START_PHASE_STEP) 	///../ucode/register.h
#define VPP2_HSC_REGION0_PHASE_SLOPE 0x1914 	///../ucode/register.h
#define P_VPP2_HSC_REGION0_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION0_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_HSC_REGION1_PHASE_SLOPE 0x1915 	///../ucode/register.h
#define P_VPP2_HSC_REGION1_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION1_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_HSC_REGION3_PHASE_SLOPE 0x1916 	///../ucode/register.h
#define P_VPP2_HSC_REGION3_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION3_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_HSC_REGION4_PHASE_SLOPE 0x1917 	///../ucode/register.h
#define P_VPP2_HSC_REGION4_PHASE_SLOPE 		CBUS_REG_ADDR(VPP2_HSC_REGION4_PHASE_SLOPE) 	///../ucode/register.h
#define VPP2_HSC_PHASE_CTRL 0x1918 	///../ucode/register.h
#define P_VPP2_HSC_PHASE_CTRL 		CBUS_REG_ADDR(VPP2_HSC_PHASE_CTRL) 	///../ucode/register.h
#define VPP2_SC_MISC 0x1919 	///../ucode/register.h
#define P_VPP2_SC_MISC 		CBUS_REG_ADDR(VPP2_SC_MISC) 	///../ucode/register.h
#define VPP2_PREBLEND_VD1_H_START_END 0x191a 	///../ucode/register.h
#define P_VPP2_PREBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP2_PREBLEND_VD1_H_START_END) 	///../ucode/register.h
#define VPP2_PREBLEND_VD1_V_START_END 0x191b 	///../ucode/register.h
#define P_VPP2_PREBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP2_PREBLEND_VD1_V_START_END) 	///../ucode/register.h
#define VPP2_POSTBLEND_VD1_H_START_END 0x191c 	///../ucode/register.h
#define P_VPP2_POSTBLEND_VD1_H_START_END 		CBUS_REG_ADDR(VPP2_POSTBLEND_VD1_H_START_END) 	///../ucode/register.h
#define VPP2_POSTBLEND_VD1_V_START_END 0x191d 	///../ucode/register.h
#define P_VPP2_POSTBLEND_VD1_V_START_END 		CBUS_REG_ADDR(VPP2_POSTBLEND_VD1_V_START_END) 	///../ucode/register.h
#define VPP2_PREBLEND_H_SIZE 0x1920 	///../ucode/register.h
#define P_VPP2_PREBLEND_H_SIZE 		CBUS_REG_ADDR(VPP2_PREBLEND_H_SIZE) 	///../ucode/register.h
#define VPP2_POSTBLEND_H_SIZE 0x1921 	///../ucode/register.h
#define P_VPP2_POSTBLEND_H_SIZE 		CBUS_REG_ADDR(VPP2_POSTBLEND_H_SIZE) 	///../ucode/register.h
#define VPP2_HOLD_LINES 0x1922 	///../ucode/register.h
#define P_VPP2_HOLD_LINES 		CBUS_REG_ADDR(VPP2_HOLD_LINES) 	///../ucode/register.h
#define VPP2_BLEND_ONECOLOR_CTRL 0x1923 	///../ucode/register.h
#define P_VPP2_BLEND_ONECOLOR_CTRL 		CBUS_REG_ADDR(VPP2_BLEND_ONECOLOR_CTRL) 	///../ucode/register.h
#define VPP2_PREBLEND_CURRENT_XY 0x1924 	///../ucode/register.h
#define P_VPP2_PREBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP2_PREBLEND_CURRENT_XY) 	///../ucode/register.h
#define VPP2_POSTBLEND_CURRENT_XY 0x1925 	///../ucode/register.h
#define P_VPP2_POSTBLEND_CURRENT_XY 		CBUS_REG_ADDR(VPP2_POSTBLEND_CURRENT_XY) 	///../ucode/register.h
#define VPP2_MISC 0x1926 	///../ucode/register.h
#define P_VPP2_MISC 		CBUS_REG_ADDR(VPP2_MISC) 	///../ucode/register.h
#define VPP2_OFIFO_SIZE 0x1927 	///../ucode/register.h
#define P_VPP2_OFIFO_SIZE 		CBUS_REG_ADDR(VPP2_OFIFO_SIZE) 	///../ucode/register.h
#define VPP2_FIFO_STATUS 0x1928 	///../ucode/register.h
#define P_VPP2_FIFO_STATUS 		CBUS_REG_ADDR(VPP2_FIFO_STATUS) 	///../ucode/register.h
#define VPP2_SMOKE_CTRL 0x1929 	///../ucode/register.h
#define P_VPP2_SMOKE_CTRL 		CBUS_REG_ADDR(VPP2_SMOKE_CTRL) 	///../ucode/register.h
#define VPP2_SMOKE1_VAL 0x192a 	///../ucode/register.h
#define P_VPP2_SMOKE1_VAL 		CBUS_REG_ADDR(VPP2_SMOKE1_VAL) 	///../ucode/register.h
#define VPP2_SMOKE2_VAL 0x192b 	///../ucode/register.h
#define P_VPP2_SMOKE2_VAL 		CBUS_REG_ADDR(VPP2_SMOKE2_VAL) 	///../ucode/register.h
#define VPP2_SMOKE1_H_START_END 0x192d 	///../ucode/register.h
#define P_VPP2_SMOKE1_H_START_END 		CBUS_REG_ADDR(VPP2_SMOKE1_H_START_END) 	///../ucode/register.h
#define VPP2_SMOKE1_V_START_END 0x192e 	///../ucode/register.h
#define P_VPP2_SMOKE1_V_START_END 		CBUS_REG_ADDR(VPP2_SMOKE1_V_START_END) 	///../ucode/register.h
#define VPP2_SMOKE2_H_START_END 0x192f 	///../ucode/register.h
#define P_VPP2_SMOKE2_H_START_END 		CBUS_REG_ADDR(VPP2_SMOKE2_H_START_END) 	///../ucode/register.h
#define VPP2_SMOKE2_V_START_END 0x1930 	///../ucode/register.h
#define P_VPP2_SMOKE2_V_START_END 		CBUS_REG_ADDR(VPP2_SMOKE2_V_START_END) 	///../ucode/register.h
#define VPP2_SCO_FIFO_CTRL 0x1933 	///../ucode/register.h
#define P_VPP2_SCO_FIFO_CTRL 		CBUS_REG_ADDR(VPP2_SCO_FIFO_CTRL) 	///../ucode/register.h
#define VPP2_VADJ_CTRL 0x1940 	///../ucode/register.h
#define P_VPP2_VADJ_CTRL 		CBUS_REG_ADDR(VPP2_VADJ_CTRL) 	///../ucode/register.h
#define VPP2_VADJ1_Y 0x1941 	///../ucode/register.h
#define P_VPP2_VADJ1_Y 		CBUS_REG_ADDR(VPP2_VADJ1_Y) 	///../ucode/register.h
#define VPP2_VADJ1_MA_MB 0x1942 	///../ucode/register.h
#define P_VPP2_VADJ1_MA_MB 		CBUS_REG_ADDR(VPP2_VADJ1_MA_MB) 	///../ucode/register.h
#define VPP2_VADJ1_MC_MD 0x1943 	///../ucode/register.h
#define P_VPP2_VADJ1_MC_MD 		CBUS_REG_ADDR(VPP2_VADJ1_MC_MD) 	///../ucode/register.h
#define VPP2_VADJ2_Y 0x1944 	///../ucode/register.h
#define P_VPP2_VADJ2_Y 		CBUS_REG_ADDR(VPP2_VADJ2_Y) 	///../ucode/register.h
#define VPP2_VADJ2_MA_MB 0x1945 	///../ucode/register.h
#define P_VPP2_VADJ2_MA_MB 		CBUS_REG_ADDR(VPP2_VADJ2_MA_MB) 	///../ucode/register.h
#define VPP2_VADJ2_MC_MD 0x1946 	///../ucode/register.h
#define P_VPP2_VADJ2_MC_MD 		CBUS_REG_ADDR(VPP2_VADJ2_MC_MD) 	///../ucode/register.h
#define VPP2_HSHARP_CTRL 0x1950 	///../ucode/register.h
#define P_VPP2_HSHARP_CTRL 		CBUS_REG_ADDR(VPP2_HSHARP_CTRL) 	///../ucode/register.h
#define VPP2_HSHARP_LUMA_THRESH01 0x1951 	///../ucode/register.h
#define P_VPP2_HSHARP_LUMA_THRESH01 		CBUS_REG_ADDR(VPP2_HSHARP_LUMA_THRESH01) 	///../ucode/register.h
#define VPP2_HSHARP_LUMA_THRESH23 0x1952 	///../ucode/register.h
#define P_VPP2_HSHARP_LUMA_THRESH23 		CBUS_REG_ADDR(VPP2_HSHARP_LUMA_THRESH23) 	///../ucode/register.h
#define VPP2_HSHARP_CHROMA_THRESH01 0x1953 	///../ucode/register.h
#define P_VPP2_HSHARP_CHROMA_THRESH01 		CBUS_REG_ADDR(VPP2_HSHARP_CHROMA_THRESH01) 	///../ucode/register.h
#define VPP2_HSHARP_CHROMA_THRESH23 0x1954 	///../ucode/register.h
#define P_VPP2_HSHARP_CHROMA_THRESH23 		CBUS_REG_ADDR(VPP2_HSHARP_CHROMA_THRESH23) 	///../ucode/register.h
#define VPP2_HSHARP_LUMA_GAIN 0x1955 	///../ucode/register.h
#define P_VPP2_HSHARP_LUMA_GAIN 		CBUS_REG_ADDR(VPP2_HSHARP_LUMA_GAIN) 	///../ucode/register.h
#define VPP2_HSHARP_CHROMA_GAIN 0x1956 	///../ucode/register.h
#define P_VPP2_HSHARP_CHROMA_GAIN 		CBUS_REG_ADDR(VPP2_HSHARP_CHROMA_GAIN) 	///../ucode/register.h
#define VPP2_MATRIX_CTRL 0x195f 	///../ucode/register.h
#define P_VPP2_MATRIX_CTRL 		CBUS_REG_ADDR(VPP2_MATRIX_CTRL) 	///../ucode/register.h
#define VPP2_MATRIX_COEF00_01 0x1960 	///../ucode/register.h
#define P_VPP2_MATRIX_COEF00_01 		CBUS_REG_ADDR(VPP2_MATRIX_COEF00_01) 	///../ucode/register.h
#define VPP2_MATRIX_COEF02_10 0x1961 	///../ucode/register.h
#define P_VPP2_MATRIX_COEF02_10 		CBUS_REG_ADDR(VPP2_MATRIX_COEF02_10) 	///../ucode/register.h
#define VPP2_MATRIX_COEF11_12 0x1962 	///../ucode/register.h
#define P_VPP2_MATRIX_COEF11_12 		CBUS_REG_ADDR(VPP2_MATRIX_COEF11_12) 	///../ucode/register.h
#define VPP2_MATRIX_COEF20_21 0x1963 	///../ucode/register.h
#define P_VPP2_MATRIX_COEF20_21 		CBUS_REG_ADDR(VPP2_MATRIX_COEF20_21) 	///../ucode/register.h
#define VPP2_MATRIX_COEF22 0x1964 	///../ucode/register.h
#define P_VPP2_MATRIX_COEF22 		CBUS_REG_ADDR(VPP2_MATRIX_COEF22) 	///../ucode/register.h
#define VPP2_MATRIX_OFFSET0_1 0x1965 	///../ucode/register.h
#define P_VPP2_MATRIX_OFFSET0_1 		CBUS_REG_ADDR(VPP2_MATRIX_OFFSET0_1) 	///../ucode/register.h
#define VPP2_MATRIX_OFFSET2 0x1966 	///../ucode/register.h
#define P_VPP2_MATRIX_OFFSET2 		CBUS_REG_ADDR(VPP2_MATRIX_OFFSET2) 	///../ucode/register.h
#define VPP2_MATRIX_PRE_OFFSET0_1 0x1967 	///../ucode/register.h
#define P_VPP2_MATRIX_PRE_OFFSET0_1 		CBUS_REG_ADDR(VPP2_MATRIX_PRE_OFFSET0_1) 	///../ucode/register.h
#define VPP2_MATRIX_PRE_OFFSET2 0x1968 	///../ucode/register.h
#define P_VPP2_MATRIX_PRE_OFFSET2 		CBUS_REG_ADDR(VPP2_MATRIX_PRE_OFFSET2) 	///../ucode/register.h
#define VPP2_DUMMY_DATA1 0x1969 	///../ucode/register.h
#define P_VPP2_DUMMY_DATA1 		CBUS_REG_ADDR(VPP2_DUMMY_DATA1) 	///../ucode/register.h
#define VPP2_GAINOFF_CTRL0 0x196a 	///../ucode/register.h
#define P_VPP2_GAINOFF_CTRL0 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL0) 	///../ucode/register.h
#define VPP2_GAINOFF_CTRL1 0x196b 	///../ucode/register.h
#define P_VPP2_GAINOFF_CTRL1 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL1) 	///../ucode/register.h
#define VPP2_GAINOFF_CTRL2 0x196c 	///../ucode/register.h
#define P_VPP2_GAINOFF_CTRL2 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL2) 	///../ucode/register.h
#define VPP2_GAINOFF_CTRL3 0x196d 	///../ucode/register.h
#define P_VPP2_GAINOFF_CTRL3 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL3) 	///../ucode/register.h
#define VPP2_GAINOFF_CTRL4 0x196e 	///../ucode/register.h
#define P_VPP2_GAINOFF_CTRL4 		CBUS_REG_ADDR(VPP2_GAINOFF_CTRL4) 	///../ucode/register.h
#define VPP2_CHROMA_ADDR_PORT 0x1970 	///../ucode/register.h
#define P_VPP2_CHROMA_ADDR_PORT 		CBUS_REG_ADDR(VPP2_CHROMA_ADDR_PORT) 	///../ucode/register.h
#define VPP2_CHROMA_DATA_PORT 0x1971 	///../ucode/register.h
#define P_VPP2_CHROMA_DATA_PORT 		CBUS_REG_ADDR(VPP2_CHROMA_DATA_PORT) 	///../ucode/register.h
#define VPP2_GCLK_CTRL0 0x1972 	///../ucode/register.h
#define P_VPP2_GCLK_CTRL0 		CBUS_REG_ADDR(VPP2_GCLK_CTRL0) 	///../ucode/register.h
#define VPP2_GCLK_CTRL1 0x1973 	///../ucode/register.h
#define P_VPP2_GCLK_CTRL1 		CBUS_REG_ADDR(VPP2_GCLK_CTRL1) 	///../ucode/register.h
#define VPP2_SC_GCLK_CTRL 0x1974 	///../ucode/register.h
#define P_VPP2_SC_GCLK_CTRL 		CBUS_REG_ADDR(VPP2_SC_GCLK_CTRL) 	///../ucode/register.h
#define VPP2_BLACKEXT_CTRL 0x1980 	///../ucode/register.h
#define P_VPP2_BLACKEXT_CTRL 		CBUS_REG_ADDR(VPP2_BLACKEXT_CTRL) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_00 0x1981 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_00 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_00) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_01 0x1982 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_01 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_01) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_02 0x1983 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_02 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_02) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_03 0x1984 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_03 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_03) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_04 0x1985 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_04 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_04) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_05 0x1986 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_05 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_05) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_06 0x1987 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_06 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_06) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_07 0x1988 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_07 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_07) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_08 0x1989 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_08 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_08) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_09 0x198a 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_09 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_09) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_10 0x198b 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_10 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_10) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_11 0x198c 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_11 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_11) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_12 0x198d 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_12 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_12) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_13 0x198e 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_13 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_13) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_14 0x198f 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_14 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_14) 	///../ucode/register.h
#define VPP2_DNLP_CTRL_15 0x1990 	///../ucode/register.h
#define P_VPP2_DNLP_CTRL_15 		CBUS_REG_ADDR(VPP2_DNLP_CTRL_15) 	///../ucode/register.h
#define VPP2_PEAKING_HGAIN 0x1991 	///../ucode/register.h
#define P_VPP2_PEAKING_HGAIN 		CBUS_REG_ADDR(VPP2_PEAKING_HGAIN) 	///../ucode/register.h
#define VPP2_PEAKING_VGAIN 0x1992 	///../ucode/register.h
#define P_VPP2_PEAKING_VGAIN 		CBUS_REG_ADDR(VPP2_PEAKING_VGAIN) 	///../ucode/register.h
#define VPP2_PEAKING_NLP_1 0x1993 	///../ucode/register.h
#define P_VPP2_PEAKING_NLP_1 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_1) 	///../ucode/register.h
#define VPP2_PEAKING_NLP_2 0x1994 	///../ucode/register.h
#define P_VPP2_PEAKING_NLP_2 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_2) 	///../ucode/register.h
#define VPP2_PEAKING_NLP_3 0x1995 	///../ucode/register.h
#define P_VPP2_PEAKING_NLP_3 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_3) 	///../ucode/register.h
#define VPP2_PEAKING_NLP_4 0x1996 	///../ucode/register.h
#define P_VPP2_PEAKING_NLP_4 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_4) 	///../ucode/register.h
#define VPP2_PEAKING_NLP_5 0x1997 	///../ucode/register.h
#define P_VPP2_PEAKING_NLP_5 		CBUS_REG_ADDR(VPP2_PEAKING_NLP_5) 	///../ucode/register.h
#define VPP2_SHARP_LIMIT 0x1998 	///../ucode/register.h
#define P_VPP2_SHARP_LIMIT 		CBUS_REG_ADDR(VPP2_SHARP_LIMIT) 	///../ucode/register.h
#define VPP2_VLTI_CTRL 0x1999 	///../ucode/register.h
#define P_VPP2_VLTI_CTRL 		CBUS_REG_ADDR(VPP2_VLTI_CTRL) 	///../ucode/register.h
#define VPP2_HLTI_CTRL 0x199a 	///../ucode/register.h
#define P_VPP2_HLTI_CTRL 		CBUS_REG_ADDR(VPP2_HLTI_CTRL) 	///../ucode/register.h
#define VPP2_CTI_CTRL 0x199b 	///../ucode/register.h
#define P_VPP2_CTI_CTRL 		CBUS_REG_ADDR(VPP2_CTI_CTRL) 	///../ucode/register.h
#define VPP2_BLUE_STRETCH_1 0x199c 	///../ucode/register.h
#define P_VPP2_BLUE_STRETCH_1 		CBUS_REG_ADDR(VPP2_BLUE_STRETCH_1) 	///../ucode/register.h
#define VPP2_BLUE_STRETCH_2 0x199d 	///../ucode/register.h
#define P_VPP2_BLUE_STRETCH_2 		CBUS_REG_ADDR(VPP2_BLUE_STRETCH_2) 	///../ucode/register.h
#define VPP2_BLUE_STRETCH_3 0x199e 	///../ucode/register.h
#define P_VPP2_BLUE_STRETCH_3 		CBUS_REG_ADDR(VPP2_BLUE_STRETCH_3) 	///../ucode/register.h
#define VPP2_CCORING_CTRL 0x19a0 	///../ucode/register.h
#define P_VPP2_CCORING_CTRL 		CBUS_REG_ADDR(VPP2_CCORING_CTRL) 	///../ucode/register.h
#define VPP2_VE_ENABLE_CTRL 0x19a1 	///../ucode/register.h
#define P_VPP2_VE_ENABLE_CTRL 		CBUS_REG_ADDR(VPP2_VE_ENABLE_CTRL) 	///../ucode/register.h
#define VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 0x19a2 	///../ucode/register.h
#define P_VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH 		CBUS_REG_ADDR(VPP2_VE_DEMO_LEFT_TOP_SCREEN_WIDTH) 	///../ucode/register.h
#define VPP2_VE_DEMO_CENTER_BAR 0x19a3 	///../ucode/register.h
#define P_VPP2_VE_DEMO_CENTER_BAR 		CBUS_REG_ADDR(VPP2_VE_DEMO_CENTER_BAR) 	///../ucode/register.h
#define VPP2_VDO_MEAS_CTRL 0x19a8 	///../ucode/register.h
#define P_VPP2_VDO_MEAS_CTRL 		CBUS_REG_ADDR(VPP2_VDO_MEAS_CTRL) 	///../ucode/register.h
#define VPP2_VDO_MEAS_VS_COUNT_HI 0x19a9 	///../ucode/register.h
#define P_VPP2_VDO_MEAS_VS_COUNT_HI 		CBUS_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_HI) 	///../ucode/register.h
#define VPP2_VDO_MEAS_VS_COUNT_LO 0x19aa 	///../ucode/register.h
#define P_VPP2_VDO_MEAS_VS_COUNT_LO 		CBUS_REG_ADDR(VPP2_VDO_MEAS_VS_COUNT_LO) 	///../ucode/register.h
#define GE2D_GEN_CTRL0 0x18a0 	///../ucode/register.h
#define P_GE2D_GEN_CTRL0 		CBUS_REG_ADDR(GE2D_GEN_CTRL0) 	///../ucode/register.h
#define GE2D_GEN_CTRL1 0x18a1 	///../ucode/register.h
#define P_GE2D_GEN_CTRL1 		CBUS_REG_ADDR(GE2D_GEN_CTRL1) 	///../ucode/register.h
#define GE2D_GEN_CTRL2 0x18a2 	///../ucode/register.h
#define P_GE2D_GEN_CTRL2 		CBUS_REG_ADDR(GE2D_GEN_CTRL2) 	///../ucode/register.h
#define GE2D_CMD_CTRL 0x18a3 	///../ucode/register.h
#define P_GE2D_CMD_CTRL 		CBUS_REG_ADDR(GE2D_CMD_CTRL) 	///../ucode/register.h
#define GE2D_STATUS0 0x18a4 	///../ucode/register.h
#define P_GE2D_STATUS0 		CBUS_REG_ADDR(GE2D_STATUS0) 	///../ucode/register.h
#define GE2D_STATUS1 0x18a5 	///../ucode/register.h
#define P_GE2D_STATUS1 		CBUS_REG_ADDR(GE2D_STATUS1) 	///../ucode/register.h
#define GE2D_SRC1_DEF_COLOR 0x18a6 	///../ucode/register.h
#define P_GE2D_SRC1_DEF_COLOR 		CBUS_REG_ADDR(GE2D_SRC1_DEF_COLOR) 	///../ucode/register.h
#define GE2D_SRC1_CLIPX_START_END 0x18a7 	///../ucode/register.h
#define P_GE2D_SRC1_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_SRC1_CLIPX_START_END) 	///../ucode/register.h
#define GE2D_SRC1_CLIPY_START_END 0x18a8 	///../ucode/register.h
#define P_GE2D_SRC1_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_SRC1_CLIPY_START_END) 	///../ucode/register.h
#define GE2D_SRC1_CANVAS 0x18a9 	///../ucode/register.h
#define P_GE2D_SRC1_CANVAS 		CBUS_REG_ADDR(GE2D_SRC1_CANVAS) 	///../ucode/register.h
#define GE2D_SRC1_X_START_END 0x18aa 	///../ucode/register.h
#define P_GE2D_SRC1_X_START_END 		CBUS_REG_ADDR(GE2D_SRC1_X_START_END) 	///../ucode/register.h
#define GE2D_SRC1_Y_START_END 0x18ab 	///../ucode/register.h
#define P_GE2D_SRC1_Y_START_END 		CBUS_REG_ADDR(GE2D_SRC1_Y_START_END) 	///../ucode/register.h
#define GE2D_SRC1_LUT_ADDR 0x18ac 	///../ucode/register.h
#define P_GE2D_SRC1_LUT_ADDR 		CBUS_REG_ADDR(GE2D_SRC1_LUT_ADDR) 	///../ucode/register.h
#define GE2D_SRC1_LUT_DAT 0x18ad 	///../ucode/register.h
#define P_GE2D_SRC1_LUT_DAT 		CBUS_REG_ADDR(GE2D_SRC1_LUT_DAT) 	///../ucode/register.h
#define GE2D_SRC1_FMT_CTRL 0x18ae 	///../ucode/register.h
#define P_GE2D_SRC1_FMT_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_FMT_CTRL) 	///../ucode/register.h
#define GE2D_SRC2_DEF_COLOR 0x18af 	///../ucode/register.h
#define P_GE2D_SRC2_DEF_COLOR 		CBUS_REG_ADDR(GE2D_SRC2_DEF_COLOR) 	///../ucode/register.h
#define GE2D_SRC2_CLIPX_START_END 0x18b0 	///../ucode/register.h
#define P_GE2D_SRC2_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_SRC2_CLIPX_START_END) 	///../ucode/register.h
#define GE2D_SRC2_CLIPY_START_END 0x18b1 	///../ucode/register.h
#define P_GE2D_SRC2_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_SRC2_CLIPY_START_END) 	///../ucode/register.h
#define GE2D_SRC2_X_START_END 0x18b2 	///../ucode/register.h
#define P_GE2D_SRC2_X_START_END 		CBUS_REG_ADDR(GE2D_SRC2_X_START_END) 	///../ucode/register.h
#define GE2D_SRC2_Y_START_END 0x18b3 	///../ucode/register.h
#define P_GE2D_SRC2_Y_START_END 		CBUS_REG_ADDR(GE2D_SRC2_Y_START_END) 	///../ucode/register.h
#define GE2D_DST_CLIPX_START_END 0x18b4 	///../ucode/register.h
#define P_GE2D_DST_CLIPX_START_END 		CBUS_REG_ADDR(GE2D_DST_CLIPX_START_END) 	///../ucode/register.h
#define GE2D_DST_CLIPY_START_END 0x18b5 	///../ucode/register.h
#define P_GE2D_DST_CLIPY_START_END 		CBUS_REG_ADDR(GE2D_DST_CLIPY_START_END) 	///../ucode/register.h
#define GE2D_DST_X_START_END 0x18b6 	///../ucode/register.h
#define P_GE2D_DST_X_START_END 		CBUS_REG_ADDR(GE2D_DST_X_START_END) 	///../ucode/register.h
#define GE2D_DST_Y_START_END 0x18b7 	///../ucode/register.h
#define P_GE2D_DST_Y_START_END 		CBUS_REG_ADDR(GE2D_DST_Y_START_END) 	///../ucode/register.h
#define GE2D_SRC2_DST_CANVAS 0x18b8 	///../ucode/register.h
#define P_GE2D_SRC2_DST_CANVAS 		CBUS_REG_ADDR(GE2D_SRC2_DST_CANVAS) 	///../ucode/register.h
#define GE2D_VSC_START_PHASE_STEP 0x18b9 	///../ucode/register.h
#define P_GE2D_VSC_START_PHASE_STEP 		CBUS_REG_ADDR(GE2D_VSC_START_PHASE_STEP) 	///../ucode/register.h
#define GE2D_VSC_PHASE_SLOPE 0x18ba 	///../ucode/register.h
#define P_GE2D_VSC_PHASE_SLOPE 		CBUS_REG_ADDR(GE2D_VSC_PHASE_SLOPE) 	///../ucode/register.h
#define GE2D_VSC_INI_CTRL 0x18bb 	///../ucode/register.h
#define P_GE2D_VSC_INI_CTRL 		CBUS_REG_ADDR(GE2D_VSC_INI_CTRL) 	///../ucode/register.h
#define GE2D_HSC_START_PHASE_STEP 0x18bc 	///../ucode/register.h
#define P_GE2D_HSC_START_PHASE_STEP 		CBUS_REG_ADDR(GE2D_HSC_START_PHASE_STEP) 	///../ucode/register.h
#define GE2D_HSC_PHASE_SLOPE 0x18bd 	///../ucode/register.h
#define P_GE2D_HSC_PHASE_SLOPE 		CBUS_REG_ADDR(GE2D_HSC_PHASE_SLOPE) 	///../ucode/register.h
#define GE2D_HSC_INI_CTRL 0x18be 	///../ucode/register.h
#define P_GE2D_HSC_INI_CTRL 		CBUS_REG_ADDR(GE2D_HSC_INI_CTRL) 	///../ucode/register.h
#define GE2D_HSC_ADV_CTRL 0x18bf 	///../ucode/register.h
#define P_GE2D_HSC_ADV_CTRL 		CBUS_REG_ADDR(GE2D_HSC_ADV_CTRL) 	///../ucode/register.h
#define GE2D_SC_MISC_CTRL 0x18c0 	///../ucode/register.h
#define P_GE2D_SC_MISC_CTRL 		CBUS_REG_ADDR(GE2D_SC_MISC_CTRL) 	///../ucode/register.h
#define GE2D_VSC_NRND_POINT 0x18c1 	///../ucode/register.h
#define P_GE2D_VSC_NRND_POINT 		CBUS_REG_ADDR(GE2D_VSC_NRND_POINT) 	///../ucode/register.h
#define GE2D_VSC_NRND_PHASE 0x18c2 	///../ucode/register.h
#define P_GE2D_VSC_NRND_PHASE 		CBUS_REG_ADDR(GE2D_VSC_NRND_PHASE) 	///../ucode/register.h
#define GE2D_HSC_NRND_POINT 0x18c3 	///../ucode/register.h
#define P_GE2D_HSC_NRND_POINT 		CBUS_REG_ADDR(GE2D_HSC_NRND_POINT) 	///../ucode/register.h
#define GE2D_HSC_NRND_PHASE 0x18c4 	///../ucode/register.h
#define P_GE2D_HSC_NRND_PHASE 		CBUS_REG_ADDR(GE2D_HSC_NRND_PHASE) 	///../ucode/register.h
#define GE2D_MATRIX_PRE_OFFSET 0x18c5 	///../ucode/register.h
#define P_GE2D_MATRIX_PRE_OFFSET 		CBUS_REG_ADDR(GE2D_MATRIX_PRE_OFFSET) 	///../ucode/register.h
#define GE2D_MATRIX_COEF00_01 0x18c6 	///../ucode/register.h
#define P_GE2D_MATRIX_COEF00_01 		CBUS_REG_ADDR(GE2D_MATRIX_COEF00_01) 	///../ucode/register.h
#define GE2D_MATRIX_COEF02_10 0x18c7 	///../ucode/register.h
#define P_GE2D_MATRIX_COEF02_10 		CBUS_REG_ADDR(GE2D_MATRIX_COEF02_10) 	///../ucode/register.h
#define GE2D_MATRIX_COEF11_12 0x18c8 	///../ucode/register.h
#define P_GE2D_MATRIX_COEF11_12 		CBUS_REG_ADDR(GE2D_MATRIX_COEF11_12) 	///../ucode/register.h
#define GE2D_MATRIX_COEF20_21 0x18c9 	///../ucode/register.h
#define P_GE2D_MATRIX_COEF20_21 		CBUS_REG_ADDR(GE2D_MATRIX_COEF20_21) 	///../ucode/register.h
#define GE2D_MATRIX_COEF22_CTRL 0x18ca 	///../ucode/register.h
#define P_GE2D_MATRIX_COEF22_CTRL 		CBUS_REG_ADDR(GE2D_MATRIX_COEF22_CTRL) 	///../ucode/register.h
#define GE2D_MATRIX_OFFSET 0x18cb 	///../ucode/register.h
#define P_GE2D_MATRIX_OFFSET 		CBUS_REG_ADDR(GE2D_MATRIX_OFFSET) 	///../ucode/register.h
#define GE2D_ALU_OP_CTRL 0x18cc 	///../ucode/register.h
#define P_GE2D_ALU_OP_CTRL 		CBUS_REG_ADDR(GE2D_ALU_OP_CTRL) 	///../ucode/register.h
#define GE2D_ALU_CONST_COLOR 0x18cd 	///../ucode/register.h
#define P_GE2D_ALU_CONST_COLOR 		CBUS_REG_ADDR(GE2D_ALU_CONST_COLOR) 	///../ucode/register.h
#define GE2D_SRC1_KEY 0x18ce 	///../ucode/register.h
#define P_GE2D_SRC1_KEY 		CBUS_REG_ADDR(GE2D_SRC1_KEY) 	///../ucode/register.h
#define GE2D_SRC1_KEY_MASK 0x18cf 	///../ucode/register.h
#define P_GE2D_SRC1_KEY_MASK 		CBUS_REG_ADDR(GE2D_SRC1_KEY_MASK) 	///../ucode/register.h
#define GE2D_SRC2_KEY 0x18d0 	///../ucode/register.h
#define P_GE2D_SRC2_KEY 		CBUS_REG_ADDR(GE2D_SRC2_KEY) 	///../ucode/register.h
#define GE2D_SRC2_KEY_MASK 0x18d1 	///../ucode/register.h
#define P_GE2D_SRC2_KEY_MASK 		CBUS_REG_ADDR(GE2D_SRC2_KEY_MASK) 	///../ucode/register.h
#define GE2D_DST_BITMASK 0x18d2 	///../ucode/register.h
#define P_GE2D_DST_BITMASK 		CBUS_REG_ADDR(GE2D_DST_BITMASK) 	///../ucode/register.h
#define GE2D_DP_ONOFF_CTRL 0x18d3 	///../ucode/register.h
#define P_GE2D_DP_ONOFF_CTRL 		CBUS_REG_ADDR(GE2D_DP_ONOFF_CTRL) 	///../ucode/register.h
#define GE2D_SCALE_COEF_IDX 0x18d4 	///../ucode/register.h
#define P_GE2D_SCALE_COEF_IDX 		CBUS_REG_ADDR(GE2D_SCALE_COEF_IDX) 	///../ucode/register.h
#define GE2D_SCALE_COEF 0x18d5 	///../ucode/register.h
#define P_GE2D_SCALE_COEF 		CBUS_REG_ADDR(GE2D_SCALE_COEF) 	///../ucode/register.h
#define GE2D_SRC_OUTSIDE_ALPHA 0x18d6 	///../ucode/register.h
#define P_GE2D_SRC_OUTSIDE_ALPHA 		CBUS_REG_ADDR(GE2D_SRC_OUTSIDE_ALPHA) 	///../ucode/register.h
#define GE2D_ANTIFLICK_CTRL0 0x18d8 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_CTRL0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL0) 	///../ucode/register.h
#define GE2D_ANTIFLICK_CTRL1 0x18d9 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_CTRL1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_CTRL1) 	///../ucode/register.h
#define GE2D_ANTIFLICK_COLOR_FILT0 0x18da 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_COLOR_FILT0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT0) 	///../ucode/register.h
#define GE2D_ANTIFLICK_COLOR_FILT1 0x18db 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_COLOR_FILT1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT1) 	///../ucode/register.h
#define GE2D_ANTIFLICK_COLOR_FILT2 0x18dc 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_COLOR_FILT2 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT2) 	///../ucode/register.h
#define GE2D_ANTIFLICK_COLOR_FILT3 0x18dd 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_COLOR_FILT3 		CBUS_REG_ADDR(GE2D_ANTIFLICK_COLOR_FILT3) 	///../ucode/register.h
#define GE2D_ANTIFLICK_ALPHA_FILT0 0x18de 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_ALPHA_FILT0 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT0) 	///../ucode/register.h
#define GE2D_ANTIFLICK_ALPHA_FILT1 0x18df 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_ALPHA_FILT1 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT1) 	///../ucode/register.h
#define GE2D_ANTIFLICK_ALPHA_FILT2 0x18e0 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_ALPHA_FILT2 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT2) 	///../ucode/register.h
#define GE2D_ANTIFLICK_ALPHA_FILT3 0x18e1 	///../ucode/register.h
#define P_GE2D_ANTIFLICK_ALPHA_FILT3 		CBUS_REG_ADDR(GE2D_ANTIFLICK_ALPHA_FILT3) 	///../ucode/register.h
#define GE2D_SRC1_RANGE_MAP_Y_CTRL 0x18e3 	///../ucode/register.h
#define P_GE2D_SRC1_RANGE_MAP_Y_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_Y_CTRL) 	///../ucode/register.h
#define GE2D_SRC1_RANGE_MAP_CB_CTRL 0x18e4 	///../ucode/register.h
#define P_GE2D_SRC1_RANGE_MAP_CB_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CB_CTRL) 	///../ucode/register.h
#define GE2D_SRC1_RANGE_MAP_CR_CTRL 0x18e5 	///../ucode/register.h
#define P_GE2D_SRC1_RANGE_MAP_CR_CTRL 		CBUS_REG_ADDR(GE2D_SRC1_RANGE_MAP_CR_CTRL) 	///../ucode/register.h
#define GE2D_ARB_BURST_NUM 0x18e6 	///../ucode/register.h
#define P_GE2D_ARB_BURST_NUM 		CBUS_REG_ADDR(GE2D_ARB_BURST_NUM) 	///../ucode/register.h
#define GE2D_TID_TOKEN 0x18e7 	///../ucode/register.h
#define P_GE2D_TID_TOKEN 		CBUS_REG_ADDR(GE2D_TID_TOKEN) 	///../ucode/register.h
#define GE2D_GEN_CTRL3 0x18e8 	///../ucode/register.h
#define P_GE2D_GEN_CTRL3 		CBUS_REG_ADDR(GE2D_GEN_CTRL3) 	///../ucode/register.h
#define GE2D_STATUS2 0x18e9 	///../ucode/register.h
#define P_GE2D_STATUS2 		CBUS_REG_ADDR(GE2D_STATUS2) 	///../ucode/register.h
#define CSI2_CLK_RESET 0x2a00 	///../ucode/register.h
#define P_CSI2_CLK_RESET 		CBUS_REG_ADDR(CSI2_CLK_RESET) 	///../ucode/register.h
#define CSI2_GEN_CTRL0 0x2a01 	///../ucode/register.h
#define P_CSI2_GEN_CTRL0 		CBUS_REG_ADDR(CSI2_GEN_CTRL0) 	///../ucode/register.h
#define CSI2_FORCE_PIC_SIZE 0x2a02 	///../ucode/register.h
#define P_CSI2_FORCE_PIC_SIZE 		CBUS_REG_ADDR(CSI2_FORCE_PIC_SIZE) 	///../ucode/register.h
#define CSI2_DDR_START_ADDR 0x2a03 	///../ucode/register.h
#define P_CSI2_DDR_START_ADDR 		CBUS_REG_ADDR(CSI2_DDR_START_ADDR) 	///../ucode/register.h
#define CSI2_DDR_END_ADDR 0x2a04 	///../ucode/register.h
#define P_CSI2_DDR_END_ADDR 		CBUS_REG_ADDR(CSI2_DDR_END_ADDR) 	///../ucode/register.h
#define CSI2_INTERRUPT_CTRL_STAT 0x2a05 	///../ucode/register.h
#define P_CSI2_INTERRUPT_CTRL_STAT 		CBUS_REG_ADDR(CSI2_INTERRUPT_CTRL_STAT) 	///../ucode/register.h
#define CSI2_PIC_SIZE_STAT 0x2a06 	///../ucode/register.h
#define P_CSI2_PIC_SIZE_STAT 		CBUS_REG_ADDR(CSI2_PIC_SIZE_STAT) 	///../ucode/register.h
#define CSI2_GEN_STAT0 0x2a07 	///../ucode/register.h
#define P_CSI2_GEN_STAT0 		CBUS_REG_ADDR(CSI2_GEN_STAT0) 	///../ucode/register.h
#define CSI2_DDR_WRPT_STAT 0x2a08 	///../ucode/register.h
#define P_CSI2_DDR_WRPT_STAT 		CBUS_REG_ADDR(CSI2_DDR_WRPT_STAT) 	///../ucode/register.h
#define CSI2_FS_EMBED_DDR_START 0x2a09 	///../ucode/register.h
#define P_CSI2_FS_EMBED_DDR_START 		CBUS_REG_ADDR(CSI2_FS_EMBED_DDR_START) 	///../ucode/register.h
#define CSI2_FS_EMBED_DDR_END 0x2a0a 	///../ucode/register.h
#define P_CSI2_FS_EMBED_DDR_END 		CBUS_REG_ADDR(CSI2_FS_EMBED_DDR_END) 	///../ucode/register.h
#define CSI2_FE_EMBED_DDR_START 0x2a0b 	///../ucode/register.h
#define P_CSI2_FE_EMBED_DDR_START 		CBUS_REG_ADDR(CSI2_FE_EMBED_DDR_START) 	///../ucode/register.h
#define CSI2_FE_EMBED_DDR_END 0x2a0c 	///../ucode/register.h
#define P_CSI2_FE_EMBED_DDR_END 		CBUS_REG_ADDR(CSI2_FE_EMBED_DDR_END) 	///../ucode/register.h
#define CSI2_MEM_PIXEL_BYTE_CNT 0x2a0d 	///../ucode/register.h
#define P_CSI2_MEM_PIXEL_BYTE_CNT 		CBUS_REG_ADDR(CSI2_MEM_PIXEL_BYTE_CNT) 	///../ucode/register.h
#define CSI2_MEM_PIXEL_LINE_CNT 0x2a0e 	///../ucode/register.h
#define P_CSI2_MEM_PIXEL_LINE_CNT 		CBUS_REG_ADDR(CSI2_MEM_PIXEL_LINE_CNT) 	///../ucode/register.h
#define CSI2_PIXEL_DDR_START 0x2a0f 	///../ucode/register.h
#define P_CSI2_PIXEL_DDR_START 		CBUS_REG_ADDR(CSI2_PIXEL_DDR_START) 	///../ucode/register.h
#define CSI2_PIXEL_DDR_END 0x2a10 	///../ucode/register.h
#define P_CSI2_PIXEL_DDR_END 		CBUS_REG_ADDR(CSI2_PIXEL_DDR_END) 	///../ucode/register.h
#define CSI2_USER_DDR_START 0x2a11 	///../ucode/register.h
#define P_CSI2_USER_DDR_START 		CBUS_REG_ADDR(CSI2_USER_DDR_START) 	///../ucode/register.h
#define CSI2_USER_DDR_END 0x2a12 	///../ucode/register.h
#define P_CSI2_USER_DDR_END 		CBUS_REG_ADDR(CSI2_USER_DDR_END) 	///../ucode/register.h
#define CSI2_DATA_TYPE_IN_MEM 0x2a13 	///../ucode/register.h
#define P_CSI2_DATA_TYPE_IN_MEM 		CBUS_REG_ADDR(CSI2_DATA_TYPE_IN_MEM) 	///../ucode/register.h
#define CSI2_ERR_STAT0 0x2a14 	///../ucode/register.h
#define P_CSI2_ERR_STAT0 		CBUS_REG_ADDR(CSI2_ERR_STAT0) 	///../ucode/register.h
#define VIU_ADDR_START 0x1a00 	///../ucode/register.h
#define P_VIU_ADDR_START 		CBUS_REG_ADDR(VIU_ADDR_START) 	///../ucode/register.h
#define VIU_ADDR_END 0x1aff 	///../ucode/register.h
#define P_VIU_ADDR_END 		CBUS_REG_ADDR(VIU_ADDR_END) 	///../ucode/register.h
#define TRACE_REG 0x1a08 	///../ucode/register.h
#define P_TRACE_REG 		CBUS_REG_ADDR(TRACE_REG) 	///../ucode/register.h
#define VIU_SW_RESET 0x1a01 	///../ucode/register.h
#define P_VIU_SW_RESET 		CBUS_REG_ADDR(VIU_SW_RESET) 	///../ucode/register.h
#define VIU_OSD1_CTRL_STAT 0x1a10 	///../ucode/register.h
#define P_VIU_OSD1_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD1_CTRL_STAT) 	///../ucode/register.h
#define VIU_OSD1_CTRL_STAT2 0x1a2d 	///../ucode/register.h
#define P_VIU_OSD1_CTRL_STAT2 		CBUS_REG_ADDR(VIU_OSD1_CTRL_STAT2) 	///../ucode/register.h
#define VIU_OSD1_COLOR_ADDR 0x1a11 	///../ucode/register.h
#define P_VIU_OSD1_COLOR_ADDR 		CBUS_REG_ADDR(VIU_OSD1_COLOR_ADDR) 	///../ucode/register.h
#define VIU_OSD1_COLOR 0x1a12 	///../ucode/register.h
#define P_VIU_OSD1_COLOR 		CBUS_REG_ADDR(VIU_OSD1_COLOR) 	///../ucode/register.h
#define VIU_OSD1_TCOLOR_AG0 0x1a17 	///../ucode/register.h
#define P_VIU_OSD1_TCOLOR_AG0 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG0) 	///../ucode/register.h
#define VIU_OSD1_TCOLOR_AG1 0x1a18 	///../ucode/register.h
#define P_VIU_OSD1_TCOLOR_AG1 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG1) 	///../ucode/register.h
#define VIU_OSD1_TCOLOR_AG2 0x1a19 	///../ucode/register.h
#define P_VIU_OSD1_TCOLOR_AG2 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG2) 	///../ucode/register.h
#define VIU_OSD1_TCOLOR_AG3 0x1a1a 	///../ucode/register.h
#define P_VIU_OSD1_TCOLOR_AG3 		CBUS_REG_ADDR(VIU_OSD1_TCOLOR_AG3) 	///../ucode/register.h
#define VIU_OSD1_BLK0_CFG_W0 0x1a1b 	///../ucode/register.h
#define P_VIU_OSD1_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W0) 	///../ucode/register.h
#define VIU_OSD1_BLK1_CFG_W0 0x1a1f 	///../ucode/register.h
#define P_VIU_OSD1_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W0) 	///../ucode/register.h
#define VIU_OSD1_BLK2_CFG_W0 0x1a23 	///../ucode/register.h
#define P_VIU_OSD1_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W0) 	///../ucode/register.h
#define VIU_OSD1_BLK3_CFG_W0 0x1a27 	///../ucode/register.h
#define P_VIU_OSD1_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W0) 	///../ucode/register.h
#define VIU_OSD1_BLK0_CFG_W1 0x1a1c 	///../ucode/register.h
#define P_VIU_OSD1_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W1) 	///../ucode/register.h
#define VIU_OSD1_BLK1_CFG_W1 0x1a20 	///../ucode/register.h
#define P_VIU_OSD1_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W1) 	///../ucode/register.h
#define VIU_OSD1_BLK2_CFG_W1 0x1a24 	///../ucode/register.h
#define P_VIU_OSD1_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W1) 	///../ucode/register.h
#define VIU_OSD1_BLK3_CFG_W1 0x1a28 	///../ucode/register.h
#define P_VIU_OSD1_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W1) 	///../ucode/register.h
#define VIU_OSD1_BLK0_CFG_W2 0x1a1d 	///../ucode/register.h
#define P_VIU_OSD1_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W2) 	///../ucode/register.h
#define VIU_OSD1_BLK1_CFG_W2 0x1a21 	///../ucode/register.h
#define P_VIU_OSD1_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W2) 	///../ucode/register.h
#define VIU_OSD1_BLK2_CFG_W2 0x1a25 	///../ucode/register.h
#define P_VIU_OSD1_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W2) 	///../ucode/register.h
#define VIU_OSD1_BLK3_CFG_W2 0x1a29 	///../ucode/register.h
#define P_VIU_OSD1_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W2) 	///../ucode/register.h
#define VIU_OSD1_BLK0_CFG_W3 0x1a1e 	///../ucode/register.h
#define P_VIU_OSD1_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W3) 	///../ucode/register.h
#define VIU_OSD1_BLK1_CFG_W3 0x1a22 	///../ucode/register.h
#define P_VIU_OSD1_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W3) 	///../ucode/register.h
#define VIU_OSD1_BLK2_CFG_W3 0x1a26 	///../ucode/register.h
#define P_VIU_OSD1_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W3) 	///../ucode/register.h
#define VIU_OSD1_BLK3_CFG_W3 0x1a2a 	///../ucode/register.h
#define P_VIU_OSD1_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W3) 	///../ucode/register.h
#define VIU_OSD1_BLK0_CFG_W4 0x1a13 	///../ucode/register.h
#define P_VIU_OSD1_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK0_CFG_W4) 	///../ucode/register.h
#define VIU_OSD1_BLK1_CFG_W4 0x1a14 	///../ucode/register.h
#define P_VIU_OSD1_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK1_CFG_W4) 	///../ucode/register.h
#define VIU_OSD1_BLK2_CFG_W4 0x1a15 	///../ucode/register.h
#define P_VIU_OSD1_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK2_CFG_W4) 	///../ucode/register.h
#define VIU_OSD1_BLK3_CFG_W4 0x1a16 	///../ucode/register.h
#define P_VIU_OSD1_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU_OSD1_BLK3_CFG_W4) 	///../ucode/register.h
#define VIU_OSD1_FIFO_CTRL_STAT 0x1a2b 	///../ucode/register.h
#define P_VIU_OSD1_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD1_FIFO_CTRL_STAT) 	///../ucode/register.h
#define VIU_OSD1_TEST_RDDATA 0x1a2c 	///../ucode/register.h
#define P_VIU_OSD1_TEST_RDDATA 		CBUS_REG_ADDR(VIU_OSD1_TEST_RDDATA) 	///../ucode/register.h
#define VIU_OSD2_CTRL_STAT 0x1a30 	///../ucode/register.h
#define P_VIU_OSD2_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD2_CTRL_STAT) 	///../ucode/register.h
#define VIU_OSD2_CTRL_STAT2 0x1a4d 	///../ucode/register.h
#define P_VIU_OSD2_CTRL_STAT2 		CBUS_REG_ADDR(VIU_OSD2_CTRL_STAT2) 	///../ucode/register.h
#define VIU_OSD2_COLOR_ADDR 0x1a31 	///../ucode/register.h
#define P_VIU_OSD2_COLOR_ADDR 		CBUS_REG_ADDR(VIU_OSD2_COLOR_ADDR) 	///../ucode/register.h
#define VIU_OSD2_COLOR 0x1a32 	///../ucode/register.h
#define P_VIU_OSD2_COLOR 		CBUS_REG_ADDR(VIU_OSD2_COLOR) 	///../ucode/register.h
#define VIU_OSD2_HL1_H_START_END 0x1a33 	///../ucode/register.h
#define P_VIU_OSD2_HL1_H_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL1_H_START_END) 	///../ucode/register.h
#define VIU_OSD2_HL1_V_START_END 0x1a34 	///../ucode/register.h
#define P_VIU_OSD2_HL1_V_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL1_V_START_END) 	///../ucode/register.h
#define VIU_OSD2_HL2_H_START_END 0x1a35 	///../ucode/register.h
#define P_VIU_OSD2_HL2_H_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL2_H_START_END) 	///../ucode/register.h
#define VIU_OSD2_HL2_V_START_END 0x1a36 	///../ucode/register.h
#define P_VIU_OSD2_HL2_V_START_END 		CBUS_REG_ADDR(VIU_OSD2_HL2_V_START_END) 	///../ucode/register.h
#define VIU_OSD2_TCOLOR_AG0 0x1a37 	///../ucode/register.h
#define P_VIU_OSD2_TCOLOR_AG0 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG0) 	///../ucode/register.h
#define VIU_OSD2_TCOLOR_AG1 0x1a38 	///../ucode/register.h
#define P_VIU_OSD2_TCOLOR_AG1 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG1) 	///../ucode/register.h
#define VIU_OSD2_TCOLOR_AG2 0x1a39 	///../ucode/register.h
#define P_VIU_OSD2_TCOLOR_AG2 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG2) 	///../ucode/register.h
#define VIU_OSD2_TCOLOR_AG3 0x1a3a 	///../ucode/register.h
#define P_VIU_OSD2_TCOLOR_AG3 		CBUS_REG_ADDR(VIU_OSD2_TCOLOR_AG3) 	///../ucode/register.h
#define VIU_OSD2_BLK0_CFG_W0 0x1a3b 	///../ucode/register.h
#define P_VIU_OSD2_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W0) 	///../ucode/register.h
#define VIU_OSD2_BLK1_CFG_W0 0x1a3f 	///../ucode/register.h
#define P_VIU_OSD2_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W0) 	///../ucode/register.h
#define VIU_OSD2_BLK2_CFG_W0 0x1a43 	///../ucode/register.h
#define P_VIU_OSD2_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W0) 	///../ucode/register.h
#define VIU_OSD2_BLK3_CFG_W0 0x1a47 	///../ucode/register.h
#define P_VIU_OSD2_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W0) 	///../ucode/register.h
#define VIU_OSD2_BLK0_CFG_W1 0x1a3c 	///../ucode/register.h
#define P_VIU_OSD2_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W1) 	///../ucode/register.h
#define VIU_OSD2_BLK1_CFG_W1 0x1a40 	///../ucode/register.h
#define P_VIU_OSD2_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W1) 	///../ucode/register.h
#define VIU_OSD2_BLK2_CFG_W1 0x1a44 	///../ucode/register.h
#define P_VIU_OSD2_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W1) 	///../ucode/register.h
#define VIU_OSD2_BLK3_CFG_W1 0x1a48 	///../ucode/register.h
#define P_VIU_OSD2_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W1) 	///../ucode/register.h
#define VIU_OSD2_BLK0_CFG_W2 0x1a3d 	///../ucode/register.h
#define P_VIU_OSD2_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W2) 	///../ucode/register.h
#define VIU_OSD2_BLK1_CFG_W2 0x1a41 	///../ucode/register.h
#define P_VIU_OSD2_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W2) 	///../ucode/register.h
#define VIU_OSD2_BLK2_CFG_W2 0x1a45 	///../ucode/register.h
#define P_VIU_OSD2_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W2) 	///../ucode/register.h
#define VIU_OSD2_BLK3_CFG_W2 0x1a49 	///../ucode/register.h
#define P_VIU_OSD2_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W2) 	///../ucode/register.h
#define VIU_OSD2_BLK0_CFG_W3 0x1a3e 	///../ucode/register.h
#define P_VIU_OSD2_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W3) 	///../ucode/register.h
#define VIU_OSD2_BLK1_CFG_W3 0x1a42 	///../ucode/register.h
#define P_VIU_OSD2_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W3) 	///../ucode/register.h
#define VIU_OSD2_BLK2_CFG_W3 0x1a46 	///../ucode/register.h
#define P_VIU_OSD2_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W3) 	///../ucode/register.h
#define VIU_OSD2_BLK3_CFG_W3 0x1a4a 	///../ucode/register.h
#define P_VIU_OSD2_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W3) 	///../ucode/register.h
#define VIU_OSD2_BLK0_CFG_W4 0x1a64 	///../ucode/register.h
#define P_VIU_OSD2_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK0_CFG_W4) 	///../ucode/register.h
#define VIU_OSD2_BLK1_CFG_W4 0x1a65 	///../ucode/register.h
#define P_VIU_OSD2_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK1_CFG_W4) 	///../ucode/register.h
#define VIU_OSD2_BLK2_CFG_W4 0x1a66 	///../ucode/register.h
#define P_VIU_OSD2_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK2_CFG_W4) 	///../ucode/register.h
#define VIU_OSD2_BLK3_CFG_W4 0x1a67 	///../ucode/register.h
#define P_VIU_OSD2_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU_OSD2_BLK3_CFG_W4) 	///../ucode/register.h
#define VIU_OSD2_FIFO_CTRL_STAT 0x1a4b 	///../ucode/register.h
#define P_VIU_OSD2_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU_OSD2_FIFO_CTRL_STAT) 	///../ucode/register.h
#define VIU_OSD2_TEST_RDDATA 0x1a4c 	///../ucode/register.h
#define P_VIU_OSD2_TEST_RDDATA 		CBUS_REG_ADDR(VIU_OSD2_TEST_RDDATA) 	///../ucode/register.h
#define VD1_IF0_GEN_REG 0x1a50 	///../ucode/register.h
#define P_VD1_IF0_GEN_REG 		CBUS_REG_ADDR(VD1_IF0_GEN_REG) 	///../ucode/register.h
#define VD1_IF0_CANVAS0 0x1a51 	///../ucode/register.h
#define P_VD1_IF0_CANVAS0 		CBUS_REG_ADDR(VD1_IF0_CANVAS0) 	///../ucode/register.h
#define VD1_IF0_CANVAS1 0x1a52 	///../ucode/register.h
#define P_VD1_IF0_CANVAS1 		CBUS_REG_ADDR(VD1_IF0_CANVAS1) 	///../ucode/register.h
#define VD1_IF0_LUMA_X0 0x1a53 	///../ucode/register.h
#define P_VD1_IF0_LUMA_X0 		CBUS_REG_ADDR(VD1_IF0_LUMA_X0) 	///../ucode/register.h
#define VD1_IF0_LUMA_Y0 0x1a54 	///../ucode/register.h
#define P_VD1_IF0_LUMA_Y0 		CBUS_REG_ADDR(VD1_IF0_LUMA_Y0) 	///../ucode/register.h
#define VD1_IF0_CHROMA_X0 0x1a55 	///../ucode/register.h
#define P_VD1_IF0_CHROMA_X0 		CBUS_REG_ADDR(VD1_IF0_CHROMA_X0) 	///../ucode/register.h
#define VD1_IF0_CHROMA_Y0 0x1a56 	///../ucode/register.h
#define P_VD1_IF0_CHROMA_Y0 		CBUS_REG_ADDR(VD1_IF0_CHROMA_Y0) 	///../ucode/register.h
#define VD1_IF0_LUMA_X1 0x1a57 	///../ucode/register.h
#define P_VD1_IF0_LUMA_X1 		CBUS_REG_ADDR(VD1_IF0_LUMA_X1) 	///../ucode/register.h
#define VD1_IF0_LUMA_Y1 0x1a58 	///../ucode/register.h
#define P_VD1_IF0_LUMA_Y1 		CBUS_REG_ADDR(VD1_IF0_LUMA_Y1) 	///../ucode/register.h
#define VD1_IF0_CHROMA_X1 0x1a59 	///../ucode/register.h
#define P_VD1_IF0_CHROMA_X1 		CBUS_REG_ADDR(VD1_IF0_CHROMA_X1) 	///../ucode/register.h
#define VD1_IF0_CHROMA_Y1 0x1a5a 	///../ucode/register.h
#define P_VD1_IF0_CHROMA_Y1 		CBUS_REG_ADDR(VD1_IF0_CHROMA_Y1) 	///../ucode/register.h
#define VD1_IF0_RPT_LOOP 0x1a5b 	///../ucode/register.h
#define P_VD1_IF0_RPT_LOOP 		CBUS_REG_ADDR(VD1_IF0_RPT_LOOP) 	///../ucode/register.h
#define VD1_IF0_LUMA0_RPT_PAT 0x1a5c 	///../ucode/register.h
#define P_VD1_IF0_LUMA0_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_LUMA0_RPT_PAT) 	///../ucode/register.h
#define VD1_IF0_CHROMA0_RPT_PAT 0x1a5d 	///../ucode/register.h
#define P_VD1_IF0_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_CHROMA0_RPT_PAT) 	///../ucode/register.h
#define VD1_IF0_LUMA1_RPT_PAT 0x1a5e 	///../ucode/register.h
#define P_VD1_IF0_LUMA1_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_LUMA1_RPT_PAT) 	///../ucode/register.h
#define VD1_IF0_CHROMA1_RPT_PAT 0x1a5f 	///../ucode/register.h
#define P_VD1_IF0_CHROMA1_RPT_PAT 		CBUS_REG_ADDR(VD1_IF0_CHROMA1_RPT_PAT) 	///../ucode/register.h
#define VD1_IF0_LUMA_PSEL 0x1a60 	///../ucode/register.h
#define P_VD1_IF0_LUMA_PSEL 		CBUS_REG_ADDR(VD1_IF0_LUMA_PSEL) 	///../ucode/register.h
#define VD1_IF0_CHROMA_PSEL 0x1a61 	///../ucode/register.h
#define P_VD1_IF0_CHROMA_PSEL 		CBUS_REG_ADDR(VD1_IF0_CHROMA_PSEL) 	///../ucode/register.h
#define VD1_IF0_DUMMY_PIXEL 0x1a62 	///../ucode/register.h
#define P_VD1_IF0_DUMMY_PIXEL 		CBUS_REG_ADDR(VD1_IF0_DUMMY_PIXEL) 	///../ucode/register.h
#define VD1_IF0_LUMA_FIFO_SIZE 0x1a63 	///../ucode/register.h
#define P_VD1_IF0_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(VD1_IF0_LUMA_FIFO_SIZE) 	///../ucode/register.h
#define VD1_IF0_RANGE_MAP_Y 0x1a6a 	///../ucode/register.h
#define P_VD1_IF0_RANGE_MAP_Y 		CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_Y) 	///../ucode/register.h
#define VD1_IF0_RANGE_MAP_CB 0x1a6b 	///../ucode/register.h
#define P_VD1_IF0_RANGE_MAP_CB 		CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CB) 	///../ucode/register.h
#define VD1_IF0_RANGE_MAP_CR 0x1a6c 	///../ucode/register.h
#define P_VD1_IF0_RANGE_MAP_CR 		CBUS_REG_ADDR(VD1_IF0_RANGE_MAP_CR) 	///../ucode/register.h
#define VD1_IF0_GEN_REG2 0x1a6d 	///../ucode/register.h
#define P_VD1_IF0_GEN_REG2 		CBUS_REG_ADDR(VD1_IF0_GEN_REG2) 	///../ucode/register.h
#define VIU_VD1_FMT_CTRL 0x1a68 	///../ucode/register.h
#define P_VIU_VD1_FMT_CTRL 		CBUS_REG_ADDR(VIU_VD1_FMT_CTRL) 	///../ucode/register.h
#define VIU_VD1_FMT_W 0x1a69 	///../ucode/register.h
#define P_VIU_VD1_FMT_W 		CBUS_REG_ADDR(VIU_VD1_FMT_W) 	///../ucode/register.h
#define VD2_IF0_GEN_REG 0x1a70 	///../ucode/register.h
#define P_VD2_IF0_GEN_REG 		CBUS_REG_ADDR(VD2_IF0_GEN_REG) 	///../ucode/register.h
#define VD2_IF0_CANVAS0 0x1a71 	///../ucode/register.h
#define P_VD2_IF0_CANVAS0 		CBUS_REG_ADDR(VD2_IF0_CANVAS0) 	///../ucode/register.h
#define VD2_IF0_CANVAS1 0x1a72 	///../ucode/register.h
#define P_VD2_IF0_CANVAS1 		CBUS_REG_ADDR(VD2_IF0_CANVAS1) 	///../ucode/register.h
#define VD2_IF0_LUMA_X0 0x1a73 	///../ucode/register.h
#define P_VD2_IF0_LUMA_X0 		CBUS_REG_ADDR(VD2_IF0_LUMA_X0) 	///../ucode/register.h
#define VD2_IF0_LUMA_Y0 0x1a74 	///../ucode/register.h
#define P_VD2_IF0_LUMA_Y0 		CBUS_REG_ADDR(VD2_IF0_LUMA_Y0) 	///../ucode/register.h
#define VD2_IF0_CHROMA_X0 0x1a75 	///../ucode/register.h
#define P_VD2_IF0_CHROMA_X0 		CBUS_REG_ADDR(VD2_IF0_CHROMA_X0) 	///../ucode/register.h
#define VD2_IF0_CHROMA_Y0 0x1a76 	///../ucode/register.h
#define P_VD2_IF0_CHROMA_Y0 		CBUS_REG_ADDR(VD2_IF0_CHROMA_Y0) 	///../ucode/register.h
#define VD2_IF0_LUMA_X1 0x1a77 	///../ucode/register.h
#define P_VD2_IF0_LUMA_X1 		CBUS_REG_ADDR(VD2_IF0_LUMA_X1) 	///../ucode/register.h
#define VD2_IF0_LUMA_Y1 0x1a78 	///../ucode/register.h
#define P_VD2_IF0_LUMA_Y1 		CBUS_REG_ADDR(VD2_IF0_LUMA_Y1) 	///../ucode/register.h
#define VD2_IF0_CHROMA_X1 0x1a79 	///../ucode/register.h
#define P_VD2_IF0_CHROMA_X1 		CBUS_REG_ADDR(VD2_IF0_CHROMA_X1) 	///../ucode/register.h
#define VD2_IF0_CHROMA_Y1 0x1a7a 	///../ucode/register.h
#define P_VD2_IF0_CHROMA_Y1 		CBUS_REG_ADDR(VD2_IF0_CHROMA_Y1) 	///../ucode/register.h
#define VD2_IF0_RPT_LOOP 0x1a7b 	///../ucode/register.h
#define P_VD2_IF0_RPT_LOOP 		CBUS_REG_ADDR(VD2_IF0_RPT_LOOP) 	///../ucode/register.h
#define VD2_IF0_LUMA0_RPT_PAT 0x1a7c 	///../ucode/register.h
#define P_VD2_IF0_LUMA0_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_LUMA0_RPT_PAT) 	///../ucode/register.h
#define VD2_IF0_CHROMA0_RPT_PAT 0x1a7d 	///../ucode/register.h
#define P_VD2_IF0_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_CHROMA0_RPT_PAT) 	///../ucode/register.h
#define VD2_IF0_LUMA1_RPT_PAT 0x1a7e 	///../ucode/register.h
#define P_VD2_IF0_LUMA1_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_LUMA1_RPT_PAT) 	///../ucode/register.h
#define VD2_IF0_CHROMA1_RPT_PAT 0x1a7f 	///../ucode/register.h
#define P_VD2_IF0_CHROMA1_RPT_PAT 		CBUS_REG_ADDR(VD2_IF0_CHROMA1_RPT_PAT) 	///../ucode/register.h
#define VD2_IF0_LUMA_PSEL 0x1a80 	///../ucode/register.h
#define P_VD2_IF0_LUMA_PSEL 		CBUS_REG_ADDR(VD2_IF0_LUMA_PSEL) 	///../ucode/register.h
#define VD2_IF0_CHROMA_PSEL 0x1a81 	///../ucode/register.h
#define P_VD2_IF0_CHROMA_PSEL 		CBUS_REG_ADDR(VD2_IF0_CHROMA_PSEL) 	///../ucode/register.h
#define VD2_IF0_DUMMY_PIXEL 0x1a82 	///../ucode/register.h
#define P_VD2_IF0_DUMMY_PIXEL 		CBUS_REG_ADDR(VD2_IF0_DUMMY_PIXEL) 	///../ucode/register.h
#define VD2_IF0_LUMA_FIFO_SIZE 0x1a83 	///../ucode/register.h
#define P_VD2_IF0_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(VD2_IF0_LUMA_FIFO_SIZE) 	///../ucode/register.h
#define VD2_IF0_RANGE_MAP_Y 0x1a8a 	///../ucode/register.h
#define P_VD2_IF0_RANGE_MAP_Y 		CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_Y) 	///../ucode/register.h
#define VD2_IF0_RANGE_MAP_CB 0x1a8b 	///../ucode/register.h
#define P_VD2_IF0_RANGE_MAP_CB 		CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CB) 	///../ucode/register.h
#define VD2_IF0_RANGE_MAP_CR 0x1a8c 	///../ucode/register.h
#define P_VD2_IF0_RANGE_MAP_CR 		CBUS_REG_ADDR(VD2_IF0_RANGE_MAP_CR) 	///../ucode/register.h
#define VD2_IF0_GEN_REG2 0x1a8d 	///../ucode/register.h
#define P_VD2_IF0_GEN_REG2 		CBUS_REG_ADDR(VD2_IF0_GEN_REG2) 	///../ucode/register.h
#define VIU_VD2_FMT_CTRL 0x1a88 	///../ucode/register.h
#define P_VIU_VD2_FMT_CTRL 		CBUS_REG_ADDR(VIU_VD2_FMT_CTRL) 	///../ucode/register.h
#define VIU_VD2_FMT_W 0x1a89 	///../ucode/register.h
#define P_VIU_VD2_FMT_W 		CBUS_REG_ADDR(VIU_VD2_FMT_W) 	///../ucode/register.h
#define DI_PRE_CTRL 0x1700 	///../ucode/register.h
#define P_DI_PRE_CTRL 		CBUS_REG_ADDR(DI_PRE_CTRL) 	///../ucode/register.h
#define DI_POST_CTRL 0x1701 	///../ucode/register.h
#define P_DI_POST_CTRL 		CBUS_REG_ADDR(DI_POST_CTRL) 	///../ucode/register.h
#define DI_POST_SIZE 0x1702 	///../ucode/register.h
#define P_DI_POST_SIZE 		CBUS_REG_ADDR(DI_POST_SIZE) 	///../ucode/register.h
#define DI_PRE_SIZE 0x1703 	///../ucode/register.h
#define P_DI_PRE_SIZE 		CBUS_REG_ADDR(DI_PRE_SIZE) 	///../ucode/register.h
#define DI_EI_CTRL0 0x1704 	///../ucode/register.h
#define P_DI_EI_CTRL0 		CBUS_REG_ADDR(DI_EI_CTRL0) 	///../ucode/register.h
#define DI_EI_CTRL1 0x1705 	///../ucode/register.h
#define P_DI_EI_CTRL1 		CBUS_REG_ADDR(DI_EI_CTRL1) 	///../ucode/register.h
#define DI_EI_CTRL2 0x1706 	///../ucode/register.h
#define P_DI_EI_CTRL2 		CBUS_REG_ADDR(DI_EI_CTRL2) 	///../ucode/register.h
#define DI_NR_CTRL0 0x1707 	///../ucode/register.h
#define P_DI_NR_CTRL0 		CBUS_REG_ADDR(DI_NR_CTRL0) 	///../ucode/register.h
#define DI_NR_CTRL1 0x1708 	///../ucode/register.h
#define P_DI_NR_CTRL1 		CBUS_REG_ADDR(DI_NR_CTRL1) 	///../ucode/register.h
#define DI_NR_CTRL2 0x1709 	///../ucode/register.h
#define P_DI_NR_CTRL2 		CBUS_REG_ADDR(DI_NR_CTRL2) 	///../ucode/register.h
#define DI_NR_CTRL3 0x170a 	///../ucode/register.h
#define P_DI_NR_CTRL3 		CBUS_REG_ADDR(DI_NR_CTRL3) 	///../ucode/register.h
#define DI_MTN_CTRL 0x170b 	///../ucode/register.h
#define P_DI_MTN_CTRL 		CBUS_REG_ADDR(DI_MTN_CTRL) 	///../ucode/register.h
#define DI_MTN_CTRL1 0x170c 	///../ucode/register.h
#define P_DI_MTN_CTRL1 		CBUS_REG_ADDR(DI_MTN_CTRL1) 	///../ucode/register.h
#define DI_BLEND_CTRL 0x170d 	///../ucode/register.h
#define P_DI_BLEND_CTRL 		CBUS_REG_ADDR(DI_BLEND_CTRL) 	///../ucode/register.h
#define DI_BLEND_CTRL1 0x170e 	///../ucode/register.h
#define P_DI_BLEND_CTRL1 		CBUS_REG_ADDR(DI_BLEND_CTRL1) 	///../ucode/register.h
#define DI_BLEND_CTRL2 0x170f 	///../ucode/register.h
#define P_DI_BLEND_CTRL2 		CBUS_REG_ADDR(DI_BLEND_CTRL2) 	///../ucode/register.h
#define DI_BLEND_REG0_X 0x1710 	///../ucode/register.h
#define P_DI_BLEND_REG0_X 		CBUS_REG_ADDR(DI_BLEND_REG0_X) 	///../ucode/register.h
#define DI_BLEND_REG0_Y 0x1711 	///../ucode/register.h
#define P_DI_BLEND_REG0_Y 		CBUS_REG_ADDR(DI_BLEND_REG0_Y) 	///../ucode/register.h
#define DI_BLEND_REG1_X 0x1712 	///../ucode/register.h
#define P_DI_BLEND_REG1_X 		CBUS_REG_ADDR(DI_BLEND_REG1_X) 	///../ucode/register.h
#define DI_BLEND_REG1_Y 0x1713 	///../ucode/register.h
#define P_DI_BLEND_REG1_Y 		CBUS_REG_ADDR(DI_BLEND_REG1_Y) 	///../ucode/register.h
#define DI_BLEND_REG2_X 0x1714 	///../ucode/register.h
#define P_DI_BLEND_REG2_X 		CBUS_REG_ADDR(DI_BLEND_REG2_X) 	///../ucode/register.h
#define DI_BLEND_REG2_Y 0x1715 	///../ucode/register.h
#define P_DI_BLEND_REG2_Y 		CBUS_REG_ADDR(DI_BLEND_REG2_Y) 	///../ucode/register.h
#define DI_BLEND_REG3_X 0x1716 	///../ucode/register.h
#define P_DI_BLEND_REG3_X 		CBUS_REG_ADDR(DI_BLEND_REG3_X) 	///../ucode/register.h
#define DI_BLEND_REG3_Y 0x1717 	///../ucode/register.h
#define P_DI_BLEND_REG3_Y 		CBUS_REG_ADDR(DI_BLEND_REG3_Y) 	///../ucode/register.h
#define DI_CLKG_CTRL 0x1718 	///../ucode/register.h
#define P_DI_CLKG_CTRL 		CBUS_REG_ADDR(DI_CLKG_CTRL) 	///../ucode/register.h
#define DI_MC_REG0_X 0x1720 	///../ucode/register.h
#define P_DI_MC_REG0_X 		CBUS_REG_ADDR(DI_MC_REG0_X) 	///../ucode/register.h
#define DI_MC_REG0_Y 0x1721 	///../ucode/register.h
#define P_DI_MC_REG0_Y 		CBUS_REG_ADDR(DI_MC_REG0_Y) 	///../ucode/register.h
#define DI_MC_REG1_X 0x1722 	///../ucode/register.h
#define P_DI_MC_REG1_X 		CBUS_REG_ADDR(DI_MC_REG1_X) 	///../ucode/register.h
#define DI_MC_REG1_Y 0x1723 	///../ucode/register.h
#define P_DI_MC_REG1_Y 		CBUS_REG_ADDR(DI_MC_REG1_Y) 	///../ucode/register.h
#define DI_MC_REG2_X 0x1724 	///../ucode/register.h
#define P_DI_MC_REG2_X 		CBUS_REG_ADDR(DI_MC_REG2_X) 	///../ucode/register.h
#define DI_MC_REG2_Y 0x1725 	///../ucode/register.h
#define P_DI_MC_REG2_Y 		CBUS_REG_ADDR(DI_MC_REG2_Y) 	///../ucode/register.h
#define DI_MC_REG3_X 0x1726 	///../ucode/register.h
#define P_DI_MC_REG3_X 		CBUS_REG_ADDR(DI_MC_REG3_X) 	///../ucode/register.h
#define DI_MC_REG3_Y 0x1727 	///../ucode/register.h
#define P_DI_MC_REG3_Y 		CBUS_REG_ADDR(DI_MC_REG3_Y) 	///../ucode/register.h
#define DI_MC_REG4_X 0x1728 	///../ucode/register.h
#define P_DI_MC_REG4_X 		CBUS_REG_ADDR(DI_MC_REG4_X) 	///../ucode/register.h
#define DI_MC_REG4_Y 0x1729 	///../ucode/register.h
#define P_DI_MC_REG4_Y 		CBUS_REG_ADDR(DI_MC_REG4_Y) 	///../ucode/register.h
#define DI_MC_32LVL0 0x172a 	///../ucode/register.h
#define P_DI_MC_32LVL0 		CBUS_REG_ADDR(DI_MC_32LVL0) 	///../ucode/register.h
#define DI_MC_32LVL1 0x172b 	///../ucode/register.h
#define P_DI_MC_32LVL1 		CBUS_REG_ADDR(DI_MC_32LVL1) 	///../ucode/register.h
#define DI_MC_22LVL0 0x172c 	///../ucode/register.h
#define P_DI_MC_22LVL0 		CBUS_REG_ADDR(DI_MC_22LVL0) 	///../ucode/register.h
#define DI_MC_22LVL1 0x172d 	///../ucode/register.h
#define P_DI_MC_22LVL1 		CBUS_REG_ADDR(DI_MC_22LVL1) 	///../ucode/register.h
#define DI_MC_22LVL2 0x172e 	///../ucode/register.h
#define P_DI_MC_22LVL2 		CBUS_REG_ADDR(DI_MC_22LVL2) 	///../ucode/register.h
#define DI_MC_CTRL 0x172f 	///../ucode/register.h
#define P_DI_MC_CTRL 		CBUS_REG_ADDR(DI_MC_CTRL) 	///../ucode/register.h
#define DI_INTR_CTRL 0x1730 	///../ucode/register.h
#define P_DI_INTR_CTRL 		CBUS_REG_ADDR(DI_INTR_CTRL) 	///../ucode/register.h
#define DI_INFO_ADDR 0x1731 	///../ucode/register.h
#define P_DI_INFO_ADDR 		CBUS_REG_ADDR(DI_INFO_ADDR) 	///../ucode/register.h
#define DI_INFO_DATA 0x1732 	///../ucode/register.h
#define P_DI_INFO_DATA 		CBUS_REG_ADDR(DI_INFO_DATA) 	///../ucode/register.h
#define DI_PRE_HOLD 0x1733 	///../ucode/register.h
#define P_DI_PRE_HOLD 		CBUS_REG_ADDR(DI_PRE_HOLD) 	///../ucode/register.h
#define DI_NRWR_X 0x17c0 	///../ucode/register.h
#define P_DI_NRWR_X 		CBUS_REG_ADDR(DI_NRWR_X) 	///../ucode/register.h
#define DI_NRWR_Y 0x17c1 	///../ucode/register.h
#define P_DI_NRWR_Y 		CBUS_REG_ADDR(DI_NRWR_Y) 	///../ucode/register.h
#define DI_NRWR_CTRL 0x17c2 	///../ucode/register.h
#define P_DI_NRWR_CTRL 		CBUS_REG_ADDR(DI_NRWR_CTRL) 	///../ucode/register.h
#define DI_MTNWR_X 0x17c3 	///../ucode/register.h
#define P_DI_MTNWR_X 		CBUS_REG_ADDR(DI_MTNWR_X) 	///../ucode/register.h
#define DI_MTNWR_Y 0x17c4 	///../ucode/register.h
#define P_DI_MTNWR_Y 		CBUS_REG_ADDR(DI_MTNWR_Y) 	///../ucode/register.h
#define DI_MTNWR_CTRL 0x17c5 	///../ucode/register.h
#define P_DI_MTNWR_CTRL 		CBUS_REG_ADDR(DI_MTNWR_CTRL) 	///../ucode/register.h
#define DI_DIWR_X 0x17c6 	///../ucode/register.h
#define P_DI_DIWR_X 		CBUS_REG_ADDR(DI_DIWR_X) 	///../ucode/register.h
#define DI_DIWR_Y 0x17c7 	///../ucode/register.h
#define P_DI_DIWR_Y 		CBUS_REG_ADDR(DI_DIWR_Y) 	///../ucode/register.h
#define DI_DIWR_CTRL 0x17c8 	///../ucode/register.h
#define P_DI_DIWR_CTRL 		CBUS_REG_ADDR(DI_DIWR_CTRL) 	///../ucode/register.h
#define DI_MTNCRD_X 0x17c9 	///../ucode/register.h
#define P_DI_MTNCRD_X 		CBUS_REG_ADDR(DI_MTNCRD_X) 	///../ucode/register.h
#define DI_MTNCRD_Y 0x17ca 	///../ucode/register.h
#define P_DI_MTNCRD_Y 		CBUS_REG_ADDR(DI_MTNCRD_Y) 	///../ucode/register.h
#define DI_MTNPRD_X 0x17cb 	///../ucode/register.h
#define P_DI_MTNPRD_X 		CBUS_REG_ADDR(DI_MTNPRD_X) 	///../ucode/register.h
#define DI_MTNPRD_Y 0x17cc 	///../ucode/register.h
#define P_DI_MTNPRD_Y 		CBUS_REG_ADDR(DI_MTNPRD_Y) 	///../ucode/register.h
#define DI_MTNRD_CTRL 0x17cd 	///../ucode/register.h
#define P_DI_MTNRD_CTRL 		CBUS_REG_ADDR(DI_MTNRD_CTRL) 	///../ucode/register.h
#define DI_INP_GEN_REG 0x17ce 	///../ucode/register.h
#define P_DI_INP_GEN_REG 		CBUS_REG_ADDR(DI_INP_GEN_REG) 	///../ucode/register.h
#define DI_INP_CANVAS0 0x17cf 	///../ucode/register.h
#define P_DI_INP_CANVAS0 		CBUS_REG_ADDR(DI_INP_CANVAS0) 	///../ucode/register.h
#define DI_INP_LUMA_X0 0x17d0 	///../ucode/register.h
#define P_DI_INP_LUMA_X0 		CBUS_REG_ADDR(DI_INP_LUMA_X0) 	///../ucode/register.h
#define DI_INP_LUMA_Y0 0x17d1 	///../ucode/register.h
#define P_DI_INP_LUMA_Y0 		CBUS_REG_ADDR(DI_INP_LUMA_Y0) 	///../ucode/register.h
#define DI_INP_CHROMA_X0 0x17d2 	///../ucode/register.h
#define P_DI_INP_CHROMA_X0 		CBUS_REG_ADDR(DI_INP_CHROMA_X0) 	///../ucode/register.h
#define DI_INP_CHROMA_Y0 0x17d3 	///../ucode/register.h
#define P_DI_INP_CHROMA_Y0 		CBUS_REG_ADDR(DI_INP_CHROMA_Y0) 	///../ucode/register.h
#define DI_INP_RPT_LOOP 0x17d4 	///../ucode/register.h
#define P_DI_INP_RPT_LOOP 		CBUS_REG_ADDR(DI_INP_RPT_LOOP) 	///../ucode/register.h
#define DI_INP_LUMA0_RPT_PAT 0x17d5 	///../ucode/register.h
#define P_DI_INP_LUMA0_RPT_PAT 		CBUS_REG_ADDR(DI_INP_LUMA0_RPT_PAT) 	///../ucode/register.h
#define DI_INP_CHROMA0_RPT_PAT 0x17d6 	///../ucode/register.h
#define P_DI_INP_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(DI_INP_CHROMA0_RPT_PAT) 	///../ucode/register.h
#define DI_INP_DUMMY_PIXEL 0x17d7 	///../ucode/register.h
#define P_DI_INP_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_INP_DUMMY_PIXEL) 	///../ucode/register.h
#define DI_INP_LUMA_FIFO_SIZE 0x17d8 	///../ucode/register.h
#define P_DI_INP_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(DI_INP_LUMA_FIFO_SIZE) 	///../ucode/register.h
#define DI_INP_RANGE_MAP_Y 0x17ba 	///../ucode/register.h
#define P_DI_INP_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_INP_RANGE_MAP_Y) 	///../ucode/register.h
#define DI_INP_RANGE_MAP_CB 0x17bb 	///../ucode/register.h
#define P_DI_INP_RANGE_MAP_CB 		CBUS_REG_ADDR(DI_INP_RANGE_MAP_CB) 	///../ucode/register.h
#define DI_INP_RANGE_MAP_CR 0x17bc 	///../ucode/register.h
#define P_DI_INP_RANGE_MAP_CR 		CBUS_REG_ADDR(DI_INP_RANGE_MAP_CR) 	///../ucode/register.h
#define DI_INP_GEN_REG2 0x1791 	///../ucode/register.h
#define P_DI_INP_GEN_REG2 		CBUS_REG_ADDR(DI_INP_GEN_REG2) 	///../ucode/register.h
#define DI_INP_FMT_CTRL 0x17d9 	///../ucode/register.h
#define P_DI_INP_FMT_CTRL 		CBUS_REG_ADDR(DI_INP_FMT_CTRL) 	///../ucode/register.h
#define DI_INP_FMT_W 0x17da 	///../ucode/register.h
#define P_DI_INP_FMT_W 		CBUS_REG_ADDR(DI_INP_FMT_W) 	///../ucode/register.h
#define DI_MEM_GEN_REG 0x17db 	///../ucode/register.h
#define P_DI_MEM_GEN_REG 		CBUS_REG_ADDR(DI_MEM_GEN_REG) 	///../ucode/register.h
#define DI_MEM_CANVAS0 0x17dc 	///../ucode/register.h
#define P_DI_MEM_CANVAS0 		CBUS_REG_ADDR(DI_MEM_CANVAS0) 	///../ucode/register.h
#define DI_MEM_LUMA_X0 0x17dd 	///../ucode/register.h
#define P_DI_MEM_LUMA_X0 		CBUS_REG_ADDR(DI_MEM_LUMA_X0) 	///../ucode/register.h
#define DI_MEM_LUMA_Y0 0x17de 	///../ucode/register.h
#define P_DI_MEM_LUMA_Y0 		CBUS_REG_ADDR(DI_MEM_LUMA_Y0) 	///../ucode/register.h
#define DI_MEM_CHROMA_X0 0x17df 	///../ucode/register.h
#define P_DI_MEM_CHROMA_X0 		CBUS_REG_ADDR(DI_MEM_CHROMA_X0) 	///../ucode/register.h
#define DI_MEM_CHROMA_Y0 0x17e0 	///../ucode/register.h
#define P_DI_MEM_CHROMA_Y0 		CBUS_REG_ADDR(DI_MEM_CHROMA_Y0) 	///../ucode/register.h
#define DI_MEM_RPT_LOOP 0x17e1 	///../ucode/register.h
#define P_DI_MEM_RPT_LOOP 		CBUS_REG_ADDR(DI_MEM_RPT_LOOP) 	///../ucode/register.h
#define DI_MEM_LUMA0_RPT_PAT 0x17e2 	///../ucode/register.h
#define P_DI_MEM_LUMA0_RPT_PAT 		CBUS_REG_ADDR(DI_MEM_LUMA0_RPT_PAT) 	///../ucode/register.h
#define DI_MEM_CHROMA0_RPT_PAT 0x17e3 	///../ucode/register.h
#define P_DI_MEM_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(DI_MEM_CHROMA0_RPT_PAT) 	///../ucode/register.h
#define DI_MEM_DUMMY_PIXEL 0x17e4 	///../ucode/register.h
#define P_DI_MEM_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_MEM_DUMMY_PIXEL) 	///../ucode/register.h
#define DI_MEM_LUMA_FIFO_SIZE 0x17e5 	///../ucode/register.h
#define P_DI_MEM_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(DI_MEM_LUMA_FIFO_SIZE) 	///../ucode/register.h
#define DI_MEM_RANGE_MAP_Y 0x17bd 	///../ucode/register.h
#define P_DI_MEM_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_MEM_RANGE_MAP_Y) 	///../ucode/register.h
#define DI_MEM_RANGE_MAP_CB 0x17be 	///../ucode/register.h
#define P_DI_MEM_RANGE_MAP_CB 		CBUS_REG_ADDR(DI_MEM_RANGE_MAP_CB) 	///../ucode/register.h
#define DI_MEM_RANGE_MAP_CR 0x17bf 	///../ucode/register.h
#define P_DI_MEM_RANGE_MAP_CR 		CBUS_REG_ADDR(DI_MEM_RANGE_MAP_CR) 	///../ucode/register.h
#define DI_MEM_GEN_REG2 0x1792 	///../ucode/register.h
#define P_DI_MEM_GEN_REG2 		CBUS_REG_ADDR(DI_MEM_GEN_REG2) 	///../ucode/register.h
#define DI_MEM_FMT_CTRL 0x17e6 	///../ucode/register.h
#define P_DI_MEM_FMT_CTRL 		CBUS_REG_ADDR(DI_MEM_FMT_CTRL) 	///../ucode/register.h
#define DI_MEM_FMT_W 0x17e7 	///../ucode/register.h
#define P_DI_MEM_FMT_W 		CBUS_REG_ADDR(DI_MEM_FMT_W) 	///../ucode/register.h
#define DI_IF1_GEN_REG 0x17e8 	///../ucode/register.h
#define P_DI_IF1_GEN_REG 		CBUS_REG_ADDR(DI_IF1_GEN_REG) 	///../ucode/register.h
#define DI_IF1_CANVAS0 0x17e9 	///../ucode/register.h
#define P_DI_IF1_CANVAS0 		CBUS_REG_ADDR(DI_IF1_CANVAS0) 	///../ucode/register.h
#define DI_IF1_LUMA_X0 0x17ea 	///../ucode/register.h
#define P_DI_IF1_LUMA_X0 		CBUS_REG_ADDR(DI_IF1_LUMA_X0) 	///../ucode/register.h
#define DI_IF1_LUMA_Y0 0x17eb 	///../ucode/register.h
#define P_DI_IF1_LUMA_Y0 		CBUS_REG_ADDR(DI_IF1_LUMA_Y0) 	///../ucode/register.h
#define DI_IF1_CHROMA_X0 0x17ec 	///../ucode/register.h
#define P_DI_IF1_CHROMA_X0 		CBUS_REG_ADDR(DI_IF1_CHROMA_X0) 	///../ucode/register.h
#define DI_IF1_CHROMA_Y0 0x17ed 	///../ucode/register.h
#define P_DI_IF1_CHROMA_Y0 		CBUS_REG_ADDR(DI_IF1_CHROMA_Y0) 	///../ucode/register.h
#define DI_IF1_RPT_LOOP 0x17ee 	///../ucode/register.h
#define P_DI_IF1_RPT_LOOP 		CBUS_REG_ADDR(DI_IF1_RPT_LOOP) 	///../ucode/register.h
#define DI_IF1_LUMA0_RPT_PAT 0x17ef 	///../ucode/register.h
#define P_DI_IF1_LUMA0_RPT_PAT 		CBUS_REG_ADDR(DI_IF1_LUMA0_RPT_PAT) 	///../ucode/register.h
#define DI_IF1_CHROMA0_RPT_PAT 0x17f0 	///../ucode/register.h
#define P_DI_IF1_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(DI_IF1_CHROMA0_RPT_PAT) 	///../ucode/register.h
#define DI_IF1_DUMMY_PIXEL 0x17f1 	///../ucode/register.h
#define P_DI_IF1_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_IF1_DUMMY_PIXEL) 	///../ucode/register.h
#define DI_IF1_LUMA_FIFO_SIZE 0x17f2 	///../ucode/register.h
#define P_DI_IF1_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(DI_IF1_LUMA_FIFO_SIZE) 	///../ucode/register.h
#define DI_IF1_RANGE_MAP_Y 0x17fc 	///../ucode/register.h
#define P_DI_IF1_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_IF1_RANGE_MAP_Y) 	///../ucode/register.h
#define DI_IF1_RANGE_MAP_CB 0x17fd 	///../ucode/register.h
#define P_DI_IF1_RANGE_MAP_CB 		CBUS_REG_ADDR(DI_IF1_RANGE_MAP_CB) 	///../ucode/register.h
#define DI_IF1_RANGE_MAP_CR 0x17fe 	///../ucode/register.h
#define P_DI_IF1_RANGE_MAP_CR 		CBUS_REG_ADDR(DI_IF1_RANGE_MAP_CR) 	///../ucode/register.h
#define DI_IF1_GEN_REG2 0x1790 	///../ucode/register.h
#define P_DI_IF1_GEN_REG2 		CBUS_REG_ADDR(DI_IF1_GEN_REG2) 	///../ucode/register.h
#define DI_IF1_FMT_CTRL 0x17f3 	///../ucode/register.h
#define P_DI_IF1_FMT_CTRL 		CBUS_REG_ADDR(DI_IF1_FMT_CTRL) 	///../ucode/register.h
#define DI_IF1_FMT_W 0x17f4 	///../ucode/register.h
#define P_DI_IF1_FMT_W 		CBUS_REG_ADDR(DI_IF1_FMT_W) 	///../ucode/register.h
#define DI_CHAN2_GEN_REG 0x17f5 	///../ucode/register.h
#define P_DI_CHAN2_GEN_REG 		CBUS_REG_ADDR(DI_CHAN2_GEN_REG) 	///../ucode/register.h
#define DI_CHAN2_CANVAS 0x17f6 	///../ucode/register.h
#define P_DI_CHAN2_CANVAS 		CBUS_REG_ADDR(DI_CHAN2_CANVAS) 	///../ucode/register.h
#define DI_CHAN2_LUMA_X 0x17f7 	///../ucode/register.h
#define P_DI_CHAN2_LUMA_X 		CBUS_REG_ADDR(DI_CHAN2_LUMA_X) 	///../ucode/register.h
#define DI_CHAN2_LUMA_Y 0x17f8 	///../ucode/register.h
#define P_DI_CHAN2_LUMA_Y 		CBUS_REG_ADDR(DI_CHAN2_LUMA_Y) 	///../ucode/register.h
#define DI_CHAN2_RPT_LOOP 0x17f9 	///../ucode/register.h
#define P_DI_CHAN2_RPT_LOOP 		CBUS_REG_ADDR(DI_CHAN2_RPT_LOOP) 	///../ucode/register.h
#define DI_CHAN2_LUMA_RPT_PAT 0x17fa 	///../ucode/register.h
#define P_DI_CHAN2_LUMA_RPT_PAT 		CBUS_REG_ADDR(DI_CHAN2_LUMA_RPT_PAT) 	///../ucode/register.h
#define DI_CHAN2_DUMMY_PIXEL 0x17fb 	///../ucode/register.h
#define P_DI_CHAN2_DUMMY_PIXEL 		CBUS_REG_ADDR(DI_CHAN2_DUMMY_PIXEL) 	///../ucode/register.h
#define DI_CHAN2_RANGE_MAP_Y 0x17b9 	///../ucode/register.h
#define P_DI_CHAN2_RANGE_MAP_Y 		CBUS_REG_ADDR(DI_CHAN2_RANGE_MAP_Y) 	///../ucode/register.h
#define VIU2_ADDR_START 0x1e00 	///../ucode/register.h
#define P_VIU2_ADDR_START 		CBUS_REG_ADDR(VIU2_ADDR_START) 	///../ucode/register.h
#define VIU2_ADDR_END 0x1eff 	///../ucode/register.h
#define P_VIU2_ADDR_END 		CBUS_REG_ADDR(VIU2_ADDR_END) 	///../ucode/register.h
#define VIU2_OSD1_CTRL_STAT 0x1e10 	///../ucode/register.h
#define P_VIU2_OSD1_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT) 	///../ucode/register.h
#define VIU2_OSD1_CTRL_STAT2 0x1e2d 	///../ucode/register.h
#define P_VIU2_OSD1_CTRL_STAT2 		CBUS_REG_ADDR(VIU2_OSD1_CTRL_STAT2) 	///../ucode/register.h
#define VIU2_OSD1_COLOR_ADDR 0x1e11 	///../ucode/register.h
#define P_VIU2_OSD1_COLOR_ADDR 		CBUS_REG_ADDR(VIU2_OSD1_COLOR_ADDR) 	///../ucode/register.h
#define VIU2_OSD1_COLOR 0x1e12 	///../ucode/register.h
#define P_VIU2_OSD1_COLOR 		CBUS_REG_ADDR(VIU2_OSD1_COLOR) 	///../ucode/register.h
#define VIU2_OSD1_TCOLOR_AG0 0x1e17 	///../ucode/register.h
#define P_VIU2_OSD1_TCOLOR_AG0 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG0) 	///../ucode/register.h
#define VIU2_OSD1_TCOLOR_AG1 0x1e18 	///../ucode/register.h
#define P_VIU2_OSD1_TCOLOR_AG1 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG1) 	///../ucode/register.h
#define VIU2_OSD1_TCOLOR_AG2 0x1e19 	///../ucode/register.h
#define P_VIU2_OSD1_TCOLOR_AG2 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG2) 	///../ucode/register.h
#define VIU2_OSD1_TCOLOR_AG3 0x1e1a 	///../ucode/register.h
#define P_VIU2_OSD1_TCOLOR_AG3 		CBUS_REG_ADDR(VIU2_OSD1_TCOLOR_AG3) 	///../ucode/register.h
#define VIU2_OSD1_BLK0_CFG_W0 0x1e1b 	///../ucode/register.h
#define P_VIU2_OSD1_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD1_BLK1_CFG_W0 0x1e1f 	///../ucode/register.h
#define P_VIU2_OSD1_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD1_BLK2_CFG_W0 0x1e23 	///../ucode/register.h
#define P_VIU2_OSD1_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD1_BLK3_CFG_W0 0x1e27 	///../ucode/register.h
#define P_VIU2_OSD1_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD1_BLK0_CFG_W1 0x1e1c 	///../ucode/register.h
#define P_VIU2_OSD1_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD1_BLK1_CFG_W1 0x1e20 	///../ucode/register.h
#define P_VIU2_OSD1_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD1_BLK2_CFG_W1 0x1e24 	///../ucode/register.h
#define P_VIU2_OSD1_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD1_BLK3_CFG_W1 0x1e28 	///../ucode/register.h
#define P_VIU2_OSD1_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD1_BLK0_CFG_W2 0x1e1d 	///../ucode/register.h
#define P_VIU2_OSD1_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD1_BLK1_CFG_W2 0x1e21 	///../ucode/register.h
#define P_VIU2_OSD1_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD1_BLK2_CFG_W2 0x1e25 	///../ucode/register.h
#define P_VIU2_OSD1_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD1_BLK3_CFG_W2 0x1e29 	///../ucode/register.h
#define P_VIU2_OSD1_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD1_BLK0_CFG_W3 0x1e1e 	///../ucode/register.h
#define P_VIU2_OSD1_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD1_BLK1_CFG_W3 0x1e22 	///../ucode/register.h
#define P_VIU2_OSD1_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD1_BLK2_CFG_W3 0x1e26 	///../ucode/register.h
#define P_VIU2_OSD1_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD1_BLK3_CFG_W3 0x1e2a 	///../ucode/register.h
#define P_VIU2_OSD1_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD1_BLK0_CFG_W4 0x1e13 	///../ucode/register.h
#define P_VIU2_OSD1_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK0_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD1_BLK1_CFG_W4 0x1e14 	///../ucode/register.h
#define P_VIU2_OSD1_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK1_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD1_BLK2_CFG_W4 0x1e15 	///../ucode/register.h
#define P_VIU2_OSD1_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK2_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD1_BLK3_CFG_W4 0x1e16 	///../ucode/register.h
#define P_VIU2_OSD1_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD1_BLK3_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD1_FIFO_CTRL_STAT 0x1e2b 	///../ucode/register.h
#define P_VIU2_OSD1_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD1_FIFO_CTRL_STAT) 	///../ucode/register.h
#define VIU2_OSD1_TEST_RDDATA 0x1e2c 	///../ucode/register.h
#define P_VIU2_OSD1_TEST_RDDATA 		CBUS_REG_ADDR(VIU2_OSD1_TEST_RDDATA) 	///../ucode/register.h
#define VIU2_OSD2_CTRL_STAT 0x1e30 	///../ucode/register.h
#define P_VIU2_OSD2_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD2_CTRL_STAT) 	///../ucode/register.h
#define VIU2_OSD2_CTRL_STAT2 0x1e4d 	///../ucode/register.h
#define P_VIU2_OSD2_CTRL_STAT2 		CBUS_REG_ADDR(VIU2_OSD2_CTRL_STAT2) 	///../ucode/register.h
#define VIU2_OSD2_COLOR_ADDR 0x1e31 	///../ucode/register.h
#define P_VIU2_OSD2_COLOR_ADDR 		CBUS_REG_ADDR(VIU2_OSD2_COLOR_ADDR) 	///../ucode/register.h
#define VIU2_OSD2_COLOR 0x1e32 	///../ucode/register.h
#define P_VIU2_OSD2_COLOR 		CBUS_REG_ADDR(VIU2_OSD2_COLOR) 	///../ucode/register.h
#define VIU2_OSD2_HL1_H_START_END 0x1e33 	///../ucode/register.h
#define P_VIU2_OSD2_HL1_H_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL1_H_START_END) 	///../ucode/register.h
#define VIU2_OSD2_HL1_V_START_END 0x1e34 	///../ucode/register.h
#define P_VIU2_OSD2_HL1_V_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL1_V_START_END) 	///../ucode/register.h
#define VIU2_OSD2_HL2_H_START_END 0x1e35 	///../ucode/register.h
#define P_VIU2_OSD2_HL2_H_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL2_H_START_END) 	///../ucode/register.h
#define VIU2_OSD2_HL2_V_START_END 0x1e36 	///../ucode/register.h
#define P_VIU2_OSD2_HL2_V_START_END 		CBUS_REG_ADDR(VIU2_OSD2_HL2_V_START_END) 	///../ucode/register.h
#define VIU2_OSD2_TCOLOR_AG0 0x1e37 	///../ucode/register.h
#define P_VIU2_OSD2_TCOLOR_AG0 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG0) 	///../ucode/register.h
#define VIU2_OSD2_TCOLOR_AG1 0x1e38 	///../ucode/register.h
#define P_VIU2_OSD2_TCOLOR_AG1 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG1) 	///../ucode/register.h
#define VIU2_OSD2_TCOLOR_AG2 0x1e39 	///../ucode/register.h
#define P_VIU2_OSD2_TCOLOR_AG2 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG2) 	///../ucode/register.h
#define VIU2_OSD2_TCOLOR_AG3 0x1e3a 	///../ucode/register.h
#define P_VIU2_OSD2_TCOLOR_AG3 		CBUS_REG_ADDR(VIU2_OSD2_TCOLOR_AG3) 	///../ucode/register.h
#define VIU2_OSD2_BLK0_CFG_W0 0x1e3b 	///../ucode/register.h
#define P_VIU2_OSD2_BLK0_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD2_BLK1_CFG_W0 0x1e3f 	///../ucode/register.h
#define P_VIU2_OSD2_BLK1_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD2_BLK2_CFG_W0 0x1e43 	///../ucode/register.h
#define P_VIU2_OSD2_BLK2_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD2_BLK3_CFG_W0 0x1e47 	///../ucode/register.h
#define P_VIU2_OSD2_BLK3_CFG_W0 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W0) 	///../ucode/register.h
#define VIU2_OSD2_BLK0_CFG_W1 0x1e3c 	///../ucode/register.h
#define P_VIU2_OSD2_BLK0_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD2_BLK1_CFG_W1 0x1e40 	///../ucode/register.h
#define P_VIU2_OSD2_BLK1_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD2_BLK2_CFG_W1 0x1e44 	///../ucode/register.h
#define P_VIU2_OSD2_BLK2_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD2_BLK3_CFG_W1 0x1e48 	///../ucode/register.h
#define P_VIU2_OSD2_BLK3_CFG_W1 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W1) 	///../ucode/register.h
#define VIU2_OSD2_BLK0_CFG_W2 0x1e3d 	///../ucode/register.h
#define P_VIU2_OSD2_BLK0_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD2_BLK1_CFG_W2 0x1e41 	///../ucode/register.h
#define P_VIU2_OSD2_BLK1_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD2_BLK2_CFG_W2 0x1e45 	///../ucode/register.h
#define P_VIU2_OSD2_BLK2_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD2_BLK3_CFG_W2 0x1e49 	///../ucode/register.h
#define P_VIU2_OSD2_BLK3_CFG_W2 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W2) 	///../ucode/register.h
#define VIU2_OSD2_BLK0_CFG_W3 0x1e3e 	///../ucode/register.h
#define P_VIU2_OSD2_BLK0_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD2_BLK1_CFG_W3 0x1e42 	///../ucode/register.h
#define P_VIU2_OSD2_BLK1_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD2_BLK2_CFG_W3 0x1e46 	///../ucode/register.h
#define P_VIU2_OSD2_BLK2_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD2_BLK3_CFG_W3 0x1e4a 	///../ucode/register.h
#define P_VIU2_OSD2_BLK3_CFG_W3 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W3) 	///../ucode/register.h
#define VIU2_OSD2_BLK0_CFG_W4 0x1e64 	///../ucode/register.h
#define P_VIU2_OSD2_BLK0_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK0_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD2_BLK1_CFG_W4 0x1e65 	///../ucode/register.h
#define P_VIU2_OSD2_BLK1_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK1_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD2_BLK2_CFG_W4 0x1e66 	///../ucode/register.h
#define P_VIU2_OSD2_BLK2_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK2_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD2_BLK3_CFG_W4 0x1e67 	///../ucode/register.h
#define P_VIU2_OSD2_BLK3_CFG_W4 		CBUS_REG_ADDR(VIU2_OSD2_BLK3_CFG_W4) 	///../ucode/register.h
#define VIU2_OSD2_FIFO_CTRL_STAT 0x1e4b 	///../ucode/register.h
#define P_VIU2_OSD2_FIFO_CTRL_STAT 		CBUS_REG_ADDR(VIU2_OSD2_FIFO_CTRL_STAT) 	///../ucode/register.h
#define VIU2_OSD2_TEST_RDDATA 0x1e4c 	///../ucode/register.h
#define P_VIU2_OSD2_TEST_RDDATA 		CBUS_REG_ADDR(VIU2_OSD2_TEST_RDDATA) 	///../ucode/register.h
#define VIU2_VD1_IF0_GEN_REG 0x1e50 	///../ucode/register.h
#define P_VIU2_VD1_IF0_GEN_REG 		CBUS_REG_ADDR(VIU2_VD1_IF0_GEN_REG) 	///../ucode/register.h
#define VIU2_VD1_IF0_CANVAS0 0x1e51 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CANVAS0 		CBUS_REG_ADDR(VIU2_VD1_IF0_CANVAS0) 	///../ucode/register.h
#define VIU2_VD1_IF0_CANVAS1 0x1e52 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CANVAS1 		CBUS_REG_ADDR(VIU2_VD1_IF0_CANVAS1) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA_X0 0x1e53 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA_X0 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_X0) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA_Y0 0x1e54 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA_Y0 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_Y0) 	///../ucode/register.h
#define VIU2_VD1_IF0_CHROMA_X0 0x1e55 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CHROMA_X0 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_X0) 	///../ucode/register.h
#define VIU2_VD1_IF0_CHROMA_Y0 0x1e56 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CHROMA_Y0 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y0) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA_X1 0x1e57 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA_X1 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_X1) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA_Y1 0x1e58 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA_Y1 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_Y1) 	///../ucode/register.h
#define VIU2_VD1_IF0_CHROMA_X1 0x1e59 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CHROMA_X1 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_X1) 	///../ucode/register.h
#define VIU2_VD1_IF0_CHROMA_Y1 0x1e5a 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CHROMA_Y1 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_Y1) 	///../ucode/register.h
#define VIU2_VD1_IF0_RPT_LOOP 0x1e5b 	///../ucode/register.h
#define P_VIU2_VD1_IF0_RPT_LOOP 		CBUS_REG_ADDR(VIU2_VD1_IF0_RPT_LOOP) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA0_RPT_PAT 0x1e5c 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA0_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA0_RPT_PAT) 	///../ucode/register.h
#define VIU2_VD1_IF0_CHROMA0_RPT_PAT 0x1e5d 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CHROMA0_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA0_RPT_PAT) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA1_RPT_PAT 0x1e5e 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA1_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA1_RPT_PAT) 	///../ucode/register.h
#define VIU2_VD1_IF0_CHROMA1_RPT_PAT 0x1e5f 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CHROMA1_RPT_PAT 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA1_RPT_PAT) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA_PSEL 0x1e60 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA_PSEL 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_PSEL) 	///../ucode/register.h
#define VIU2_VD1_IF0_CHROMA_PSEL 0x1e61 	///../ucode/register.h
#define P_VIU2_VD1_IF0_CHROMA_PSEL 		CBUS_REG_ADDR(VIU2_VD1_IF0_CHROMA_PSEL) 	///../ucode/register.h
#define VIU2_VD1_IF0_DUMMY_PIXEL 0x1e62 	///../ucode/register.h
#define P_VIU2_VD1_IF0_DUMMY_PIXEL 		CBUS_REG_ADDR(VIU2_VD1_IF0_DUMMY_PIXEL) 	///../ucode/register.h
#define VIU2_VD1_IF0_LUMA_FIFO_SIZE 0x1e63 	///../ucode/register.h
#define P_VIU2_VD1_IF0_LUMA_FIFO_SIZE 		CBUS_REG_ADDR(VIU2_VD1_IF0_LUMA_FIFO_SIZE) 	///../ucode/register.h
#define VIU2_VD1_IF0_RANGE_MAP_Y 0x1e6a 	///../ucode/register.h
#define P_VIU2_VD1_IF0_RANGE_MAP_Y 		CBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_Y) 	///../ucode/register.h
#define VIU2_VD1_IF0_RANGE_MAP_CB 0x1e6b 	///../ucode/register.h
#define P_VIU2_VD1_IF0_RANGE_MAP_CB 		CBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CB) 	///../ucode/register.h
#define VIU2_VD1_IF0_RANGE_MAP_CR 0x1e6c 	///../ucode/register.h
#define P_VIU2_VD1_IF0_RANGE_MAP_CR 		CBUS_REG_ADDR(VIU2_VD1_IF0_RANGE_MAP_CR) 	///../ucode/register.h
#define VIU2_VD1_IF0_GEN_REG2 0x1e6d 	///../ucode/register.h
#define P_VIU2_VD1_IF0_GEN_REG2 		CBUS_REG_ADDR(VIU2_VD1_IF0_GEN_REG2) 	///../ucode/register.h
#define VIU2_VD1_FMT_CTRL 0x1e68 	///../ucode/register.h
#define P_VIU2_VD1_FMT_CTRL 		CBUS_REG_ADDR(VIU2_VD1_FMT_CTRL) 	///../ucode/register.h
#define VIU2_VD1_FMT_W 0x1e69 	///../ucode/register.h
#define P_VIU2_VD1_FMT_W 		CBUS_REG_ADDR(VIU2_VD1_FMT_W) 	///../ucode/register.h
#define ENCP_VFIFO2VD_CTL 0x1b58 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCP_VFIFO2VD_CTL) 	///../ucode/register.h
#define ENCP_VFIFO2VD_PIXEL_START 0x1b59 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCP_VFIFO2VD_PIXEL_START) 	///../ucode/register.h
#define ENCP_VFIFO2VD_PIXEL_END 0x1b5a 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCP_VFIFO2VD_PIXEL_END) 	///../ucode/register.h
#define ENCP_VFIFO2VD_LINE_TOP_START 0x1b5b 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_START) 	///../ucode/register.h
#define ENCP_VFIFO2VD_LINE_TOP_END 0x1b5c 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_TOP_END) 	///../ucode/register.h
#define ENCP_VFIFO2VD_LINE_BOT_START 0x1b5d 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_START) 	///../ucode/register.h
#define ENCP_VFIFO2VD_LINE_BOT_END 0x1b5e 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCP_VFIFO2VD_LINE_BOT_END) 	///../ucode/register.h
#define VENC_SYNC_ROUTE 0x1b60 	///../ucode/register.h
#define P_VENC_SYNC_ROUTE 		CBUS_REG_ADDR(VENC_SYNC_ROUTE) 	///../ucode/register.h
#define VENC_VIDEO_EXSRC 0x1b61 	///../ucode/register.h
#define P_VENC_VIDEO_EXSRC 		CBUS_REG_ADDR(VENC_VIDEO_EXSRC) 	///../ucode/register.h
#define VENC_DVI_SETTING 0x1b62 	///../ucode/register.h
#define P_VENC_DVI_SETTING 		CBUS_REG_ADDR(VENC_DVI_SETTING) 	///../ucode/register.h
#define VENC_C656_CTRL 0x1b63 	///../ucode/register.h
#define P_VENC_C656_CTRL 		CBUS_REG_ADDR(VENC_C656_CTRL) 	///../ucode/register.h
#define VENC_UPSAMPLE_CTRL0 0x1b64 	///../ucode/register.h
#define P_VENC_UPSAMPLE_CTRL0 		CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL0) 	///../ucode/register.h
#define VENC_UPSAMPLE_CTRL1 0x1b65 	///../ucode/register.h
#define P_VENC_UPSAMPLE_CTRL1 		CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL1) 	///../ucode/register.h
#define VENC_UPSAMPLE_CTRL2 0x1b66 	///../ucode/register.h
#define P_VENC_UPSAMPLE_CTRL2 		CBUS_REG_ADDR(VENC_UPSAMPLE_CTRL2) 	///../ucode/register.h
#define TCON_INVERT_CTL 0x1b67 	///../ucode/register.h
#define P_TCON_INVERT_CTL 		CBUS_REG_ADDR(TCON_INVERT_CTL) 	///../ucode/register.h
#define VENC_VIDEO_PROG_MODE 0x1b68 	///../ucode/register.h
#define P_VENC_VIDEO_PROG_MODE 		CBUS_REG_ADDR(VENC_VIDEO_PROG_MODE) 	///../ucode/register.h
#define VENC_ENCI_LINE 0x1b69 	///../ucode/register.h
#define P_VENC_ENCI_LINE 		CBUS_REG_ADDR(VENC_ENCI_LINE) 	///../ucode/register.h
#define VENC_ENCI_PIXEL 0x1b6a 	///../ucode/register.h
#define P_VENC_ENCI_PIXEL 		CBUS_REG_ADDR(VENC_ENCI_PIXEL) 	///../ucode/register.h
#define VENC_ENCP_LINE 0x1b6b 	///../ucode/register.h
#define P_VENC_ENCP_LINE 		CBUS_REG_ADDR(VENC_ENCP_LINE) 	///../ucode/register.h
#define VENC_ENCP_PIXEL 0x1b6c 	///../ucode/register.h
#define P_VENC_ENCP_PIXEL 		CBUS_REG_ADDR(VENC_ENCP_PIXEL) 	///../ucode/register.h
#define VENC_STATA 0x1b6d 	///../ucode/register.h
#define P_VENC_STATA 		CBUS_REG_ADDR(VENC_STATA) 	///../ucode/register.h
#define VENC_INTCTRL 0x1b6e 	///../ucode/register.h
#define P_VENC_INTCTRL 		CBUS_REG_ADDR(VENC_INTCTRL) 	///../ucode/register.h
#define VENC_INTFLAG 0x1b6f 	///../ucode/register.h
#define P_VENC_INTFLAG 		CBUS_REG_ADDR(VENC_INTFLAG) 	///../ucode/register.h
#define VENC_VIDEO_TST_EN 0x1b70 	///../ucode/register.h
#define P_VENC_VIDEO_TST_EN 		CBUS_REG_ADDR(VENC_VIDEO_TST_EN) 	///../ucode/register.h
#define VENC_VIDEO_TST_MDSEL 0x1b71 	///../ucode/register.h
#define P_VENC_VIDEO_TST_MDSEL 		CBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL) 	///../ucode/register.h
#define VENC_VIDEO_TST_Y 0x1b72 	///../ucode/register.h
#define P_VENC_VIDEO_TST_Y 		CBUS_REG_ADDR(VENC_VIDEO_TST_Y) 	///../ucode/register.h
#define VENC_VIDEO_TST_CB 0x1b73 	///../ucode/register.h
#define P_VENC_VIDEO_TST_CB 		CBUS_REG_ADDR(VENC_VIDEO_TST_CB) 	///../ucode/register.h
#define VENC_VIDEO_TST_CR 0x1b74 	///../ucode/register.h
#define P_VENC_VIDEO_TST_CR 		CBUS_REG_ADDR(VENC_VIDEO_TST_CR) 	///../ucode/register.h
#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75 	///../ucode/register.h
#define P_VENC_VIDEO_TST_CLRBAR_STRT 		CBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT) 	///../ucode/register.h
#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76 	///../ucode/register.h
#define P_VENC_VIDEO_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH) 	///../ucode/register.h
#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77 	///../ucode/register.h
#define P_VENC_VIDEO_TST_VDCNT_STSET 		CBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET) 	///../ucode/register.h
#define VENC_VDAC_DACSEL0 0x1b78 	///../ucode/register.h
#define P_VENC_VDAC_DACSEL0 		CBUS_REG_ADDR(VENC_VDAC_DACSEL0) 	///../ucode/register.h
#define VENC_VDAC_DACSEL1 0x1b79 	///../ucode/register.h
#define P_VENC_VDAC_DACSEL1 		CBUS_REG_ADDR(VENC_VDAC_DACSEL1) 	///../ucode/register.h
#define VENC_VDAC_DACSEL2 0x1b7a 	///../ucode/register.h
#define P_VENC_VDAC_DACSEL2 		CBUS_REG_ADDR(VENC_VDAC_DACSEL2) 	///../ucode/register.h
#define VENC_VDAC_DACSEL3 0x1b7b 	///../ucode/register.h
#define P_VENC_VDAC_DACSEL3 		CBUS_REG_ADDR(VENC_VDAC_DACSEL3) 	///../ucode/register.h
#define VENC_VDAC_DACSEL4 0x1b7c 	///../ucode/register.h
#define P_VENC_VDAC_DACSEL4 		CBUS_REG_ADDR(VENC_VDAC_DACSEL4) 	///../ucode/register.h
#define VENC_VDAC_DACSEL5 0x1b7d 	///../ucode/register.h
#define P_VENC_VDAC_DACSEL5 		CBUS_REG_ADDR(VENC_VDAC_DACSEL5) 	///../ucode/register.h
#define VENC_VDAC_SETTING 0x1b7e 	///../ucode/register.h
#define P_VENC_VDAC_SETTING 		CBUS_REG_ADDR(VENC_VDAC_SETTING) 	///../ucode/register.h
#define VENC_VDAC_TST_VAL 0x1b7f 	///../ucode/register.h
#define P_VENC_VDAC_TST_VAL 		CBUS_REG_ADDR(VENC_VDAC_TST_VAL) 	///../ucode/register.h
#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0 	///../ucode/register.h
#define P_VENC_VDAC_DAC0_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC0_GAINCTRL) 	///../ucode/register.h
#define VENC_VDAC_DAC0_OFFSET 0x1bf1 	///../ucode/register.h
#define P_VENC_VDAC_DAC0_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC0_OFFSET) 	///../ucode/register.h
#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2 	///../ucode/register.h
#define P_VENC_VDAC_DAC1_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC1_GAINCTRL) 	///../ucode/register.h
#define VENC_VDAC_DAC1_OFFSET 0x1bf3 	///../ucode/register.h
#define P_VENC_VDAC_DAC1_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC1_OFFSET) 	///../ucode/register.h
#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4 	///../ucode/register.h
#define P_VENC_VDAC_DAC2_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC2_GAINCTRL) 	///../ucode/register.h
#define VENC_VDAC_DAC2_OFFSET 0x1bf5 	///../ucode/register.h
#define P_VENC_VDAC_DAC2_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC2_OFFSET) 	///../ucode/register.h
#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6 	///../ucode/register.h
#define P_VENC_VDAC_DAC3_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC3_GAINCTRL) 	///../ucode/register.h
#define VENC_VDAC_DAC3_OFFSET 0x1bf7 	///../ucode/register.h
#define P_VENC_VDAC_DAC3_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC3_OFFSET) 	///../ucode/register.h
#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8 	///../ucode/register.h
#define P_VENC_VDAC_DAC4_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC4_GAINCTRL) 	///../ucode/register.h
#define VENC_VDAC_DAC4_OFFSET 0x1bf9 	///../ucode/register.h
#define P_VENC_VDAC_DAC4_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC4_OFFSET) 	///../ucode/register.h
#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa 	///../ucode/register.h
#define P_VENC_VDAC_DAC5_GAINCTRL 		CBUS_REG_ADDR(VENC_VDAC_DAC5_GAINCTRL) 	///../ucode/register.h
#define VENC_VDAC_DAC5_OFFSET 0x1bfb 	///../ucode/register.h
#define P_VENC_VDAC_DAC5_OFFSET 		CBUS_REG_ADDR(VENC_VDAC_DAC5_OFFSET) 	///../ucode/register.h
#define VENC_VDAC_FIFO_CTRL 0x1bfc 	///../ucode/register.h
#define P_VENC_VDAC_FIFO_CTRL 		CBUS_REG_ADDR(VENC_VDAC_FIFO_CTRL) 	///../ucode/register.h
#define ENCL_TCON_INVERT_CTL 0x1bfd 	///../ucode/register.h
#define P_ENCL_TCON_INVERT_CTL 		CBUS_REG_ADDR(ENCL_TCON_INVERT_CTL) 	///../ucode/register.h
#define ENCP_VIDEO_EN 0x1b80 	///../ucode/register.h
#define P_ENCP_VIDEO_EN 		CBUS_REG_ADDR(ENCP_VIDEO_EN) 	///../ucode/register.h
#define ENCP_VIDEO_SYNC_MODE 0x1b81 	///../ucode/register.h
#define P_ENCP_VIDEO_SYNC_MODE 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE) 	///../ucode/register.h
#define ENCP_MACV_EN 0x1b82 	///../ucode/register.h
#define P_ENCP_MACV_EN 		CBUS_REG_ADDR(ENCP_MACV_EN) 	///../ucode/register.h
#define ENCP_VIDEO_Y_SCL 0x1b83 	///../ucode/register.h
#define P_ENCP_VIDEO_Y_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_Y_SCL) 	///../ucode/register.h
#define ENCP_VIDEO_PB_SCL 0x1b84 	///../ucode/register.h
#define P_ENCP_VIDEO_PB_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_PB_SCL) 	///../ucode/register.h
#define ENCP_VIDEO_PR_SCL 0x1b85 	///../ucode/register.h
#define P_ENCP_VIDEO_PR_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_PR_SCL) 	///../ucode/register.h
#define ENCP_VIDEO_SYNC_SCL 0x1b86 	///../ucode/register.h
#define P_ENCP_VIDEO_SYNC_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL) 	///../ucode/register.h
#define ENCP_VIDEO_MACV_SCL 0x1b87 	///../ucode/register.h
#define P_ENCP_VIDEO_MACV_SCL 		CBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL) 	///../ucode/register.h
#define ENCP_VIDEO_Y_OFFST 0x1b88 	///../ucode/register.h
#define P_ENCP_VIDEO_Y_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST) 	///../ucode/register.h
#define ENCP_VIDEO_PB_OFFST 0x1b89 	///../ucode/register.h
#define P_ENCP_VIDEO_PB_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST) 	///../ucode/register.h
#define ENCP_VIDEO_PR_OFFST 0x1b8a 	///../ucode/register.h
#define P_ENCP_VIDEO_PR_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST) 	///../ucode/register.h
#define ENCP_VIDEO_SYNC_OFFST 0x1b8b 	///../ucode/register.h
#define P_ENCP_VIDEO_SYNC_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST) 	///../ucode/register.h
#define ENCP_VIDEO_MACV_OFFST 0x1b8c 	///../ucode/register.h
#define P_ENCP_VIDEO_MACV_OFFST 		CBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST) 	///../ucode/register.h
#define ENCP_VIDEO_MODE 0x1b8d 	///../ucode/register.h
#define P_ENCP_VIDEO_MODE 		CBUS_REG_ADDR(ENCP_VIDEO_MODE) 	///../ucode/register.h
#define ENCP_VIDEO_MODE_ADV 0x1b8e 	///../ucode/register.h
#define P_ENCP_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV) 	///../ucode/register.h
#define ENCP_DBG_PX_RST 0x1b90 	///../ucode/register.h
#define P_ENCP_DBG_PX_RST 		CBUS_REG_ADDR(ENCP_DBG_PX_RST) 	///../ucode/register.h
#define ENCP_DBG_LN_RST 0x1b91 	///../ucode/register.h
#define P_ENCP_DBG_LN_RST 		CBUS_REG_ADDR(ENCP_DBG_LN_RST) 	///../ucode/register.h
#define ENCP_DBG_PX_INT 0x1b92 	///../ucode/register.h
#define P_ENCP_DBG_PX_INT 		CBUS_REG_ADDR(ENCP_DBG_PX_INT) 	///../ucode/register.h
#define ENCP_DBG_LN_INT 0x1b93 	///../ucode/register.h
#define P_ENCP_DBG_LN_INT 		CBUS_REG_ADDR(ENCP_DBG_LN_INT) 	///../ucode/register.h
#define ENCP_VIDEO_YFP1_HTIME 0x1b94 	///../ucode/register.h
#define P_ENCP_VIDEO_YFP1_HTIME 		CBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME) 	///../ucode/register.h
#define ENCP_VIDEO_YFP2_HTIME 0x1b95 	///../ucode/register.h
#define P_ENCP_VIDEO_YFP2_HTIME 		CBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME) 	///../ucode/register.h
#define ENCP_VIDEO_YC_DLY 0x1b96 	///../ucode/register.h
#define P_ENCP_VIDEO_YC_DLY 		CBUS_REG_ADDR(ENCP_VIDEO_YC_DLY) 	///../ucode/register.h
#define ENCP_VIDEO_MAX_PXCNT 0x1b97 	///../ucode/register.h
#define P_ENCP_VIDEO_MAX_PXCNT 		CBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT) 	///../ucode/register.h
#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 	///../ucode/register.h
#define P_ENCP_VIDEO_HSPULS_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN) 	///../ucode/register.h
#define ENCP_VIDEO_HSPULS_END 0x1b99 	///../ucode/register.h
#define P_ENCP_VIDEO_HSPULS_END 		CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END) 	///../ucode/register.h
#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a 	///../ucode/register.h
#define P_ENCP_VIDEO_HSPULS_SWITCH 		CBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH) 	///../ucode/register.h
#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b 	///../ucode/register.h
#define P_ENCP_VIDEO_VSPULS_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN) 	///../ucode/register.h
#define ENCP_VIDEO_VSPULS_END 0x1b9c 	///../ucode/register.h
#define P_ENCP_VIDEO_VSPULS_END 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END) 	///../ucode/register.h
#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d 	///../ucode/register.h
#define P_ENCP_VIDEO_VSPULS_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE) 	///../ucode/register.h
#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e 	///../ucode/register.h
#define P_ENCP_VIDEO_VSPULS_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE) 	///../ucode/register.h
#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f 	///../ucode/register.h
#define P_ENCP_VIDEO_EQPULS_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN) 	///../ucode/register.h
#define ENCP_VIDEO_EQPULS_END 0x1ba0 	///../ucode/register.h
#define P_ENCP_VIDEO_EQPULS_END 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END) 	///../ucode/register.h
#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 	///../ucode/register.h
#define P_ENCP_VIDEO_EQPULS_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE) 	///../ucode/register.h
#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 	///../ucode/register.h
#define P_ENCP_VIDEO_EQPULS_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE) 	///../ucode/register.h
#define ENCP_VIDEO_HAVON_END 0x1ba3 	///../ucode/register.h
#define P_ENCP_VIDEO_HAVON_END 		CBUS_REG_ADDR(ENCP_VIDEO_HAVON_END) 	///../ucode/register.h
#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 	///../ucode/register.h
#define P_ENCP_VIDEO_HAVON_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN) 	///../ucode/register.h
#define ENCP_VIDEO_VAVON_ELINE 0x1baf 	///../ucode/register.h
#define P_ENCP_VIDEO_VAVON_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE) 	///../ucode/register.h
#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 	///../ucode/register.h
#define P_ENCP_VIDEO_VAVON_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE) 	///../ucode/register.h
#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 	///../ucode/register.h
#define P_ENCP_VIDEO_HSO_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN) 	///../ucode/register.h
#define ENCP_VIDEO_HSO_END 0x1ba8 	///../ucode/register.h
#define P_ENCP_VIDEO_HSO_END 		CBUS_REG_ADDR(ENCP_VIDEO_HSO_END) 	///../ucode/register.h
#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 	///../ucode/register.h
#define P_ENCP_VIDEO_VSO_BEGIN 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN) 	///../ucode/register.h
#define ENCP_VIDEO_VSO_END 0x1baa 	///../ucode/register.h
#define P_ENCP_VIDEO_VSO_END 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_END) 	///../ucode/register.h
#define ENCP_VIDEO_VSO_BLINE 0x1bab 	///../ucode/register.h
#define P_ENCP_VIDEO_VSO_BLINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE) 	///../ucode/register.h
#define ENCP_VIDEO_VSO_ELINE 0x1bac 	///../ucode/register.h
#define P_ENCP_VIDEO_VSO_ELINE 		CBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE) 	///../ucode/register.h
#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad 	///../ucode/register.h
#define P_ENCP_VIDEO_SYNC_WAVE_CURVE 		CBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE) 	///../ucode/register.h
#define ENCP_VIDEO_MAX_LNCNT 0x1bae 	///../ucode/register.h
#define P_ENCP_VIDEO_MAX_LNCNT 		CBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT) 	///../ucode/register.h
#define ENCP_VIDEO_SY_VAL 0x1bb0 	///../ucode/register.h
#define P_ENCP_VIDEO_SY_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_SY_VAL) 	///../ucode/register.h
#define ENCP_VIDEO_SY2_VAL 0x1bb1 	///../ucode/register.h
#define P_ENCP_VIDEO_SY2_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL) 	///../ucode/register.h
#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 	///../ucode/register.h
#define P_ENCP_VIDEO_BLANKY_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL) 	///../ucode/register.h
#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 	///../ucode/register.h
#define P_ENCP_VIDEO_BLANKPB_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL) 	///../ucode/register.h
#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 	///../ucode/register.h
#define P_ENCP_VIDEO_BLANKPR_VAL 		CBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL) 	///../ucode/register.h
#define ENCP_VIDEO_HOFFST 0x1bb5 	///../ucode/register.h
#define P_ENCP_VIDEO_HOFFST 		CBUS_REG_ADDR(ENCP_VIDEO_HOFFST) 	///../ucode/register.h
#define ENCP_VIDEO_VOFFST 0x1bb6 	///../ucode/register.h
#define P_ENCP_VIDEO_VOFFST 		CBUS_REG_ADDR(ENCP_VIDEO_VOFFST) 	///../ucode/register.h
#define ENCP_VIDEO_RGB_CTRL 0x1bb7 	///../ucode/register.h
#define P_ENCP_VIDEO_RGB_CTRL 		CBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL) 	///../ucode/register.h
#define ENCP_VIDEO_FILT_CTRL 0x1bb8 	///../ucode/register.h
#define P_ENCP_VIDEO_FILT_CTRL 		CBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL) 	///../ucode/register.h
#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 	///../ucode/register.h
#define P_ENCP_VIDEO_OFLD_VPEQ_OFST 		CBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST) 	///../ucode/register.h
#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba 	///../ucode/register.h
#define P_ENCP_VIDEO_OFLD_VOAV_OFST 		CBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST) 	///../ucode/register.h
#define ENCP_VIDEO_MATRIX_CB 0x1bbb 	///../ucode/register.h
#define P_ENCP_VIDEO_MATRIX_CB 		CBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB) 	///../ucode/register.h
#define ENCP_VIDEO_MATRIX_CR 0x1bbc 	///../ucode/register.h
#define P_ENCP_VIDEO_MATRIX_CR 		CBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR) 	///../ucode/register.h
#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd 	///../ucode/register.h
#define P_ENCP_VIDEO_RGBIN_CTRL 		CBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL) 	///../ucode/register.h
#define ENCP_MACV_BLANKY_VAL 0x1bc0 	///../ucode/register.h
#define P_ENCP_MACV_BLANKY_VAL 		CBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL) 	///../ucode/register.h
#define ENCP_MACV_MAXY_VAL 0x1bc1 	///../ucode/register.h
#define P_ENCP_MACV_MAXY_VAL 		CBUS_REG_ADDR(ENCP_MACV_MAXY_VAL) 	///../ucode/register.h
#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 	///../ucode/register.h
#define P_ENCP_MACV_1ST_PSSYNC_STRT 		CBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT) 	///../ucode/register.h
#define ENCP_MACV_PSSYNC_STRT 0x1bc3 	///../ucode/register.h
#define P_ENCP_MACV_PSSYNC_STRT 		CBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT) 	///../ucode/register.h
#define ENCP_MACV_AGC_STRT 0x1bc4 	///../ucode/register.h
#define P_ENCP_MACV_AGC_STRT 		CBUS_REG_ADDR(ENCP_MACV_AGC_STRT) 	///../ucode/register.h
#define ENCP_MACV_AGC_END 0x1bc5 	///../ucode/register.h
#define P_ENCP_MACV_AGC_END 		CBUS_REG_ADDR(ENCP_MACV_AGC_END) 	///../ucode/register.h
#define ENCP_MACV_WAVE_END 0x1bc6 	///../ucode/register.h
#define P_ENCP_MACV_WAVE_END 		CBUS_REG_ADDR(ENCP_MACV_WAVE_END) 	///../ucode/register.h
#define ENCP_MACV_STRTLINE 0x1bc7 	///../ucode/register.h
#define P_ENCP_MACV_STRTLINE 		CBUS_REG_ADDR(ENCP_MACV_STRTLINE) 	///../ucode/register.h
#define ENCP_MACV_ENDLINE 0x1bc8 	///../ucode/register.h
#define P_ENCP_MACV_ENDLINE 		CBUS_REG_ADDR(ENCP_MACV_ENDLINE) 	///../ucode/register.h
#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 	///../ucode/register.h
#define P_ENCP_MACV_TS_CNT_MAX_L 		CBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L) 	///../ucode/register.h
#define ENCP_MACV_TS_CNT_MAX_H 0x1bca 	///../ucode/register.h
#define P_ENCP_MACV_TS_CNT_MAX_H 		CBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H) 	///../ucode/register.h
#define ENCP_MACV_TIME_DOWN 0x1bcb 	///../ucode/register.h
#define P_ENCP_MACV_TIME_DOWN 		CBUS_REG_ADDR(ENCP_MACV_TIME_DOWN) 	///../ucode/register.h
#define ENCP_MACV_TIME_LO 0x1bcc 	///../ucode/register.h
#define P_ENCP_MACV_TIME_LO 		CBUS_REG_ADDR(ENCP_MACV_TIME_LO) 	///../ucode/register.h
#define ENCP_MACV_TIME_UP 0x1bcd 	///../ucode/register.h
#define P_ENCP_MACV_TIME_UP 		CBUS_REG_ADDR(ENCP_MACV_TIME_UP) 	///../ucode/register.h
#define ENCP_MACV_TIME_RST 0x1bce 	///../ucode/register.h
#define P_ENCP_MACV_TIME_RST 		CBUS_REG_ADDR(ENCP_MACV_TIME_RST) 	///../ucode/register.h
#define ENCP_VBI_CTRL 0x1bd0 	///../ucode/register.h
#define P_ENCP_VBI_CTRL 		CBUS_REG_ADDR(ENCP_VBI_CTRL) 	///../ucode/register.h
#define ENCP_VBI_SETTING 0x1bd1 	///../ucode/register.h
#define P_ENCP_VBI_SETTING 		CBUS_REG_ADDR(ENCP_VBI_SETTING) 	///../ucode/register.h
#define ENCP_VBI_BEGIN 0x1bd2 	///../ucode/register.h
#define P_ENCP_VBI_BEGIN 		CBUS_REG_ADDR(ENCP_VBI_BEGIN) 	///../ucode/register.h
#define ENCP_VBI_WIDTH 0x1bd3 	///../ucode/register.h
#define P_ENCP_VBI_WIDTH 		CBUS_REG_ADDR(ENCP_VBI_WIDTH) 	///../ucode/register.h
#define ENCP_VBI_HVAL 0x1bd4 	///../ucode/register.h
#define P_ENCP_VBI_HVAL 		CBUS_REG_ADDR(ENCP_VBI_HVAL) 	///../ucode/register.h
#define ENCP_VBI_DATA0 0x1bd5 	///../ucode/register.h
#define P_ENCP_VBI_DATA0 		CBUS_REG_ADDR(ENCP_VBI_DATA0) 	///../ucode/register.h
#define ENCP_VBI_DATA1 0x1bd6 	///../ucode/register.h
#define P_ENCP_VBI_DATA1 		CBUS_REG_ADDR(ENCP_VBI_DATA1) 	///../ucode/register.h
#define C656_HS_ST 0x1be0 	///../ucode/register.h
#define P_C656_HS_ST 		CBUS_REG_ADDR(C656_HS_ST) 	///../ucode/register.h
#define C656_HS_ED 0x1be1 	///../ucode/register.h
#define P_C656_HS_ED 		CBUS_REG_ADDR(C656_HS_ED) 	///../ucode/register.h
#define C656_VS_LNST_E 0x1be2 	///../ucode/register.h
#define P_C656_VS_LNST_E 		CBUS_REG_ADDR(C656_VS_LNST_E) 	///../ucode/register.h
#define C656_VS_LNST_O 0x1be3 	///../ucode/register.h
#define P_C656_VS_LNST_O 		CBUS_REG_ADDR(C656_VS_LNST_O) 	///../ucode/register.h
#define C656_VS_LNED_E 0x1be4 	///../ucode/register.h
#define P_C656_VS_LNED_E 		CBUS_REG_ADDR(C656_VS_LNED_E) 	///../ucode/register.h
#define C656_VS_LNED_O 0x1be5 	///../ucode/register.h
#define P_C656_VS_LNED_O 		CBUS_REG_ADDR(C656_VS_LNED_O) 	///../ucode/register.h
#define C656_FS_LNST 0x1be6 	///../ucode/register.h
#define P_C656_FS_LNST 		CBUS_REG_ADDR(C656_FS_LNST) 	///../ucode/register.h
#define C656_FS_LNED 0x1be7 	///../ucode/register.h
#define P_C656_FS_LNED 		CBUS_REG_ADDR(C656_FS_LNED) 	///../ucode/register.h
#define ENCI_VIDEO_MODE 0x1b00 	///../ucode/register.h
#define P_ENCI_VIDEO_MODE 		CBUS_REG_ADDR(ENCI_VIDEO_MODE) 	///../ucode/register.h
#define ENCI_VIDEO_MODE_ADV 0x1b01 	///../ucode/register.h
#define P_ENCI_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV) 	///../ucode/register.h
#define ENCI_VIDEO_FSC_ADJ 0x1b02 	///../ucode/register.h
#define P_ENCI_VIDEO_FSC_ADJ 		CBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ) 	///../ucode/register.h
#define ENCI_VIDEO_BRIGHT 0x1b03 	///../ucode/register.h
#define P_ENCI_VIDEO_BRIGHT 		CBUS_REG_ADDR(ENCI_VIDEO_BRIGHT) 	///../ucode/register.h
#define ENCI_VIDEO_CONT 0x1b04 	///../ucode/register.h
#define P_ENCI_VIDEO_CONT 		CBUS_REG_ADDR(ENCI_VIDEO_CONT) 	///../ucode/register.h
#define ENCI_VIDEO_SAT 0x1b05 	///../ucode/register.h
#define P_ENCI_VIDEO_SAT 		CBUS_REG_ADDR(ENCI_VIDEO_SAT) 	///../ucode/register.h
#define ENCI_VIDEO_HUE 0x1b06 	///../ucode/register.h
#define P_ENCI_VIDEO_HUE 		CBUS_REG_ADDR(ENCI_VIDEO_HUE) 	///../ucode/register.h
#define ENCI_VIDEO_SCH 0x1b07 	///../ucode/register.h
#define P_ENCI_VIDEO_SCH 		CBUS_REG_ADDR(ENCI_VIDEO_SCH) 	///../ucode/register.h
#define ENCI_SYNC_MODE 0x1b08 	///../ucode/register.h
#define P_ENCI_SYNC_MODE 		CBUS_REG_ADDR(ENCI_SYNC_MODE) 	///../ucode/register.h
#define ENCI_SYNC_CTRL 0x1b09 	///../ucode/register.h
#define P_ENCI_SYNC_CTRL 		CBUS_REG_ADDR(ENCI_SYNC_CTRL) 	///../ucode/register.h
#define ENCI_SYNC_HSO_BEGIN 0x1b0a 	///../ucode/register.h
#define P_ENCI_SYNC_HSO_BEGIN 		CBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN) 	///../ucode/register.h
#define ENCI_SYNC_HSO_END 0x1b0b 	///../ucode/register.h
#define P_ENCI_SYNC_HSO_END 		CBUS_REG_ADDR(ENCI_SYNC_HSO_END) 	///../ucode/register.h
#define ENCI_SYNC_VSO_EVN 0x1b0c 	///../ucode/register.h
#define P_ENCI_SYNC_VSO_EVN 		CBUS_REG_ADDR(ENCI_SYNC_VSO_EVN) 	///../ucode/register.h
#define ENCI_SYNC_VSO_ODD 0x1b0d 	///../ucode/register.h
#define P_ENCI_SYNC_VSO_ODD 		CBUS_REG_ADDR(ENCI_SYNC_VSO_ODD) 	///../ucode/register.h
#define ENCI_SYNC_VSO_EVNLN 0x1b0e 	///../ucode/register.h
#define P_ENCI_SYNC_VSO_EVNLN 		CBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN) 	///../ucode/register.h
#define ENCI_SYNC_VSO_ODDLN 0x1b0f 	///../ucode/register.h
#define P_ENCI_SYNC_VSO_ODDLN 		CBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN) 	///../ucode/register.h
#define ENCI_SYNC_HOFFST 0x1b10 	///../ucode/register.h
#define P_ENCI_SYNC_HOFFST 		CBUS_REG_ADDR(ENCI_SYNC_HOFFST) 	///../ucode/register.h
#define ENCI_SYNC_VOFFST 0x1b11 	///../ucode/register.h
#define P_ENCI_SYNC_VOFFST 		CBUS_REG_ADDR(ENCI_SYNC_VOFFST) 	///../ucode/register.h
#define ENCI_SYNC_ADJ 0x1b12 	///../ucode/register.h
#define P_ENCI_SYNC_ADJ 		CBUS_REG_ADDR(ENCI_SYNC_ADJ) 	///../ucode/register.h
#define ENCI_RGB_SETTING 0x1b13 	///../ucode/register.h
#define P_ENCI_RGB_SETTING 		CBUS_REG_ADDR(ENCI_RGB_SETTING) 	///../ucode/register.h
#define ENCI_DE_H_BEGIN 0x1b16 	///../ucode/register.h
#define P_ENCI_DE_H_BEGIN 		CBUS_REG_ADDR(ENCI_DE_H_BEGIN) 	///../ucode/register.h
#define ENCI_DE_H_END 0x1b17 	///../ucode/register.h
#define P_ENCI_DE_H_END 		CBUS_REG_ADDR(ENCI_DE_H_END) 	///../ucode/register.h
#define ENCI_DE_V_BEGIN_EVEN 0x1b18 	///../ucode/register.h
#define P_ENCI_DE_V_BEGIN_EVEN 		CBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN) 	///../ucode/register.h
#define ENCI_DE_V_END_EVEN 0x1b19 	///../ucode/register.h
#define P_ENCI_DE_V_END_EVEN 		CBUS_REG_ADDR(ENCI_DE_V_END_EVEN) 	///../ucode/register.h
#define ENCI_DE_V_BEGIN_ODD 0x1b1a 	///../ucode/register.h
#define P_ENCI_DE_V_BEGIN_ODD 		CBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD) 	///../ucode/register.h
#define ENCI_DE_V_END_ODD 0x1b1b 	///../ucode/register.h
#define P_ENCI_DE_V_END_ODD 		CBUS_REG_ADDR(ENCI_DE_V_END_ODD) 	///../ucode/register.h
#define ENCI_VBI_SETTING 0x1b20 	///../ucode/register.h
#define P_ENCI_VBI_SETTING 		CBUS_REG_ADDR(ENCI_VBI_SETTING) 	///../ucode/register.h
#define ENCI_VBI_CCDT_EVN 0x1b21 	///../ucode/register.h
#define P_ENCI_VBI_CCDT_EVN 		CBUS_REG_ADDR(ENCI_VBI_CCDT_EVN) 	///../ucode/register.h
#define ENCI_VBI_CCDT_ODD 0x1b22 	///../ucode/register.h
#define P_ENCI_VBI_CCDT_ODD 		CBUS_REG_ADDR(ENCI_VBI_CCDT_ODD) 	///../ucode/register.h
#define ENCI_VBI_CC525_LN 0x1b23 	///../ucode/register.h
#define P_ENCI_VBI_CC525_LN 		CBUS_REG_ADDR(ENCI_VBI_CC525_LN) 	///../ucode/register.h
#define ENCI_VBI_CC625_LN 0x1b24 	///../ucode/register.h
#define P_ENCI_VBI_CC625_LN 		CBUS_REG_ADDR(ENCI_VBI_CC625_LN) 	///../ucode/register.h
#define ENCI_VBI_WSSDT 0x1b25 	///../ucode/register.h
#define P_ENCI_VBI_WSSDT 		CBUS_REG_ADDR(ENCI_VBI_WSSDT) 	///../ucode/register.h
#define ENCI_VBI_WSS_LN 0x1b26 	///../ucode/register.h
#define P_ENCI_VBI_WSS_LN 		CBUS_REG_ADDR(ENCI_VBI_WSS_LN) 	///../ucode/register.h
#define ENCI_VBI_CGMSDT_L 0x1b27 	///../ucode/register.h
#define P_ENCI_VBI_CGMSDT_L 		CBUS_REG_ADDR(ENCI_VBI_CGMSDT_L) 	///../ucode/register.h
#define ENCI_VBI_CGMSDT_H 0x1b28 	///../ucode/register.h
#define P_ENCI_VBI_CGMSDT_H 		CBUS_REG_ADDR(ENCI_VBI_CGMSDT_H) 	///../ucode/register.h
#define ENCI_VBI_CGMS_LN 0x1b29 	///../ucode/register.h
#define P_ENCI_VBI_CGMS_LN 		CBUS_REG_ADDR(ENCI_VBI_CGMS_LN) 	///../ucode/register.h
#define ENCI_VBI_TTX_HTIME 0x1b2a 	///../ucode/register.h
#define P_ENCI_VBI_TTX_HTIME 		CBUS_REG_ADDR(ENCI_VBI_TTX_HTIME) 	///../ucode/register.h
#define ENCI_VBI_TTX_LN 0x1b2b 	///../ucode/register.h
#define P_ENCI_VBI_TTX_LN 		CBUS_REG_ADDR(ENCI_VBI_TTX_LN) 	///../ucode/register.h
#define ENCI_VBI_TTXDT0 0x1b2c 	///../ucode/register.h
#define P_ENCI_VBI_TTXDT0 		CBUS_REG_ADDR(ENCI_VBI_TTXDT0) 	///../ucode/register.h
#define ENCI_VBI_TTXDT1 0x1b2d 	///../ucode/register.h
#define P_ENCI_VBI_TTXDT1 		CBUS_REG_ADDR(ENCI_VBI_TTXDT1) 	///../ucode/register.h
#define ENCI_VBI_TTXDT2 0x1b2e 	///../ucode/register.h
#define P_ENCI_VBI_TTXDT2 		CBUS_REG_ADDR(ENCI_VBI_TTXDT2) 	///../ucode/register.h
#define ENCI_VBI_TTXDT3 0x1b2f 	///../ucode/register.h
#define P_ENCI_VBI_TTXDT3 		CBUS_REG_ADDR(ENCI_VBI_TTXDT3) 	///../ucode/register.h
#define ENCI_MACV_N0 0x1b30 	///../ucode/register.h
#define P_ENCI_MACV_N0 		CBUS_REG_ADDR(ENCI_MACV_N0) 	///../ucode/register.h
#define ENCI_MACV_N1 0x1b31 	///../ucode/register.h
#define P_ENCI_MACV_N1 		CBUS_REG_ADDR(ENCI_MACV_N1) 	///../ucode/register.h
#define ENCI_MACV_N2 0x1b32 	///../ucode/register.h
#define P_ENCI_MACV_N2 		CBUS_REG_ADDR(ENCI_MACV_N2) 	///../ucode/register.h
#define ENCI_MACV_N3 0x1b33 	///../ucode/register.h
#define P_ENCI_MACV_N3 		CBUS_REG_ADDR(ENCI_MACV_N3) 	///../ucode/register.h
#define ENCI_MACV_N4 0x1b34 	///../ucode/register.h
#define P_ENCI_MACV_N4 		CBUS_REG_ADDR(ENCI_MACV_N4) 	///../ucode/register.h
#define ENCI_MACV_N5 0x1b35 	///../ucode/register.h
#define P_ENCI_MACV_N5 		CBUS_REG_ADDR(ENCI_MACV_N5) 	///../ucode/register.h
#define ENCI_MACV_N6 0x1b36 	///../ucode/register.h
#define P_ENCI_MACV_N6 		CBUS_REG_ADDR(ENCI_MACV_N6) 	///../ucode/register.h
#define ENCI_MACV_N7 0x1b37 	///../ucode/register.h
#define P_ENCI_MACV_N7 		CBUS_REG_ADDR(ENCI_MACV_N7) 	///../ucode/register.h
#define ENCI_MACV_N8 0x1b38 	///../ucode/register.h
#define P_ENCI_MACV_N8 		CBUS_REG_ADDR(ENCI_MACV_N8) 	///../ucode/register.h
#define ENCI_MACV_N9 0x1b39 	///../ucode/register.h
#define P_ENCI_MACV_N9 		CBUS_REG_ADDR(ENCI_MACV_N9) 	///../ucode/register.h
#define ENCI_MACV_N10 0x1b3a 	///../ucode/register.h
#define P_ENCI_MACV_N10 		CBUS_REG_ADDR(ENCI_MACV_N10) 	///../ucode/register.h
#define ENCI_MACV_N11 0x1b3b 	///../ucode/register.h
#define P_ENCI_MACV_N11 		CBUS_REG_ADDR(ENCI_MACV_N11) 	///../ucode/register.h
#define ENCI_MACV_N12 0x1b3c 	///../ucode/register.h
#define P_ENCI_MACV_N12 		CBUS_REG_ADDR(ENCI_MACV_N12) 	///../ucode/register.h
#define ENCI_MACV_N13 0x1b3d 	///../ucode/register.h
#define P_ENCI_MACV_N13 		CBUS_REG_ADDR(ENCI_MACV_N13) 	///../ucode/register.h
#define ENCI_MACV_N14 0x1b3e 	///../ucode/register.h
#define P_ENCI_MACV_N14 		CBUS_REG_ADDR(ENCI_MACV_N14) 	///../ucode/register.h
#define ENCI_MACV_N15 0x1b3f 	///../ucode/register.h
#define P_ENCI_MACV_N15 		CBUS_REG_ADDR(ENCI_MACV_N15) 	///../ucode/register.h
#define ENCI_MACV_N16 0x1b40 	///../ucode/register.h
#define P_ENCI_MACV_N16 		CBUS_REG_ADDR(ENCI_MACV_N16) 	///../ucode/register.h
#define ENCI_MACV_N17 0x1b41 	///../ucode/register.h
#define P_ENCI_MACV_N17 		CBUS_REG_ADDR(ENCI_MACV_N17) 	///../ucode/register.h
#define ENCI_MACV_N18 0x1b42 	///../ucode/register.h
#define P_ENCI_MACV_N18 		CBUS_REG_ADDR(ENCI_MACV_N18) 	///../ucode/register.h
#define ENCI_MACV_N19 0x1b43 	///../ucode/register.h
#define P_ENCI_MACV_N19 		CBUS_REG_ADDR(ENCI_MACV_N19) 	///../ucode/register.h
#define ENCI_MACV_N20 0x1b44 	///../ucode/register.h
#define P_ENCI_MACV_N20 		CBUS_REG_ADDR(ENCI_MACV_N20) 	///../ucode/register.h
#define ENCI_MACV_N21 0x1b45 	///../ucode/register.h
#define P_ENCI_MACV_N21 		CBUS_REG_ADDR(ENCI_MACV_N21) 	///../ucode/register.h
#define ENCI_MACV_N22 0x1b46 	///../ucode/register.h
#define P_ENCI_MACV_N22 		CBUS_REG_ADDR(ENCI_MACV_N22) 	///../ucode/register.h
#define ENCI_DBG_PX_RST 0x1b48 	///../ucode/register.h
#define P_ENCI_DBG_PX_RST 		CBUS_REG_ADDR(ENCI_DBG_PX_RST) 	///../ucode/register.h
#define ENCI_DBG_FLDLN_RST 0x1b49 	///../ucode/register.h
#define P_ENCI_DBG_FLDLN_RST 		CBUS_REG_ADDR(ENCI_DBG_FLDLN_RST) 	///../ucode/register.h
#define ENCI_DBG_PX_INT 0x1b4a 	///../ucode/register.h
#define P_ENCI_DBG_PX_INT 		CBUS_REG_ADDR(ENCI_DBG_PX_INT) 	///../ucode/register.h
#define ENCI_DBG_FLDLN_INT 0x1b4b 	///../ucode/register.h
#define P_ENCI_DBG_FLDLN_INT 		CBUS_REG_ADDR(ENCI_DBG_FLDLN_INT) 	///../ucode/register.h
#define ENCI_DBG_MAXPX 0x1b4c 	///../ucode/register.h
#define P_ENCI_DBG_MAXPX 		CBUS_REG_ADDR(ENCI_DBG_MAXPX) 	///../ucode/register.h
#define ENCI_DBG_MAXLN 0x1b4d 	///../ucode/register.h
#define P_ENCI_DBG_MAXLN 		CBUS_REG_ADDR(ENCI_DBG_MAXLN) 	///../ucode/register.h
#define ENCI_MACV_MAX_AMP 0x1b50 	///../ucode/register.h
#define P_ENCI_MACV_MAX_AMP 		CBUS_REG_ADDR(ENCI_MACV_MAX_AMP) 	///../ucode/register.h
#define ENCI_MACV_PULSE_LO 0x1b51 	///../ucode/register.h
#define P_ENCI_MACV_PULSE_LO 		CBUS_REG_ADDR(ENCI_MACV_PULSE_LO) 	///../ucode/register.h
#define ENCI_MACV_PULSE_HI 0x1b52 	///../ucode/register.h
#define P_ENCI_MACV_PULSE_HI 		CBUS_REG_ADDR(ENCI_MACV_PULSE_HI) 	///../ucode/register.h
#define ENCI_MACV_BKP_MAX 0x1b53 	///../ucode/register.h
#define P_ENCI_MACV_BKP_MAX 		CBUS_REG_ADDR(ENCI_MACV_BKP_MAX) 	///../ucode/register.h
#define ENCI_CFILT_CTRL 0x1b54 	///../ucode/register.h
#define P_ENCI_CFILT_CTRL 		CBUS_REG_ADDR(ENCI_CFILT_CTRL) 	///../ucode/register.h
#define ENCI_CFILT7 0x1b55 	///../ucode/register.h
#define P_ENCI_CFILT7 		CBUS_REG_ADDR(ENCI_CFILT7) 	///../ucode/register.h
#define ENCI_YC_DELAY 0x1b56 	///../ucode/register.h
#define P_ENCI_YC_DELAY 		CBUS_REG_ADDR(ENCI_YC_DELAY) 	///../ucode/register.h
#define ENCI_VIDEO_EN 0x1b57 	///../ucode/register.h
#define P_ENCI_VIDEO_EN 		CBUS_REG_ADDR(ENCI_VIDEO_EN) 	///../ucode/register.h
#define ENCI_DVI_HSO_BEGIN 0x1c00 	///../ucode/register.h
#define P_ENCI_DVI_HSO_BEGIN 		CBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN) 	///../ucode/register.h
#define ENCI_DVI_HSO_END 0x1c01 	///../ucode/register.h
#define P_ENCI_DVI_HSO_END 		CBUS_REG_ADDR(ENCI_DVI_HSO_END) 	///../ucode/register.h
#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 	///../ucode/register.h
#define P_ENCI_DVI_VSO_BLINE_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN) 	///../ucode/register.h
#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 	///../ucode/register.h
#define P_ENCI_DVI_VSO_BLINE_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD) 	///../ucode/register.h
#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 	///../ucode/register.h
#define P_ENCI_DVI_VSO_ELINE_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN) 	///../ucode/register.h
#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 	///../ucode/register.h
#define P_ENCI_DVI_VSO_ELINE_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD) 	///../ucode/register.h
#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 	///../ucode/register.h
#define P_ENCI_DVI_VSO_BEGIN_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN) 	///../ucode/register.h
#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 	///../ucode/register.h
#define P_ENCI_DVI_VSO_BEGIN_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD) 	///../ucode/register.h
#define ENCI_DVI_VSO_END_EVN 0x1c08 	///../ucode/register.h
#define P_ENCI_DVI_VSO_END_EVN 		CBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN) 	///../ucode/register.h
#define ENCI_DVI_VSO_END_ODD 0x1c09 	///../ucode/register.h
#define P_ENCI_DVI_VSO_END_ODD 		CBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD) 	///../ucode/register.h
#define ENCI_CFILT_CTRL2 0x1c0a 	///../ucode/register.h
#define P_ENCI_CFILT_CTRL2 		CBUS_REG_ADDR(ENCI_CFILT_CTRL2) 	///../ucode/register.h
#define ENCI_DACSEL_0 0x1c0b 	///../ucode/register.h
#define P_ENCI_DACSEL_0 		CBUS_REG_ADDR(ENCI_DACSEL_0) 	///../ucode/register.h
#define ENCI_DACSEL_1 0x1c0c 	///../ucode/register.h
#define P_ENCI_DACSEL_1 		CBUS_REG_ADDR(ENCI_DACSEL_1) 	///../ucode/register.h
#define ENCP_DACSEL_0 0x1c0d 	///../ucode/register.h
#define P_ENCP_DACSEL_0 		CBUS_REG_ADDR(ENCP_DACSEL_0) 	///../ucode/register.h
#define ENCP_DACSEL_1 0x1c0e 	///../ucode/register.h
#define P_ENCP_DACSEL_1 		CBUS_REG_ADDR(ENCP_DACSEL_1) 	///../ucode/register.h
#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f 	///../ucode/register.h
#define P_ENCP_MAX_LINE_SWITCH_POINT 		CBUS_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT) 	///../ucode/register.h
#define ENCI_TST_EN 0x1c10 	///../ucode/register.h
#define P_ENCI_TST_EN 		CBUS_REG_ADDR(ENCI_TST_EN) 	///../ucode/register.h
#define ENCI_TST_MDSEL 0x1c11 	///../ucode/register.h
#define P_ENCI_TST_MDSEL 		CBUS_REG_ADDR(ENCI_TST_MDSEL) 	///../ucode/register.h
#define ENCI_TST_Y 0x1c12 	///../ucode/register.h
#define P_ENCI_TST_Y 		CBUS_REG_ADDR(ENCI_TST_Y) 	///../ucode/register.h
#define ENCI_TST_CB 0x1c13 	///../ucode/register.h
#define P_ENCI_TST_CB 		CBUS_REG_ADDR(ENCI_TST_CB) 	///../ucode/register.h
#define ENCI_TST_CR 0x1c14 	///../ucode/register.h
#define P_ENCI_TST_CR 		CBUS_REG_ADDR(ENCI_TST_CR) 	///../ucode/register.h
#define ENCI_TST_CLRBAR_STRT 0x1c15 	///../ucode/register.h
#define P_ENCI_TST_CLRBAR_STRT 		CBUS_REG_ADDR(ENCI_TST_CLRBAR_STRT) 	///../ucode/register.h
#define ENCI_TST_CLRBAR_WIDTH 0x1c16 	///../ucode/register.h
#define P_ENCI_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(ENCI_TST_CLRBAR_WIDTH) 	///../ucode/register.h
#define ENCI_TST_VDCNT_STSET 0x1c17 	///../ucode/register.h
#define P_ENCI_TST_VDCNT_STSET 		CBUS_REG_ADDR(ENCI_TST_VDCNT_STSET) 	///../ucode/register.h
#define ENCI_VFIFO2VD_CTL 0x1c18 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCI_VFIFO2VD_CTL) 	///../ucode/register.h
#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START) 	///../ucode/register.h
#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END) 	///../ucode/register.h
#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START) 	///../ucode/register.h
#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END) 	///../ucode/register.h
#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START) 	///../ucode/register.h
#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END) 	///../ucode/register.h
#define ENCI_VFIFO2VD_CTL2 0x1c1f 	///../ucode/register.h
#define P_ENCI_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCI_VFIFO2VD_CTL2) 	///../ucode/register.h
#define ENCT_VFIFO2VD_CTL 0x1c20 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCT_VFIFO2VD_CTL) 	///../ucode/register.h
#define ENCT_VFIFO2VD_PIXEL_START 0x1c21 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCT_VFIFO2VD_PIXEL_START) 	///../ucode/register.h
#define ENCT_VFIFO2VD_PIXEL_END 0x1c22 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCT_VFIFO2VD_PIXEL_END) 	///../ucode/register.h
#define ENCT_VFIFO2VD_LINE_TOP_START 0x1c23 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_START) 	///../ucode/register.h
#define ENCT_VFIFO2VD_LINE_TOP_END 0x1c24 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_TOP_END) 	///../ucode/register.h
#define ENCT_VFIFO2VD_LINE_BOT_START 0x1c25 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_START) 	///../ucode/register.h
#define ENCT_VFIFO2VD_LINE_BOT_END 0x1c26 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCT_VFIFO2VD_LINE_BOT_END) 	///../ucode/register.h
#define ENCT_VFIFO2VD_CTL2 0x1c27 	///../ucode/register.h
#define P_ENCT_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCT_VFIFO2VD_CTL2) 	///../ucode/register.h
#define ENCT_TST_EN 0x1c28 	///../ucode/register.h
#define P_ENCT_TST_EN 		CBUS_REG_ADDR(ENCT_TST_EN) 	///../ucode/register.h
#define ENCT_TST_MDSEL 0x1c29 	///../ucode/register.h
#define P_ENCT_TST_MDSEL 		CBUS_REG_ADDR(ENCT_TST_MDSEL) 	///../ucode/register.h
#define ENCT_TST_Y 0x1c2a 	///../ucode/register.h
#define P_ENCT_TST_Y 		CBUS_REG_ADDR(ENCT_TST_Y) 	///../ucode/register.h
#define ENCT_TST_CB 0x1c2b 	///../ucode/register.h
#define P_ENCT_TST_CB 		CBUS_REG_ADDR(ENCT_TST_CB) 	///../ucode/register.h
#define ENCT_TST_CR 0x1c2c 	///../ucode/register.h
#define P_ENCT_TST_CR 		CBUS_REG_ADDR(ENCT_TST_CR) 	///../ucode/register.h
#define ENCT_TST_CLRBAR_STRT 0x1c2d 	///../ucode/register.h
#define P_ENCT_TST_CLRBAR_STRT 		CBUS_REG_ADDR(ENCT_TST_CLRBAR_STRT) 	///../ucode/register.h
#define ENCT_TST_CLRBAR_WIDTH 0x1c2e 	///../ucode/register.h
#define P_ENCT_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(ENCT_TST_CLRBAR_WIDTH) 	///../ucode/register.h
#define ENCT_TST_VDCNT_STSET 0x1c2f 	///../ucode/register.h
#define P_ENCT_TST_VDCNT_STSET 		CBUS_REG_ADDR(ENCT_TST_VDCNT_STSET) 	///../ucode/register.h
#define ENCP_DVI_HSO_BEGIN 0x1c30 	///../ucode/register.h
#define P_ENCP_DVI_HSO_BEGIN 		CBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN) 	///../ucode/register.h
#define ENCP_DVI_HSO_END 0x1c31 	///../ucode/register.h
#define P_ENCP_DVI_HSO_END 		CBUS_REG_ADDR(ENCP_DVI_HSO_END) 	///../ucode/register.h
#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 	///../ucode/register.h
#define P_ENCP_DVI_VSO_BLINE_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN) 	///../ucode/register.h
#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 	///../ucode/register.h
#define P_ENCP_DVI_VSO_BLINE_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD) 	///../ucode/register.h
#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 	///../ucode/register.h
#define P_ENCP_DVI_VSO_ELINE_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN) 	///../ucode/register.h
#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 	///../ucode/register.h
#define P_ENCP_DVI_VSO_ELINE_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD) 	///../ucode/register.h
#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 	///../ucode/register.h
#define P_ENCP_DVI_VSO_BEGIN_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN) 	///../ucode/register.h
#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 	///../ucode/register.h
#define P_ENCP_DVI_VSO_BEGIN_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD) 	///../ucode/register.h
#define ENCP_DVI_VSO_END_EVN 0x1c38 	///../ucode/register.h
#define P_ENCP_DVI_VSO_END_EVN 		CBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN) 	///../ucode/register.h
#define ENCP_DVI_VSO_END_ODD 0x1c39 	///../ucode/register.h
#define P_ENCP_DVI_VSO_END_ODD 		CBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD) 	///../ucode/register.h
#define ENCP_DE_H_BEGIN 0x1c3a 	///../ucode/register.h
#define P_ENCP_DE_H_BEGIN 		CBUS_REG_ADDR(ENCP_DE_H_BEGIN) 	///../ucode/register.h
#define ENCP_DE_H_END 0x1c3b 	///../ucode/register.h
#define P_ENCP_DE_H_END 		CBUS_REG_ADDR(ENCP_DE_H_END) 	///../ucode/register.h
#define ENCP_DE_V_BEGIN_EVEN 0x1c3c 	///../ucode/register.h
#define P_ENCP_DE_V_BEGIN_EVEN 		CBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN) 	///../ucode/register.h
#define ENCP_DE_V_END_EVEN 0x1c3d 	///../ucode/register.h
#define P_ENCP_DE_V_END_EVEN 		CBUS_REG_ADDR(ENCP_DE_V_END_EVEN) 	///../ucode/register.h
#define ENCP_DE_V_BEGIN_ODD 0x1c3e 	///../ucode/register.h
#define P_ENCP_DE_V_BEGIN_ODD 		CBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD) 	///../ucode/register.h
#define ENCP_DE_V_END_ODD 0x1c3f 	///../ucode/register.h
#define P_ENCP_DE_V_END_ODD 		CBUS_REG_ADDR(ENCP_DE_V_END_ODD) 	///../ucode/register.h
#define ENCI_SYNC_LINE_LENGTH 0x1c40 	///../ucode/register.h
#define P_ENCI_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCI_SYNC_LINE_LENGTH) 	///../ucode/register.h
#define ENCI_SYNC_PIXEL_EN 0x1c41 	///../ucode/register.h
#define P_ENCI_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN) 	///../ucode/register.h
#define ENCI_SYNC_TO_LINE_EN 0x1c42 	///../ucode/register.h
#define P_ENCI_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN) 	///../ucode/register.h
#define ENCI_SYNC_TO_PIXEL 0x1c43 	///../ucode/register.h
#define P_ENCI_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL) 	///../ucode/register.h
#define ENCP_SYNC_LINE_LENGTH 0x1c44 	///../ucode/register.h
#define P_ENCP_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCP_SYNC_LINE_LENGTH) 	///../ucode/register.h
#define ENCP_SYNC_PIXEL_EN 0x1c45 	///../ucode/register.h
#define P_ENCP_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCP_SYNC_PIXEL_EN) 	///../ucode/register.h
#define ENCP_SYNC_TO_LINE_EN 0x1c46 	///../ucode/register.h
#define P_ENCP_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCP_SYNC_TO_LINE_EN) 	///../ucode/register.h
#define ENCP_SYNC_TO_PIXEL 0x1c47 	///../ucode/register.h
#define P_ENCP_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL) 	///../ucode/register.h
#define ENCT_SYNC_LINE_LENGTH 0x1c48 	///../ucode/register.h
#define P_ENCT_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCT_SYNC_LINE_LENGTH) 	///../ucode/register.h
#define ENCT_SYNC_PIXEL_EN 0x1c49 	///../ucode/register.h
#define P_ENCT_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCT_SYNC_PIXEL_EN) 	///../ucode/register.h
#define ENCT_SYNC_TO_LINE_EN 0x1c4a 	///../ucode/register.h
#define P_ENCT_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCT_SYNC_TO_LINE_EN) 	///../ucode/register.h
#define ENCT_SYNC_TO_PIXEL 0x1c4b 	///../ucode/register.h
#define P_ENCT_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCT_SYNC_TO_PIXEL) 	///../ucode/register.h
#define ENCL_SYNC_LINE_LENGTH 0x1c4c 	///../ucode/register.h
#define P_ENCL_SYNC_LINE_LENGTH 		CBUS_REG_ADDR(ENCL_SYNC_LINE_LENGTH) 	///../ucode/register.h
#define ENCL_SYNC_PIXEL_EN 0x1c4d 	///../ucode/register.h
#define P_ENCL_SYNC_PIXEL_EN 		CBUS_REG_ADDR(ENCL_SYNC_PIXEL_EN) 	///../ucode/register.h
#define ENCL_SYNC_TO_LINE_EN 0x1c4e 	///../ucode/register.h
#define P_ENCL_SYNC_TO_LINE_EN 		CBUS_REG_ADDR(ENCL_SYNC_TO_LINE_EN) 	///../ucode/register.h
#define ENCL_SYNC_TO_PIXEL 0x1c4f 	///../ucode/register.h
#define P_ENCL_SYNC_TO_PIXEL 		CBUS_REG_ADDR(ENCL_SYNC_TO_PIXEL) 	///../ucode/register.h
#define ENCP_VFIFO2VD_CTL2 0x1c50 	///../ucode/register.h
#define P_ENCP_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCP_VFIFO2VD_CTL2) 	///../ucode/register.h
#define VENC_DVI_SETTING_MORE 0x1c51 	///../ucode/register.h
#define P_VENC_DVI_SETTING_MORE 		CBUS_REG_ADDR(VENC_DVI_SETTING_MORE) 	///../ucode/register.h
#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54 	///../ucode/register.h
#define P_VENC_VDAC_DAC4_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL0) 	///../ucode/register.h
#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55 	///../ucode/register.h
#define P_VENC_VDAC_DAC4_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC4_FILT_CTRL1) 	///../ucode/register.h
#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56 	///../ucode/register.h
#define P_VENC_VDAC_DAC5_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL0) 	///../ucode/register.h
#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57 	///../ucode/register.h
#define P_VENC_VDAC_DAC5_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC5_FILT_CTRL1) 	///../ucode/register.h
#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58 	///../ucode/register.h
#define P_VENC_VDAC_DAC0_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL0) 	///../ucode/register.h
#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59 	///../ucode/register.h
#define P_VENC_VDAC_DAC0_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC0_FILT_CTRL1) 	///../ucode/register.h
#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a 	///../ucode/register.h
#define P_VENC_VDAC_DAC1_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL0) 	///../ucode/register.h
#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b 	///../ucode/register.h
#define P_VENC_VDAC_DAC1_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC1_FILT_CTRL1) 	///../ucode/register.h
#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c 	///../ucode/register.h
#define P_VENC_VDAC_DAC2_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL0) 	///../ucode/register.h
#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d 	///../ucode/register.h
#define P_VENC_VDAC_DAC2_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC2_FILT_CTRL1) 	///../ucode/register.h
#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e 	///../ucode/register.h
#define P_VENC_VDAC_DAC3_FILT_CTRL0 		CBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL0) 	///../ucode/register.h
#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f 	///../ucode/register.h
#define P_VENC_VDAC_DAC3_FILT_CTRL1 		CBUS_REG_ADDR(VENC_VDAC_DAC3_FILT_CTRL1) 	///../ucode/register.h
#define ENCT_VIDEO_EN 0x1c60 	///../ucode/register.h
#define P_ENCT_VIDEO_EN 		CBUS_REG_ADDR(ENCT_VIDEO_EN) 	///../ucode/register.h
#define ENCT_VIDEO_Y_SCL 0x1c61 	///../ucode/register.h
#define P_ENCT_VIDEO_Y_SCL 		CBUS_REG_ADDR(ENCT_VIDEO_Y_SCL) 	///../ucode/register.h
#define ENCT_VIDEO_PB_SCL 0x1c62 	///../ucode/register.h
#define P_ENCT_VIDEO_PB_SCL 		CBUS_REG_ADDR(ENCT_VIDEO_PB_SCL) 	///../ucode/register.h
#define ENCT_VIDEO_PR_SCL 0x1c63 	///../ucode/register.h
#define P_ENCT_VIDEO_PR_SCL 		CBUS_REG_ADDR(ENCT_VIDEO_PR_SCL) 	///../ucode/register.h
#define ENCT_VIDEO_Y_OFFST 0x1c64 	///../ucode/register.h
#define P_ENCT_VIDEO_Y_OFFST 		CBUS_REG_ADDR(ENCT_VIDEO_Y_OFFST) 	///../ucode/register.h
#define ENCT_VIDEO_PB_OFFST 0x1c65 	///../ucode/register.h
#define P_ENCT_VIDEO_PB_OFFST 		CBUS_REG_ADDR(ENCT_VIDEO_PB_OFFST) 	///../ucode/register.h
#define ENCT_VIDEO_PR_OFFST 0x1c66 	///../ucode/register.h
#define P_ENCT_VIDEO_PR_OFFST 		CBUS_REG_ADDR(ENCT_VIDEO_PR_OFFST) 	///../ucode/register.h
#define ENCT_VIDEO_MODE 0x1c67 	///../ucode/register.h
#define P_ENCT_VIDEO_MODE 		CBUS_REG_ADDR(ENCT_VIDEO_MODE) 	///../ucode/register.h
#define ENCT_VIDEO_MODE_ADV 0x1c68 	///../ucode/register.h
#define P_ENCT_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCT_VIDEO_MODE_ADV) 	///../ucode/register.h
#define ENCT_DBG_PX_RST 0x1c69 	///../ucode/register.h
#define P_ENCT_DBG_PX_RST 		CBUS_REG_ADDR(ENCT_DBG_PX_RST) 	///../ucode/register.h
#define ENCT_DBG_LN_RST 0x1c6a 	///../ucode/register.h
#define P_ENCT_DBG_LN_RST 		CBUS_REG_ADDR(ENCT_DBG_LN_RST) 	///../ucode/register.h
#define ENCT_DBG_PX_INT 0x1c6b 	///../ucode/register.h
#define P_ENCT_DBG_PX_INT 		CBUS_REG_ADDR(ENCT_DBG_PX_INT) 	///../ucode/register.h
#define ENCT_DBG_LN_INT 0x1c6c 	///../ucode/register.h
#define P_ENCT_DBG_LN_INT 		CBUS_REG_ADDR(ENCT_DBG_LN_INT) 	///../ucode/register.h
#define ENCT_VIDEO_YFP1_HTIME 0x1c6d 	///../ucode/register.h
#define P_ENCT_VIDEO_YFP1_HTIME 		CBUS_REG_ADDR(ENCT_VIDEO_YFP1_HTIME) 	///../ucode/register.h
#define ENCT_VIDEO_YFP2_HTIME 0x1c6e 	///../ucode/register.h
#define P_ENCT_VIDEO_YFP2_HTIME 		CBUS_REG_ADDR(ENCT_VIDEO_YFP2_HTIME) 	///../ucode/register.h
#define ENCT_VIDEO_YC_DLY 0x1c6f 	///../ucode/register.h
#define P_ENCT_VIDEO_YC_DLY 		CBUS_REG_ADDR(ENCT_VIDEO_YC_DLY) 	///../ucode/register.h
#define ENCT_VIDEO_MAX_PXCNT 0x1c70 	///../ucode/register.h
#define P_ENCT_VIDEO_MAX_PXCNT 		CBUS_REG_ADDR(ENCT_VIDEO_MAX_PXCNT) 	///../ucode/register.h
#define ENCT_VIDEO_HAVON_END 0x1c71 	///../ucode/register.h
#define P_ENCT_VIDEO_HAVON_END 		CBUS_REG_ADDR(ENCT_VIDEO_HAVON_END) 	///../ucode/register.h
#define ENCT_VIDEO_HAVON_BEGIN 0x1c72 	///../ucode/register.h
#define P_ENCT_VIDEO_HAVON_BEGIN 		CBUS_REG_ADDR(ENCT_VIDEO_HAVON_BEGIN) 	///../ucode/register.h
#define ENCT_VIDEO_VAVON_ELINE 0x1c73 	///../ucode/register.h
#define P_ENCT_VIDEO_VAVON_ELINE 		CBUS_REG_ADDR(ENCT_VIDEO_VAVON_ELINE) 	///../ucode/register.h
#define ENCT_VIDEO_VAVON_BLINE 0x1c74 	///../ucode/register.h
#define P_ENCT_VIDEO_VAVON_BLINE 		CBUS_REG_ADDR(ENCT_VIDEO_VAVON_BLINE) 	///../ucode/register.h
#define ENCT_VIDEO_HSO_BEGIN 0x1c75 	///../ucode/register.h
#define P_ENCT_VIDEO_HSO_BEGIN 		CBUS_REG_ADDR(ENCT_VIDEO_HSO_BEGIN) 	///../ucode/register.h
#define ENCT_VIDEO_HSO_END 0x1c76 	///../ucode/register.h
#define P_ENCT_VIDEO_HSO_END 		CBUS_REG_ADDR(ENCT_VIDEO_HSO_END) 	///../ucode/register.h
#define ENCT_VIDEO_VSO_BEGIN 0x1c77 	///../ucode/register.h
#define P_ENCT_VIDEO_VSO_BEGIN 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_BEGIN) 	///../ucode/register.h
#define ENCT_VIDEO_VSO_END 0x1c78 	///../ucode/register.h
#define P_ENCT_VIDEO_VSO_END 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_END) 	///../ucode/register.h
#define ENCT_VIDEO_VSO_BLINE 0x1c79 	///../ucode/register.h
#define P_ENCT_VIDEO_VSO_BLINE 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_BLINE) 	///../ucode/register.h
#define ENCT_VIDEO_VSO_ELINE 0x1c7a 	///../ucode/register.h
#define P_ENCT_VIDEO_VSO_ELINE 		CBUS_REG_ADDR(ENCT_VIDEO_VSO_ELINE) 	///../ucode/register.h
#define ENCT_VIDEO_MAX_LNCNT 0x1c7b 	///../ucode/register.h
#define P_ENCT_VIDEO_MAX_LNCNT 		CBUS_REG_ADDR(ENCT_VIDEO_MAX_LNCNT) 	///../ucode/register.h
#define ENCT_VIDEO_BLANKY_VAL 0x1c7c 	///../ucode/register.h
#define P_ENCT_VIDEO_BLANKY_VAL 		CBUS_REG_ADDR(ENCT_VIDEO_BLANKY_VAL) 	///../ucode/register.h
#define ENCT_VIDEO_BLANKPB_VAL 0x1c7d 	///../ucode/register.h
#define P_ENCT_VIDEO_BLANKPB_VAL 		CBUS_REG_ADDR(ENCT_VIDEO_BLANKPB_VAL) 	///../ucode/register.h
#define ENCT_VIDEO_BLANKPR_VAL 0x1c7e 	///../ucode/register.h
#define P_ENCT_VIDEO_BLANKPR_VAL 		CBUS_REG_ADDR(ENCT_VIDEO_BLANKPR_VAL) 	///../ucode/register.h
#define ENCT_VIDEO_HOFFST 0x1c7f 	///../ucode/register.h
#define P_ENCT_VIDEO_HOFFST 		CBUS_REG_ADDR(ENCT_VIDEO_HOFFST) 	///../ucode/register.h
#define ENCT_VIDEO_VOFFST 0x1c80 	///../ucode/register.h
#define P_ENCT_VIDEO_VOFFST 		CBUS_REG_ADDR(ENCT_VIDEO_VOFFST) 	///../ucode/register.h
#define ENCT_VIDEO_RGB_CTRL 0x1c81 	///../ucode/register.h
#define P_ENCT_VIDEO_RGB_CTRL 		CBUS_REG_ADDR(ENCT_VIDEO_RGB_CTRL) 	///../ucode/register.h
#define ENCT_VIDEO_FILT_CTRL 0x1c82 	///../ucode/register.h
#define P_ENCT_VIDEO_FILT_CTRL 		CBUS_REG_ADDR(ENCT_VIDEO_FILT_CTRL) 	///../ucode/register.h
#define ENCT_VIDEO_OFLD_VPEQ_OFST 0x1c83 	///../ucode/register.h
#define P_ENCT_VIDEO_OFLD_VPEQ_OFST 		CBUS_REG_ADDR(ENCT_VIDEO_OFLD_VPEQ_OFST) 	///../ucode/register.h
#define ENCT_VIDEO_OFLD_VOAV_OFST 0x1c84 	///../ucode/register.h
#define P_ENCT_VIDEO_OFLD_VOAV_OFST 		CBUS_REG_ADDR(ENCT_VIDEO_OFLD_VOAV_OFST) 	///../ucode/register.h
#define ENCT_VIDEO_MATRIX_CB 0x1c85 	///../ucode/register.h
#define P_ENCT_VIDEO_MATRIX_CB 		CBUS_REG_ADDR(ENCT_VIDEO_MATRIX_CB) 	///../ucode/register.h
#define ENCT_VIDEO_MATRIX_CR 0x1c86 	///../ucode/register.h
#define P_ENCT_VIDEO_MATRIX_CR 		CBUS_REG_ADDR(ENCT_VIDEO_MATRIX_CR) 	///../ucode/register.h
#define ENCT_VIDEO_RGBIN_CTRL 0x1c87 	///../ucode/register.h
#define P_ENCT_VIDEO_RGBIN_CTRL 		CBUS_REG_ADDR(ENCT_VIDEO_RGBIN_CTRL) 	///../ucode/register.h
#define ENCT_MAX_LINE_SWITCH_POINT 0x1c88 	///../ucode/register.h
#define P_ENCT_MAX_LINE_SWITCH_POINT 		CBUS_REG_ADDR(ENCT_MAX_LINE_SWITCH_POINT) 	///../ucode/register.h
#define ENCT_DACSEL_0 0x1c89 	///../ucode/register.h
#define P_ENCT_DACSEL_0 		CBUS_REG_ADDR(ENCT_DACSEL_0) 	///../ucode/register.h
#define ENCT_DACSEL_1 0x1c8a 	///../ucode/register.h
#define P_ENCT_DACSEL_1 		CBUS_REG_ADDR(ENCT_DACSEL_1) 	///../ucode/register.h
#define ENCL_VFIFO2VD_CTL 0x1c90 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_CTL 		CBUS_REG_ADDR(ENCL_VFIFO2VD_CTL) 	///../ucode/register.h
#define ENCL_VFIFO2VD_PIXEL_START 0x1c91 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_PIXEL_START 		CBUS_REG_ADDR(ENCL_VFIFO2VD_PIXEL_START) 	///../ucode/register.h
#define ENCL_VFIFO2VD_PIXEL_END 0x1c92 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_PIXEL_END 		CBUS_REG_ADDR(ENCL_VFIFO2VD_PIXEL_END) 	///../ucode/register.h
#define ENCL_VFIFO2VD_LINE_TOP_START 0x1c93 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_LINE_TOP_START 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_START) 	///../ucode/register.h
#define ENCL_VFIFO2VD_LINE_TOP_END 0x1c94 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_LINE_TOP_END 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_TOP_END) 	///../ucode/register.h
#define ENCL_VFIFO2VD_LINE_BOT_START 0x1c95 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_LINE_BOT_START 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_START) 	///../ucode/register.h
#define ENCL_VFIFO2VD_LINE_BOT_END 0x1c96 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_LINE_BOT_END 		CBUS_REG_ADDR(ENCL_VFIFO2VD_LINE_BOT_END) 	///../ucode/register.h
#define ENCL_VFIFO2VD_CTL2 0x1c97 	///../ucode/register.h
#define P_ENCL_VFIFO2VD_CTL2 		CBUS_REG_ADDR(ENCL_VFIFO2VD_CTL2) 	///../ucode/register.h
#define ENCL_TST_EN 0x1c98 	///../ucode/register.h
#define P_ENCL_TST_EN 		CBUS_REG_ADDR(ENCL_TST_EN) 	///../ucode/register.h
#define ENCL_TST_MDSEL 0x1c99 	///../ucode/register.h
#define P_ENCL_TST_MDSEL 		CBUS_REG_ADDR(ENCL_TST_MDSEL) 	///../ucode/register.h
#define ENCL_TST_Y 0x1c9a 	///../ucode/register.h
#define P_ENCL_TST_Y 		CBUS_REG_ADDR(ENCL_TST_Y) 	///../ucode/register.h
#define ENCL_TST_CB 0x1c9b 	///../ucode/register.h
#define P_ENCL_TST_CB 		CBUS_REG_ADDR(ENCL_TST_CB) 	///../ucode/register.h
#define ENCL_TST_CR 0x1c9c 	///../ucode/register.h
#define P_ENCL_TST_CR 		CBUS_REG_ADDR(ENCL_TST_CR) 	///../ucode/register.h
#define ENCL_TST_CLRBAR_STRT 0x1c9d 	///../ucode/register.h
#define P_ENCL_TST_CLRBAR_STRT 		CBUS_REG_ADDR(ENCL_TST_CLRBAR_STRT) 	///../ucode/register.h
#define ENCL_TST_CLRBAR_WIDTH 0x1c9e 	///../ucode/register.h
#define P_ENCL_TST_CLRBAR_WIDTH 		CBUS_REG_ADDR(ENCL_TST_CLRBAR_WIDTH) 	///../ucode/register.h
#define ENCL_TST_VDCNT_STSET 0x1c9f 	///../ucode/register.h
#define P_ENCL_TST_VDCNT_STSET 		CBUS_REG_ADDR(ENCL_TST_VDCNT_STSET) 	///../ucode/register.h
#define ENCL_VIDEO_EN 0x1ca0 	///../ucode/register.h
#define P_ENCL_VIDEO_EN 		CBUS_REG_ADDR(ENCL_VIDEO_EN) 	///../ucode/register.h
#define ENCL_VIDEO_Y_SCL 0x1ca1 	///../ucode/register.h
#define P_ENCL_VIDEO_Y_SCL 		CBUS_REG_ADDR(ENCL_VIDEO_Y_SCL) 	///../ucode/register.h
#define ENCL_VIDEO_PB_SCL 0x1ca2 	///../ucode/register.h
#define P_ENCL_VIDEO_PB_SCL 		CBUS_REG_ADDR(ENCL_VIDEO_PB_SCL) 	///../ucode/register.h
#define ENCL_VIDEO_PR_SCL 0x1ca3 	///../ucode/register.h
#define P_ENCL_VIDEO_PR_SCL 		CBUS_REG_ADDR(ENCL_VIDEO_PR_SCL) 	///../ucode/register.h
#define ENCL_VIDEO_Y_OFFST 0x1ca4 	///../ucode/register.h
#define P_ENCL_VIDEO_Y_OFFST 		CBUS_REG_ADDR(ENCL_VIDEO_Y_OFFST) 	///../ucode/register.h
#define ENCL_VIDEO_PB_OFFST 0x1ca5 	///../ucode/register.h
#define P_ENCL_VIDEO_PB_OFFST 		CBUS_REG_ADDR(ENCL_VIDEO_PB_OFFST) 	///../ucode/register.h
#define ENCL_VIDEO_PR_OFFST 0x1ca6 	///../ucode/register.h
#define P_ENCL_VIDEO_PR_OFFST 		CBUS_REG_ADDR(ENCL_VIDEO_PR_OFFST) 	///../ucode/register.h
#define ENCL_VIDEO_MODE 0x1ca7 	///../ucode/register.h
#define P_ENCL_VIDEO_MODE 		CBUS_REG_ADDR(ENCL_VIDEO_MODE) 	///../ucode/register.h
#define ENCL_VIDEO_MODE_ADV 0x1ca8 	///../ucode/register.h
#define P_ENCL_VIDEO_MODE_ADV 		CBUS_REG_ADDR(ENCL_VIDEO_MODE_ADV) 	///../ucode/register.h
#define ENCL_DBG_PX_RST 0x1ca9 	///../ucode/register.h
#define P_ENCL_DBG_PX_RST 		CBUS_REG_ADDR(ENCL_DBG_PX_RST) 	///../ucode/register.h
#define ENCL_DBG_LN_RST 0x1caa 	///../ucode/register.h
#define P_ENCL_DBG_LN_RST 		CBUS_REG_ADDR(ENCL_DBG_LN_RST) 	///../ucode/register.h
#define ENCL_DBG_PX_INT 0x1cab 	///../ucode/register.h
#define P_ENCL_DBG_PX_INT 		CBUS_REG_ADDR(ENCL_DBG_PX_INT) 	///../ucode/register.h
#define ENCL_DBG_LN_INT 0x1cac 	///../ucode/register.h
#define P_ENCL_DBG_LN_INT 		CBUS_REG_ADDR(ENCL_DBG_LN_INT) 	///../ucode/register.h
#define ENCL_VIDEO_YFP1_HTIME 0x1cad 	///../ucode/register.h
#define P_ENCL_VIDEO_YFP1_HTIME 		CBUS_REG_ADDR(ENCL_VIDEO_YFP1_HTIME) 	///../ucode/register.h
#define ENCL_VIDEO_YFP2_HTIME 0x1cae 	///../ucode/register.h
#define P_ENCL_VIDEO_YFP2_HTIME 		CBUS_REG_ADDR(ENCL_VIDEO_YFP2_HTIME) 	///../ucode/register.h
#define ENCL_VIDEO_YC_DLY 0x1caf 	///../ucode/register.h
#define P_ENCL_VIDEO_YC_DLY 		CBUS_REG_ADDR(ENCL_VIDEO_YC_DLY) 	///../ucode/register.h
#define ENCL_VIDEO_MAX_PXCNT 0x1cb0 	///../ucode/register.h
#define P_ENCL_VIDEO_MAX_PXCNT 		CBUS_REG_ADDR(ENCL_VIDEO_MAX_PXCNT) 	///../ucode/register.h
#define ENCL_VIDEO_HAVON_END 0x1cb1 	///../ucode/register.h
#define P_ENCL_VIDEO_HAVON_END 		CBUS_REG_ADDR(ENCL_VIDEO_HAVON_END) 	///../ucode/register.h
#define ENCL_VIDEO_HAVON_BEGIN 0x1cb2 	///../ucode/register.h
#define P_ENCL_VIDEO_HAVON_BEGIN 		CBUS_REG_ADDR(ENCL_VIDEO_HAVON_BEGIN) 	///../ucode/register.h
#define ENCL_VIDEO_VAVON_ELINE 0x1cb3 	///../ucode/register.h
#define P_ENCL_VIDEO_VAVON_ELINE 		CBUS_REG_ADDR(ENCL_VIDEO_VAVON_ELINE) 	///../ucode/register.h
#define ENCL_VIDEO_VAVON_BLINE 0x1cb4 	///../ucode/register.h
#define P_ENCL_VIDEO_VAVON_BLINE 		CBUS_REG_ADDR(ENCL_VIDEO_VAVON_BLINE) 	///../ucode/register.h
#define ENCL_VIDEO_HSO_BEGIN 0x1cb5 	///../ucode/register.h
#define P_ENCL_VIDEO_HSO_BEGIN 		CBUS_REG_ADDR(ENCL_VIDEO_HSO_BEGIN) 	///../ucode/register.h
#define ENCL_VIDEO_HSO_END 0x1cb6 	///../ucode/register.h
#define P_ENCL_VIDEO_HSO_END 		CBUS_REG_ADDR(ENCL_VIDEO_HSO_END) 	///../ucode/register.h
#define ENCL_VIDEO_VSO_BEGIN 0x1cb7 	///../ucode/register.h
#define P_ENCL_VIDEO_VSO_BEGIN 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_BEGIN) 	///../ucode/register.h
#define ENCL_VIDEO_VSO_END 0x1cb8 	///../ucode/register.h
#define P_ENCL_VIDEO_VSO_END 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_END) 	///../ucode/register.h
#define ENCL_VIDEO_VSO_BLINE 0x1cb9 	///../ucode/register.h
#define P_ENCL_VIDEO_VSO_BLINE 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_BLINE) 	///../ucode/register.h
#define ENCL_VIDEO_VSO_ELINE 0x1cba 	///../ucode/register.h
#define P_ENCL_VIDEO_VSO_ELINE 		CBUS_REG_ADDR(ENCL_VIDEO_VSO_ELINE) 	///../ucode/register.h
#define ENCL_VIDEO_MAX_LNCNT 0x1cbb 	///../ucode/register.h
#define P_ENCL_VIDEO_MAX_LNCNT 		CBUS_REG_ADDR(ENCL_VIDEO_MAX_LNCNT) 	///../ucode/register.h
#define ENCL_VIDEO_BLANKY_VAL 0x1cbc 	///../ucode/register.h
#define P_ENCL_VIDEO_BLANKY_VAL 		CBUS_REG_ADDR(ENCL_VIDEO_BLANKY_VAL) 	///../ucode/register.h
#define ENCL_VIDEO_BLANKPB_VAL 0x1cbd 	///../ucode/register.h
#define P_ENCL_VIDEO_BLANKPB_VAL 		CBUS_REG_ADDR(ENCL_VIDEO_BLANKPB_VAL) 	///../ucode/register.h
#define ENCL_VIDEO_BLANKPR_VAL 0x1cbe 	///../ucode/register.h
#define P_ENCL_VIDEO_BLANKPR_VAL 		CBUS_REG_ADDR(ENCL_VIDEO_BLANKPR_VAL) 	///../ucode/register.h
#define ENCL_VIDEO_HOFFST 0x1cbf 	///../ucode/register.h
#define P_ENCL_VIDEO_HOFFST 		CBUS_REG_ADDR(ENCL_VIDEO_HOFFST) 	///../ucode/register.h
#define ENCL_VIDEO_VOFFST 0x1cc0 	///../ucode/register.h
#define P_ENCL_VIDEO_VOFFST 		CBUS_REG_ADDR(ENCL_VIDEO_VOFFST) 	///../ucode/register.h
#define ENCL_VIDEO_RGB_CTRL 0x1cc1 	///../ucode/register.h
#define P_ENCL_VIDEO_RGB_CTRL 		CBUS_REG_ADDR(ENCL_VIDEO_RGB_CTRL) 	///../ucode/register.h
#define ENCL_VIDEO_FILT_CTRL 0x1cc2 	///../ucode/register.h
#define P_ENCL_VIDEO_FILT_CTRL 		CBUS_REG_ADDR(ENCL_VIDEO_FILT_CTRL) 	///../ucode/register.h
#define ENCL_VIDEO_OFLD_VPEQ_OFST 0x1cc3 	///../ucode/register.h
#define P_ENCL_VIDEO_OFLD_VPEQ_OFST 		CBUS_REG_ADDR(ENCL_VIDEO_OFLD_VPEQ_OFST) 	///../ucode/register.h
#define ENCL_VIDEO_OFLD_VOAV_OFST 0x1cc4 	///../ucode/register.h
#define P_ENCL_VIDEO_OFLD_VOAV_OFST 		CBUS_REG_ADDR(ENCL_VIDEO_OFLD_VOAV_OFST) 	///../ucode/register.h
#define ENCL_VIDEO_MATRIX_CB 0x1cc5 	///../ucode/register.h
#define P_ENCL_VIDEO_MATRIX_CB 		CBUS_REG_ADDR(ENCL_VIDEO_MATRIX_CB) 	///../ucode/register.h
#define ENCL_VIDEO_MATRIX_CR 0x1cc6 	///../ucode/register.h
#define P_ENCL_VIDEO_MATRIX_CR 		CBUS_REG_ADDR(ENCL_VIDEO_MATRIX_CR) 	///../ucode/register.h
#define ENCL_VIDEO_RGBIN_CTRL 0x1cc7 	///../ucode/register.h
#define P_ENCL_VIDEO_RGBIN_CTRL 		CBUS_REG_ADDR(ENCL_VIDEO_RGBIN_CTRL) 	///../ucode/register.h
#define ENCL_MAX_LINE_SWITCH_POINT 0x1cc8 	///../ucode/register.h
#define P_ENCL_MAX_LINE_SWITCH_POINT 		CBUS_REG_ADDR(ENCL_MAX_LINE_SWITCH_POINT) 	///../ucode/register.h
#define ENCL_DACSEL_0 0x1cc9 	///../ucode/register.h
#define P_ENCL_DACSEL_0 		CBUS_REG_ADDR(ENCL_DACSEL_0) 	///../ucode/register.h
#define ENCL_DACSEL_1 0x1cca 	///../ucode/register.h
#define P_ENCL_DACSEL_1 		CBUS_REG_ADDR(ENCL_DACSEL_1) 	///../ucode/register.h
#define RDMA_AHB_START_ADDR_MAN 0x1cf0 	///../ucode/register.h
#define P_RDMA_AHB_START_ADDR_MAN 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_MAN) 	///../ucode/register.h
#define RDMA_AHB_END_ADDR_MAN 0x1cf1 	///../ucode/register.h
#define P_RDMA_AHB_END_ADDR_MAN 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_MAN) 	///../ucode/register.h
#define RDMA_AHB_START_ADDR_1 0x1cf2 	///../ucode/register.h
#define P_RDMA_AHB_START_ADDR_1 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_1) 	///../ucode/register.h
#define RDMA_AHB_END_ADDR_1 0x1cf3 	///../ucode/register.h
#define P_RDMA_AHB_END_ADDR_1 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_1) 	///../ucode/register.h
#define RDMA_AHB_START_ADDR_2 0x1cf4 	///../ucode/register.h
#define P_RDMA_AHB_START_ADDR_2 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_2) 	///../ucode/register.h
#define RDMA_AHB_END_ADDR_2 0x1cf5 	///../ucode/register.h
#define P_RDMA_AHB_END_ADDR_2 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_2) 	///../ucode/register.h
#define RDMA_AHB_START_ADDR_3 0x1cf6 	///../ucode/register.h
#define P_RDMA_AHB_START_ADDR_3 		CBUS_REG_ADDR(RDMA_AHB_START_ADDR_3) 	///../ucode/register.h
#define RDMA_AHB_END_ADDR_3 0x1cf7 	///../ucode/register.h
#define P_RDMA_AHB_END_ADDR_3 		CBUS_REG_ADDR(RDMA_AHB_END_ADDR_3) 	///../ucode/register.h
#define RDMA_ACCESS_AUTO 0x1cf8 	///../ucode/register.h
#define P_RDMA_ACCESS_AUTO 		CBUS_REG_ADDR(RDMA_ACCESS_AUTO) 	///../ucode/register.h
#define RDMA_ACCESS_MAN 0x1cf9 	///../ucode/register.h
#define P_RDMA_ACCESS_MAN 		CBUS_REG_ADDR(RDMA_ACCESS_MAN) 	///../ucode/register.h
#define RDMA_CTRL 0x1cfa 	///../ucode/register.h
#define P_RDMA_CTRL 		CBUS_REG_ADDR(RDMA_CTRL) 	///../ucode/register.h
#define RDMA_STATUS 0x1cfb 	///../ucode/register.h
#define P_RDMA_STATUS 		CBUS_REG_ADDR(RDMA_STATUS) 	///../ucode/register.h
#define L_GAMMA_CNTL_PORT 0x1400 	///../ucode/register.h
#define P_L_GAMMA_CNTL_PORT 		CBUS_REG_ADDR(L_GAMMA_CNTL_PORT) 	///../ucode/register.h
#define L_GAMMA_DATA_PORT 0x1401 	///../ucode/register.h
#define P_L_GAMMA_DATA_PORT 		CBUS_REG_ADDR(L_GAMMA_DATA_PORT) 	///../ucode/register.h
#define L_GAMMA_ADDR_PORT 0x1402 	///../ucode/register.h
#define P_L_GAMMA_ADDR_PORT 		CBUS_REG_ADDR(L_GAMMA_ADDR_PORT) 	///../ucode/register.h
#define L_GAMMA_VCOM_HSWITCH_ADDR 0x1403 	///../ucode/register.h
#define P_L_GAMMA_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(L_GAMMA_VCOM_HSWITCH_ADDR) 	///../ucode/register.h
#define L_RGB_BASE_ADDR 0x1405 	///../ucode/register.h
#define P_L_RGB_BASE_ADDR 		CBUS_REG_ADDR(L_RGB_BASE_ADDR) 	///../ucode/register.h
#define L_RGB_COEFF_ADDR 0x1406 	///../ucode/register.h
#define P_L_RGB_COEFF_ADDR 		CBUS_REG_ADDR(L_RGB_COEFF_ADDR) 	///../ucode/register.h
#define L_POL_CNTL_ADDR 0x1407 	///../ucode/register.h
#define P_L_POL_CNTL_ADDR 		CBUS_REG_ADDR(L_POL_CNTL_ADDR) 	///../ucode/register.h
#define L_DITH_CNTL_ADDR 0x1408 	///../ucode/register.h
#define P_L_DITH_CNTL_ADDR 		CBUS_REG_ADDR(L_DITH_CNTL_ADDR) 	///../ucode/register.h
#define L_STH1_HS_ADDR 0x1410 	///../ucode/register.h
#define P_L_STH1_HS_ADDR 		CBUS_REG_ADDR(L_STH1_HS_ADDR) 	///../ucode/register.h
#define L_STH1_HE_ADDR 0x1411 	///../ucode/register.h
#define P_L_STH1_HE_ADDR 		CBUS_REG_ADDR(L_STH1_HE_ADDR) 	///../ucode/register.h
#define L_STH1_VS_ADDR 0x1412 	///../ucode/register.h
#define P_L_STH1_VS_ADDR 		CBUS_REG_ADDR(L_STH1_VS_ADDR) 	///../ucode/register.h
#define L_STH1_VE_ADDR 0x1413 	///../ucode/register.h
#define P_L_STH1_VE_ADDR 		CBUS_REG_ADDR(L_STH1_VE_ADDR) 	///../ucode/register.h
#define L_STH2_HS_ADDR 0x1414 	///../ucode/register.h
#define P_L_STH2_HS_ADDR 		CBUS_REG_ADDR(L_STH2_HS_ADDR) 	///../ucode/register.h
#define L_STH2_HE_ADDR 0x1415 	///../ucode/register.h
#define P_L_STH2_HE_ADDR 		CBUS_REG_ADDR(L_STH2_HE_ADDR) 	///../ucode/register.h
#define L_STH2_VS_ADDR 0x1416 	///../ucode/register.h
#define P_L_STH2_VS_ADDR 		CBUS_REG_ADDR(L_STH2_VS_ADDR) 	///../ucode/register.h
#define L_STH2_VE_ADDR 0x1417 	///../ucode/register.h
#define P_L_STH2_VE_ADDR 		CBUS_REG_ADDR(L_STH2_VE_ADDR) 	///../ucode/register.h
#define L_OEH_HS_ADDR 0x1418 	///../ucode/register.h
#define P_L_OEH_HS_ADDR 		CBUS_REG_ADDR(L_OEH_HS_ADDR) 	///../ucode/register.h
#define L_OEH_HE_ADDR 0x1419 	///../ucode/register.h
#define P_L_OEH_HE_ADDR 		CBUS_REG_ADDR(L_OEH_HE_ADDR) 	///../ucode/register.h
#define L_OEH_VS_ADDR 0x141a 	///../ucode/register.h
#define P_L_OEH_VS_ADDR 		CBUS_REG_ADDR(L_OEH_VS_ADDR) 	///../ucode/register.h
#define L_OEH_VE_ADDR 0x141b 	///../ucode/register.h
#define P_L_OEH_VE_ADDR 		CBUS_REG_ADDR(L_OEH_VE_ADDR) 	///../ucode/register.h
#define L_VCOM_HSWITCH_ADDR 0x141c 	///../ucode/register.h
#define P_L_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(L_VCOM_HSWITCH_ADDR) 	///../ucode/register.h
#define L_VCOM_VS_ADDR 0x141d 	///../ucode/register.h
#define P_L_VCOM_VS_ADDR 		CBUS_REG_ADDR(L_VCOM_VS_ADDR) 	///../ucode/register.h
#define L_VCOM_VE_ADDR 0x141e 	///../ucode/register.h
#define P_L_VCOM_VE_ADDR 		CBUS_REG_ADDR(L_VCOM_VE_ADDR) 	///../ucode/register.h
#define L_CPV1_HS_ADDR 0x141f 	///../ucode/register.h
#define P_L_CPV1_HS_ADDR 		CBUS_REG_ADDR(L_CPV1_HS_ADDR) 	///../ucode/register.h
#define L_CPV1_HE_ADDR 0x1420 	///../ucode/register.h
#define P_L_CPV1_HE_ADDR 		CBUS_REG_ADDR(L_CPV1_HE_ADDR) 	///../ucode/register.h
#define L_CPV1_VS_ADDR 0x1421 	///../ucode/register.h
#define P_L_CPV1_VS_ADDR 		CBUS_REG_ADDR(L_CPV1_VS_ADDR) 	///../ucode/register.h
#define L_CPV1_VE_ADDR 0x1422 	///../ucode/register.h
#define P_L_CPV1_VE_ADDR 		CBUS_REG_ADDR(L_CPV1_VE_ADDR) 	///../ucode/register.h
#define L_CPV2_HS_ADDR 0x1423 	///../ucode/register.h
#define P_L_CPV2_HS_ADDR 		CBUS_REG_ADDR(L_CPV2_HS_ADDR) 	///../ucode/register.h
#define L_CPV2_HE_ADDR 0x1424 	///../ucode/register.h
#define P_L_CPV2_HE_ADDR 		CBUS_REG_ADDR(L_CPV2_HE_ADDR) 	///../ucode/register.h
#define L_CPV2_VS_ADDR 0x1425 	///../ucode/register.h
#define P_L_CPV2_VS_ADDR 		CBUS_REG_ADDR(L_CPV2_VS_ADDR) 	///../ucode/register.h
#define L_CPV2_VE_ADDR 0x1426 	///../ucode/register.h
#define P_L_CPV2_VE_ADDR 		CBUS_REG_ADDR(L_CPV2_VE_ADDR) 	///../ucode/register.h
#define L_STV1_HS_ADDR 0x1427 	///../ucode/register.h
#define P_L_STV1_HS_ADDR 		CBUS_REG_ADDR(L_STV1_HS_ADDR) 	///../ucode/register.h
#define L_STV1_HE_ADDR 0x1428 	///../ucode/register.h
#define P_L_STV1_HE_ADDR 		CBUS_REG_ADDR(L_STV1_HE_ADDR) 	///../ucode/register.h
#define L_STV1_VS_ADDR 0x1429 	///../ucode/register.h
#define P_L_STV1_VS_ADDR 		CBUS_REG_ADDR(L_STV1_VS_ADDR) 	///../ucode/register.h
#define L_STV1_VE_ADDR 0x142a 	///../ucode/register.h
#define P_L_STV1_VE_ADDR 		CBUS_REG_ADDR(L_STV1_VE_ADDR) 	///../ucode/register.h
#define L_STV2_HS_ADDR 0x142b 	///../ucode/register.h
#define P_L_STV2_HS_ADDR 		CBUS_REG_ADDR(L_STV2_HS_ADDR) 	///../ucode/register.h
#define L_STV2_HE_ADDR 0x142c 	///../ucode/register.h
#define P_L_STV2_HE_ADDR 		CBUS_REG_ADDR(L_STV2_HE_ADDR) 	///../ucode/register.h
#define L_STV2_VS_ADDR 0x142d 	///../ucode/register.h
#define P_L_STV2_VS_ADDR 		CBUS_REG_ADDR(L_STV2_VS_ADDR) 	///../ucode/register.h
#define L_STV2_VE_ADDR 0x142e 	///../ucode/register.h
#define P_L_STV2_VE_ADDR 		CBUS_REG_ADDR(L_STV2_VE_ADDR) 	///../ucode/register.h
#define L_OEV1_HS_ADDR 0x142f 	///../ucode/register.h
#define P_L_OEV1_HS_ADDR 		CBUS_REG_ADDR(L_OEV1_HS_ADDR) 	///../ucode/register.h
#define L_OEV1_HE_ADDR 0x1430 	///../ucode/register.h
#define P_L_OEV1_HE_ADDR 		CBUS_REG_ADDR(L_OEV1_HE_ADDR) 	///../ucode/register.h
#define L_OEV1_VS_ADDR 0x1431 	///../ucode/register.h
#define P_L_OEV1_VS_ADDR 		CBUS_REG_ADDR(L_OEV1_VS_ADDR) 	///../ucode/register.h
#define L_OEV1_VE_ADDR 0x1432 	///../ucode/register.h
#define P_L_OEV1_VE_ADDR 		CBUS_REG_ADDR(L_OEV1_VE_ADDR) 	///../ucode/register.h
#define L_OEV2_HS_ADDR 0x1433 	///../ucode/register.h
#define P_L_OEV2_HS_ADDR 		CBUS_REG_ADDR(L_OEV2_HS_ADDR) 	///../ucode/register.h
#define L_OEV2_HE_ADDR 0x1434 	///../ucode/register.h
#define P_L_OEV2_HE_ADDR 		CBUS_REG_ADDR(L_OEV2_HE_ADDR) 	///../ucode/register.h
#define L_OEV2_VS_ADDR 0x1435 	///../ucode/register.h
#define P_L_OEV2_VS_ADDR 		CBUS_REG_ADDR(L_OEV2_VS_ADDR) 	///../ucode/register.h
#define L_OEV2_VE_ADDR 0x1436 	///../ucode/register.h
#define P_L_OEV2_VE_ADDR 		CBUS_REG_ADDR(L_OEV2_VE_ADDR) 	///../ucode/register.h
#define L_OEV3_HS_ADDR 0x1437 	///../ucode/register.h
#define P_L_OEV3_HS_ADDR 		CBUS_REG_ADDR(L_OEV3_HS_ADDR) 	///../ucode/register.h
#define L_OEV3_HE_ADDR 0x1438 	///../ucode/register.h
#define P_L_OEV3_HE_ADDR 		CBUS_REG_ADDR(L_OEV3_HE_ADDR) 	///../ucode/register.h
#define L_OEV3_VS_ADDR 0x1439 	///../ucode/register.h
#define P_L_OEV3_VS_ADDR 		CBUS_REG_ADDR(L_OEV3_VS_ADDR) 	///../ucode/register.h
#define L_OEV3_VE_ADDR 0x143a 	///../ucode/register.h
#define P_L_OEV3_VE_ADDR 		CBUS_REG_ADDR(L_OEV3_VE_ADDR) 	///../ucode/register.h
#define L_LCD_PWR_ADDR 0x143b 	///../ucode/register.h
#define P_L_LCD_PWR_ADDR 		CBUS_REG_ADDR(L_LCD_PWR_ADDR) 	///../ucode/register.h
#define L_LCD_PWM0_LO_ADDR 0x143c 	///../ucode/register.h
#define P_L_LCD_PWM0_LO_ADDR 		CBUS_REG_ADDR(L_LCD_PWM0_LO_ADDR) 	///../ucode/register.h
#define L_LCD_PWM0_HI_ADDR 0x143d 	///../ucode/register.h
#define P_L_LCD_PWM0_HI_ADDR 		CBUS_REG_ADDR(L_LCD_PWM0_HI_ADDR) 	///../ucode/register.h
#define L_LCD_PWM1_LO_ADDR 0x143e 	///../ucode/register.h
#define P_L_LCD_PWM1_LO_ADDR 		CBUS_REG_ADDR(L_LCD_PWM1_LO_ADDR) 	///../ucode/register.h
#define L_LCD_PWM1_HI_ADDR 0x143f 	///../ucode/register.h
#define P_L_LCD_PWM1_HI_ADDR 		CBUS_REG_ADDR(L_LCD_PWM1_HI_ADDR) 	///../ucode/register.h
#define L_INV_CNT_ADDR 0x1440 	///../ucode/register.h
#define P_L_INV_CNT_ADDR 		CBUS_REG_ADDR(L_INV_CNT_ADDR) 	///../ucode/register.h
#define L_TCON_MISC_SEL_ADDR 0x1441 	///../ucode/register.h
#define P_L_TCON_MISC_SEL_ADDR 		CBUS_REG_ADDR(L_TCON_MISC_SEL_ADDR) 	///../ucode/register.h
#define L_DUAL_PORT_CNTL_ADDR 0x1442 	///../ucode/register.h
#define P_L_DUAL_PORT_CNTL_ADDR 		CBUS_REG_ADDR(L_DUAL_PORT_CNTL_ADDR) 	///../ucode/register.h
#define L_TCON_DOUBLE_CTL 0x1449 	///../ucode/register.h
#define P_L_TCON_DOUBLE_CTL 		CBUS_REG_ADDR(L_TCON_DOUBLE_CTL) 	///../ucode/register.h
#define L_TCON_PATTERN_HI 0x144a 	///../ucode/register.h
#define P_L_TCON_PATTERN_HI 		CBUS_REG_ADDR(L_TCON_PATTERN_HI) 	///../ucode/register.h
#define L_TCON_PATTERN_LO 0x144b 	///../ucode/register.h
#define P_L_TCON_PATTERN_LO 		CBUS_REG_ADDR(L_TCON_PATTERN_LO) 	///../ucode/register.h
#define L_DE_HS_ADDR 0x1451 	///../ucode/register.h
#define P_L_DE_HS_ADDR 		CBUS_REG_ADDR(L_DE_HS_ADDR) 	///../ucode/register.h
#define L_DE_HE_ADDR 0x1452 	///../ucode/register.h
#define P_L_DE_HE_ADDR 		CBUS_REG_ADDR(L_DE_HE_ADDR) 	///../ucode/register.h
#define L_DE_VS_ADDR 0x1453 	///../ucode/register.h
#define P_L_DE_VS_ADDR 		CBUS_REG_ADDR(L_DE_VS_ADDR) 	///../ucode/register.h
#define L_DE_VE_ADDR 0x1454 	///../ucode/register.h
#define P_L_DE_VE_ADDR 		CBUS_REG_ADDR(L_DE_VE_ADDR) 	///../ucode/register.h
#define L_HSYNC_HS_ADDR 0x1455 	///../ucode/register.h
#define P_L_HSYNC_HS_ADDR 		CBUS_REG_ADDR(L_HSYNC_HS_ADDR) 	///../ucode/register.h
#define L_HSYNC_HE_ADDR 0x1456 	///../ucode/register.h
#define P_L_HSYNC_HE_ADDR 		CBUS_REG_ADDR(L_HSYNC_HE_ADDR) 	///../ucode/register.h
#define L_HSYNC_VS_ADDR 0x1457 	///../ucode/register.h
#define P_L_HSYNC_VS_ADDR 		CBUS_REG_ADDR(L_HSYNC_VS_ADDR) 	///../ucode/register.h
#define L_HSYNC_VE_ADDR 0x1458 	///../ucode/register.h
#define P_L_HSYNC_VE_ADDR 		CBUS_REG_ADDR(L_HSYNC_VE_ADDR) 	///../ucode/register.h
#define L_VSYNC_HS_ADDR 0x1459 	///../ucode/register.h
#define P_L_VSYNC_HS_ADDR 		CBUS_REG_ADDR(L_VSYNC_HS_ADDR) 	///../ucode/register.h
#define L_VSYNC_HE_ADDR 0x145a 	///../ucode/register.h
#define P_L_VSYNC_HE_ADDR 		CBUS_REG_ADDR(L_VSYNC_HE_ADDR) 	///../ucode/register.h
#define L_VSYNC_VS_ADDR 0x145b 	///../ucode/register.h
#define P_L_VSYNC_VS_ADDR 		CBUS_REG_ADDR(L_VSYNC_VS_ADDR) 	///../ucode/register.h
#define L_VSYNC_VE_ADDR 0x145c 	///../ucode/register.h
#define P_L_VSYNC_VE_ADDR 		CBUS_REG_ADDR(L_VSYNC_VE_ADDR) 	///../ucode/register.h
#define L_LCD_MCU_CTL 0x145d 	///../ucode/register.h
#define P_L_LCD_MCU_CTL 		CBUS_REG_ADDR(L_LCD_MCU_CTL) 	///../ucode/register.h
#define GAMMA_CNTL_PORT 0x1480 	///../ucode/register.h
#define P_GAMMA_CNTL_PORT 		CBUS_REG_ADDR(GAMMA_CNTL_PORT) 	///../ucode/register.h
#define GAMMA_DATA_PORT 0x1481 	///../ucode/register.h
#define P_GAMMA_DATA_PORT 		CBUS_REG_ADDR(GAMMA_DATA_PORT) 	///../ucode/register.h
#define GAMMA_ADDR_PORT 0x1482 	///../ucode/register.h
#define P_GAMMA_ADDR_PORT 		CBUS_REG_ADDR(GAMMA_ADDR_PORT) 	///../ucode/register.h
#define GAMMA_VCOM_HSWITCH_ADDR 0x1483 	///../ucode/register.h
#define P_GAMMA_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(GAMMA_VCOM_HSWITCH_ADDR) 	///../ucode/register.h
#define RGB_BASE_ADDR 0x1485 	///../ucode/register.h
#define P_RGB_BASE_ADDR 		CBUS_REG_ADDR(RGB_BASE_ADDR) 	///../ucode/register.h
#define RGB_COEFF_ADDR 0x1486 	///../ucode/register.h
#define P_RGB_COEFF_ADDR 		CBUS_REG_ADDR(RGB_COEFF_ADDR) 	///../ucode/register.h
#define POL_CNTL_ADDR 0x1487 	///../ucode/register.h
#define P_POL_CNTL_ADDR 		CBUS_REG_ADDR(POL_CNTL_ADDR) 	///../ucode/register.h
#define DITH_CNTL_ADDR 0x1488 	///../ucode/register.h
#define P_DITH_CNTL_ADDR 		CBUS_REG_ADDR(DITH_CNTL_ADDR) 	///../ucode/register.h
#define STH1_HS_ADDR 0x1490 	///../ucode/register.h
#define P_STH1_HS_ADDR 		CBUS_REG_ADDR(STH1_HS_ADDR) 	///../ucode/register.h
#define STH1_HE_ADDR 0x1491 	///../ucode/register.h
#define P_STH1_HE_ADDR 		CBUS_REG_ADDR(STH1_HE_ADDR) 	///../ucode/register.h
#define STH1_VS_ADDR 0x1492 	///../ucode/register.h
#define P_STH1_VS_ADDR 		CBUS_REG_ADDR(STH1_VS_ADDR) 	///../ucode/register.h
#define STH1_VE_ADDR 0x1493 	///../ucode/register.h
#define P_STH1_VE_ADDR 		CBUS_REG_ADDR(STH1_VE_ADDR) 	///../ucode/register.h
#define STH2_HS_ADDR 0x1494 	///../ucode/register.h
#define P_STH2_HS_ADDR 		CBUS_REG_ADDR(STH2_HS_ADDR) 	///../ucode/register.h
#define STH2_HE_ADDR 0x1495 	///../ucode/register.h
#define P_STH2_HE_ADDR 		CBUS_REG_ADDR(STH2_HE_ADDR) 	///../ucode/register.h
#define STH2_VS_ADDR 0x1496 	///../ucode/register.h
#define P_STH2_VS_ADDR 		CBUS_REG_ADDR(STH2_VS_ADDR) 	///../ucode/register.h
#define STH2_VE_ADDR 0x1497 	///../ucode/register.h
#define P_STH2_VE_ADDR 		CBUS_REG_ADDR(STH2_VE_ADDR) 	///../ucode/register.h
#define OEH_HS_ADDR 0x1498 	///../ucode/register.h
#define P_OEH_HS_ADDR 		CBUS_REG_ADDR(OEH_HS_ADDR) 	///../ucode/register.h
#define OEH_HE_ADDR 0x1499 	///../ucode/register.h
#define P_OEH_HE_ADDR 		CBUS_REG_ADDR(OEH_HE_ADDR) 	///../ucode/register.h
#define OEH_VS_ADDR 0x149a 	///../ucode/register.h
#define P_OEH_VS_ADDR 		CBUS_REG_ADDR(OEH_VS_ADDR) 	///../ucode/register.h
#define OEH_VE_ADDR 0x149b 	///../ucode/register.h
#define P_OEH_VE_ADDR 		CBUS_REG_ADDR(OEH_VE_ADDR) 	///../ucode/register.h
#define VCOM_HSWITCH_ADDR 0x149c 	///../ucode/register.h
#define P_VCOM_HSWITCH_ADDR 		CBUS_REG_ADDR(VCOM_HSWITCH_ADDR) 	///../ucode/register.h
#define VCOM_VS_ADDR 0x149d 	///../ucode/register.h
#define P_VCOM_VS_ADDR 		CBUS_REG_ADDR(VCOM_VS_ADDR) 	///../ucode/register.h
#define VCOM_VE_ADDR 0x149e 	///../ucode/register.h
#define P_VCOM_VE_ADDR 		CBUS_REG_ADDR(VCOM_VE_ADDR) 	///../ucode/register.h
#define CPV1_HS_ADDR 0x149f 	///../ucode/register.h
#define P_CPV1_HS_ADDR 		CBUS_REG_ADDR(CPV1_HS_ADDR) 	///../ucode/register.h
#define CPV1_HE_ADDR 0x14a0 	///../ucode/register.h
#define P_CPV1_HE_ADDR 		CBUS_REG_ADDR(CPV1_HE_ADDR) 	///../ucode/register.h
#define CPV1_VS_ADDR 0x14a1 	///../ucode/register.h
#define P_CPV1_VS_ADDR 		CBUS_REG_ADDR(CPV1_VS_ADDR) 	///../ucode/register.h
#define CPV1_VE_ADDR 0x14a2 	///../ucode/register.h
#define P_CPV1_VE_ADDR 		CBUS_REG_ADDR(CPV1_VE_ADDR) 	///../ucode/register.h
#define CPV2_HS_ADDR 0x14a3 	///../ucode/register.h
#define P_CPV2_HS_ADDR 		CBUS_REG_ADDR(CPV2_HS_ADDR) 	///../ucode/register.h
#define CPV2_HE_ADDR 0x14a4 	///../ucode/register.h
#define P_CPV2_HE_ADDR 		CBUS_REG_ADDR(CPV2_HE_ADDR) 	///../ucode/register.h
#define CPV2_VS_ADDR 0x14a5 	///../ucode/register.h
#define P_CPV2_VS_ADDR 		CBUS_REG_ADDR(CPV2_VS_ADDR) 	///../ucode/register.h
#define CPV2_VE_ADDR 0x14a6 	///../ucode/register.h
#define P_CPV2_VE_ADDR 		CBUS_REG_ADDR(CPV2_VE_ADDR) 	///../ucode/register.h
#define STV1_HS_ADDR 0x14a7 	///../ucode/register.h
#define P_STV1_HS_ADDR 		CBUS_REG_ADDR(STV1_HS_ADDR) 	///../ucode/register.h
#define STV1_HE_ADDR 0x14a8 	///../ucode/register.h
#define P_STV1_HE_ADDR 		CBUS_REG_ADDR(STV1_HE_ADDR) 	///../ucode/register.h
#define STV1_VS_ADDR 0x14a9 	///../ucode/register.h
#define P_STV1_VS_ADDR 		CBUS_REG_ADDR(STV1_VS_ADDR) 	///../ucode/register.h
#define STV1_VE_ADDR 0x14aa 	///../ucode/register.h
#define P_STV1_VE_ADDR 		CBUS_REG_ADDR(STV1_VE_ADDR) 	///../ucode/register.h
#define STV2_HS_ADDR 0x14ab 	///../ucode/register.h
#define P_STV2_HS_ADDR 		CBUS_REG_ADDR(STV2_HS_ADDR) 	///../ucode/register.h
#define STV2_HE_ADDR 0x14ac 	///../ucode/register.h
#define P_STV2_HE_ADDR 		CBUS_REG_ADDR(STV2_HE_ADDR) 	///../ucode/register.h
#define STV2_VS_ADDR 0x14ad 	///../ucode/register.h
#define P_STV2_VS_ADDR 		CBUS_REG_ADDR(STV2_VS_ADDR) 	///../ucode/register.h
#define STV2_VE_ADDR 0x14ae 	///../ucode/register.h
#define P_STV2_VE_ADDR 		CBUS_REG_ADDR(STV2_VE_ADDR) 	///../ucode/register.h
#define OEV1_HS_ADDR 0x14af 	///../ucode/register.h
#define P_OEV1_HS_ADDR 		CBUS_REG_ADDR(OEV1_HS_ADDR) 	///../ucode/register.h
#define OEV1_HE_ADDR 0x14b0 	///../ucode/register.h
#define P_OEV1_HE_ADDR 		CBUS_REG_ADDR(OEV1_HE_ADDR) 	///../ucode/register.h
#define OEV1_VS_ADDR 0x14b1 	///../ucode/register.h
#define P_OEV1_VS_ADDR 		CBUS_REG_ADDR(OEV1_VS_ADDR) 	///../ucode/register.h
#define OEV1_VE_ADDR 0x14b2 	///../ucode/register.h
#define P_OEV1_VE_ADDR 		CBUS_REG_ADDR(OEV1_VE_ADDR) 	///../ucode/register.h
#define OEV2_HS_ADDR 0x14b3 	///../ucode/register.h
#define P_OEV2_HS_ADDR 		CBUS_REG_ADDR(OEV2_HS_ADDR) 	///../ucode/register.h
#define OEV2_HE_ADDR 0x14b4 	///../ucode/register.h
#define P_OEV2_HE_ADDR 		CBUS_REG_ADDR(OEV2_HE_ADDR) 	///../ucode/register.h
#define OEV2_VS_ADDR 0x14b5 	///../ucode/register.h
#define P_OEV2_VS_ADDR 		CBUS_REG_ADDR(OEV2_VS_ADDR) 	///../ucode/register.h
#define OEV2_VE_ADDR 0x14b6 	///../ucode/register.h
#define P_OEV2_VE_ADDR 		CBUS_REG_ADDR(OEV2_VE_ADDR) 	///../ucode/register.h
#define OEV3_HS_ADDR 0x14b7 	///../ucode/register.h
#define P_OEV3_HS_ADDR 		CBUS_REG_ADDR(OEV3_HS_ADDR) 	///../ucode/register.h
#define OEV3_HE_ADDR 0x14b8 	///../ucode/register.h
#define P_OEV3_HE_ADDR 		CBUS_REG_ADDR(OEV3_HE_ADDR) 	///../ucode/register.h
#define OEV3_VS_ADDR 0x14b9 	///../ucode/register.h
#define P_OEV3_VS_ADDR 		CBUS_REG_ADDR(OEV3_VS_ADDR) 	///../ucode/register.h
#define OEV3_VE_ADDR 0x14ba 	///../ucode/register.h
#define P_OEV3_VE_ADDR 		CBUS_REG_ADDR(OEV3_VE_ADDR) 	///../ucode/register.h
#define LCD_PWR_ADDR 0x14bb 	///../ucode/register.h
#define P_LCD_PWR_ADDR 		CBUS_REG_ADDR(LCD_PWR_ADDR) 	///../ucode/register.h
#define LCD_PWM0_LO_ADDR 0x14bc 	///../ucode/register.h
#define P_LCD_PWM0_LO_ADDR 		CBUS_REG_ADDR(LCD_PWM0_LO_ADDR) 	///../ucode/register.h
#define LCD_PWM0_HI_ADDR 0x14bd 	///../ucode/register.h
#define P_LCD_PWM0_HI_ADDR 		CBUS_REG_ADDR(LCD_PWM0_HI_ADDR) 	///../ucode/register.h
#define LCD_PWM1_LO_ADDR 0x14be 	///../ucode/register.h
#define P_LCD_PWM1_LO_ADDR 		CBUS_REG_ADDR(LCD_PWM1_LO_ADDR) 	///../ucode/register.h
#define LCD_PWM1_HI_ADDR 0x14bf 	///../ucode/register.h
#define P_LCD_PWM1_HI_ADDR 		CBUS_REG_ADDR(LCD_PWM1_HI_ADDR) 	///../ucode/register.h
#define INV_CNT_ADDR 0x14c0 	///../ucode/register.h
#define P_INV_CNT_ADDR 		CBUS_REG_ADDR(INV_CNT_ADDR) 	///../ucode/register.h
#define TCON_MISC_SEL_ADDR 0x14c1 	///../ucode/register.h
#define P_TCON_MISC_SEL_ADDR 		CBUS_REG_ADDR(TCON_MISC_SEL_ADDR) 	///../ucode/register.h
#define DUAL_PORT_CNTL_ADDR 0x14c2 	///../ucode/register.h
#define P_DUAL_PORT_CNTL_ADDR 		CBUS_REG_ADDR(DUAL_PORT_CNTL_ADDR) 	///../ucode/register.h
#define MLVDS_CONTROL 0x14c3 	///../ucode/register.h
#define P_MLVDS_CONTROL 		CBUS_REG_ADDR(MLVDS_CONTROL) 	///../ucode/register.h
#define MLVDS_RESET_PATTERN_HI 0x14c4 	///../ucode/register.h
#define P_MLVDS_RESET_PATTERN_HI 		CBUS_REG_ADDR(MLVDS_RESET_PATTERN_HI) 	///../ucode/register.h
#define MLVDS_RESET_PATTERN_LO 0x14c5 	///../ucode/register.h
#define P_MLVDS_RESET_PATTERN_LO 		CBUS_REG_ADDR(MLVDS_RESET_PATTERN_LO) 	///../ucode/register.h
#define MLVDS_RESET_PATTERN_EXT 0x14c6 	///../ucode/register.h
#define P_MLVDS_RESET_PATTERN_EXT 		CBUS_REG_ADDR(MLVDS_RESET_PATTERN_EXT) 	///../ucode/register.h
#define MLVDS_CONFIG_HI 0x14c7 	///../ucode/register.h
#define P_MLVDS_CONFIG_HI 		CBUS_REG_ADDR(MLVDS_CONFIG_HI) 	///../ucode/register.h
#define MLVDS_CONFIG_LO 0x14c8 	///../ucode/register.h
#define P_MLVDS_CONFIG_LO 		CBUS_REG_ADDR(MLVDS_CONFIG_LO) 	///../ucode/register.h
#define TCON_DOUBLE_CTL 0x14c9 	///../ucode/register.h
#define P_TCON_DOUBLE_CTL 		CBUS_REG_ADDR(TCON_DOUBLE_CTL) 	///../ucode/register.h
#define TCON_PATTERN_HI 0x14ca 	///../ucode/register.h
#define P_TCON_PATTERN_HI 		CBUS_REG_ADDR(TCON_PATTERN_HI) 	///../ucode/register.h
#define TCON_PATTERN_LO 0x14cb 	///../ucode/register.h
#define P_TCON_PATTERN_LO 		CBUS_REG_ADDR(TCON_PATTERN_LO) 	///../ucode/register.h
#define TCON_CONTROL_HI 0x14cc 	///../ucode/register.h
#define P_TCON_CONTROL_HI 		CBUS_REG_ADDR(TCON_CONTROL_HI) 	///../ucode/register.h
#define TCON_CONTROL_LO 0x14cd 	///../ucode/register.h
#define P_TCON_CONTROL_LO 		CBUS_REG_ADDR(TCON_CONTROL_LO) 	///../ucode/register.h
#define LVDS_BLANK_DATA_HI 0x14ce 	///../ucode/register.h
#define P_LVDS_BLANK_DATA_HI 		CBUS_REG_ADDR(LVDS_BLANK_DATA_HI) 	///../ucode/register.h
#define LVDS_BLANK_DATA_LO 0x14cf 	///../ucode/register.h
#define P_LVDS_BLANK_DATA_LO 		CBUS_REG_ADDR(LVDS_BLANK_DATA_LO) 	///../ucode/register.h
#define LVDS_PACK_CNTL_ADDR 0x14d0 	///../ucode/register.h
#define P_LVDS_PACK_CNTL_ADDR 		CBUS_REG_ADDR(LVDS_PACK_CNTL_ADDR) 	///../ucode/register.h
#define DE_HS_ADDR 0x14d1 	///../ucode/register.h
#define P_DE_HS_ADDR 		CBUS_REG_ADDR(DE_HS_ADDR) 	///../ucode/register.h
#define DE_HE_ADDR 0x14d2 	///../ucode/register.h
#define P_DE_HE_ADDR 		CBUS_REG_ADDR(DE_HE_ADDR) 	///../ucode/register.h
#define DE_VS_ADDR 0x14d3 	///../ucode/register.h
#define P_DE_VS_ADDR 		CBUS_REG_ADDR(DE_VS_ADDR) 	///../ucode/register.h
#define DE_VE_ADDR 0x14d4 	///../ucode/register.h
#define P_DE_VE_ADDR 		CBUS_REG_ADDR(DE_VE_ADDR) 	///../ucode/register.h
#define HSYNC_HS_ADDR 0x14d5 	///../ucode/register.h
#define P_HSYNC_HS_ADDR 		CBUS_REG_ADDR(HSYNC_HS_ADDR) 	///../ucode/register.h
#define HSYNC_HE_ADDR 0x14d6 	///../ucode/register.h
#define P_HSYNC_HE_ADDR 		CBUS_REG_ADDR(HSYNC_HE_ADDR) 	///../ucode/register.h
#define HSYNC_VS_ADDR 0x14d7 	///../ucode/register.h
#define P_HSYNC_VS_ADDR 		CBUS_REG_ADDR(HSYNC_VS_ADDR) 	///../ucode/register.h
#define HSYNC_VE_ADDR 0x14d8 	///../ucode/register.h
#define P_HSYNC_VE_ADDR 		CBUS_REG_ADDR(HSYNC_VE_ADDR) 	///../ucode/register.h
#define VSYNC_HS_ADDR 0x14d9 	///../ucode/register.h
#define P_VSYNC_HS_ADDR 		CBUS_REG_ADDR(VSYNC_HS_ADDR) 	///../ucode/register.h
#define VSYNC_HE_ADDR 0x14da 	///../ucode/register.h
#define P_VSYNC_HE_ADDR 		CBUS_REG_ADDR(VSYNC_HE_ADDR) 	///../ucode/register.h
#define VSYNC_VS_ADDR 0x14db 	///../ucode/register.h
#define P_VSYNC_VS_ADDR 		CBUS_REG_ADDR(VSYNC_VS_ADDR) 	///../ucode/register.h
#define VSYNC_VE_ADDR 0x14dc 	///../ucode/register.h
#define P_VSYNC_VE_ADDR 		CBUS_REG_ADDR(VSYNC_VE_ADDR) 	///../ucode/register.h
#define LCD_MCU_CTL 0x14dd 	///../ucode/register.h
#define P_LCD_MCU_CTL 		CBUS_REG_ADDR(LCD_MCU_CTL) 	///../ucode/register.h
#define LCD_MCU_DATA_0 0x14de 	///../ucode/register.h
#define P_LCD_MCU_DATA_0 		CBUS_REG_ADDR(LCD_MCU_DATA_0) 	///../ucode/register.h
#define LCD_MCU_DATA_1 0x14df 	///../ucode/register.h
#define P_LCD_MCU_DATA_1 		CBUS_REG_ADDR(LCD_MCU_DATA_1) 	///../ucode/register.h
#define LVDS_GEN_CNTL 0x14e0 	///../ucode/register.h
#define P_LVDS_GEN_CNTL 		CBUS_REG_ADDR(LVDS_GEN_CNTL) 	///../ucode/register.h
#define LVDS_PHY_CNTL0 0x14e1 	///../ucode/register.h
#define P_LVDS_PHY_CNTL0 		CBUS_REG_ADDR(LVDS_PHY_CNTL0) 	///../ucode/register.h
#define LVDS_PHY_CNTL1 0x14e2 	///../ucode/register.h
#define P_LVDS_PHY_CNTL1 		CBUS_REG_ADDR(LVDS_PHY_CNTL1) 	///../ucode/register.h
#define LVDS_PHY_CNTL2 0x14e3 	///../ucode/register.h
#define P_LVDS_PHY_CNTL2 		CBUS_REG_ADDR(LVDS_PHY_CNTL2) 	///../ucode/register.h
#define LVDS_PHY_CNTL3 0x14e4 	///../ucode/register.h
#define P_LVDS_PHY_CNTL3 		CBUS_REG_ADDR(LVDS_PHY_CNTL3) 	///../ucode/register.h
#define LVDS_PHY_CNTL4 0x14e5 	///../ucode/register.h
#define P_LVDS_PHY_CNTL4 		CBUS_REG_ADDR(LVDS_PHY_CNTL4) 	///../ucode/register.h
#define LVDS_PHY_CNTL5 0x14e6 	///../ucode/register.h
#define P_LVDS_PHY_CNTL5 		CBUS_REG_ADDR(LVDS_PHY_CNTL5) 	///../ucode/register.h
#define LVDS_SRG_TEST 0x14e8 	///../ucode/register.h
#define P_LVDS_SRG_TEST 		CBUS_REG_ADDR(LVDS_SRG_TEST) 	///../ucode/register.h
#define LVDS_BIST_MUX0 0x14e9 	///../ucode/register.h
#define P_LVDS_BIST_MUX0 		CBUS_REG_ADDR(LVDS_BIST_MUX0) 	///../ucode/register.h
#define LVDS_BIST_MUX1 0x14ea 	///../ucode/register.h
#define P_LVDS_BIST_MUX1 		CBUS_REG_ADDR(LVDS_BIST_MUX1) 	///../ucode/register.h
#define LVDS_BIST_FIXED0 0x14eb 	///../ucode/register.h
#define P_LVDS_BIST_FIXED0 		CBUS_REG_ADDR(LVDS_BIST_FIXED0) 	///../ucode/register.h
#define LVDS_BIST_FIXED1 0x14ec 	///../ucode/register.h
#define P_LVDS_BIST_FIXED1 		CBUS_REG_ADDR(LVDS_BIST_FIXED1) 	///../ucode/register.h
#define LVDS_BIST_CNTL0 0x14ed 	///../ucode/register.h
#define P_LVDS_BIST_CNTL0 		CBUS_REG_ADDR(LVDS_BIST_CNTL0) 	///../ucode/register.h
#define LVDS_CLKB_CLKA 0x14ee 	///../ucode/register.h
#define P_LVDS_CLKB_CLKA 		CBUS_REG_ADDR(LVDS_CLKB_CLKA) 	///../ucode/register.h
#define LVDS_PHY_CLK_CNTL 0x14ef 	///../ucode/register.h
#define P_LVDS_PHY_CLK_CNTL 		CBUS_REG_ADDR(LVDS_PHY_CLK_CNTL) 	///../ucode/register.h
#define LVDS_SER_EN 0x14f0 	///../ucode/register.h
#define P_LVDS_SER_EN 		CBUS_REG_ADDR(LVDS_SER_EN) 	///../ucode/register.h
#define LVDS_PHY_CNTL6 0x14f1 	///../ucode/register.h
#define P_LVDS_PHY_CNTL6 		CBUS_REG_ADDR(LVDS_PHY_CNTL6) 	///../ucode/register.h
#define LVDS_PHY_CNTL7 0x14f2 	///../ucode/register.h
#define P_LVDS_PHY_CNTL7 		CBUS_REG_ADDR(LVDS_PHY_CNTL7) 	///../ucode/register.h
#define LVDS_PHY_CNTL8 0x14f3 	///../ucode/register.h
#define P_LVDS_PHY_CNTL8 		CBUS_REG_ADDR(LVDS_PHY_CNTL8) 	///../ucode/register.h
#define MLVDS_CLK_CTL_HI 0x14f4 	///../ucode/register.h
#define P_MLVDS_CLK_CTL_HI 		CBUS_REG_ADDR(MLVDS_CLK_CTL_HI) 	///../ucode/register.h
#define MLVDS_CLK_CTL_LO 0x14f5 	///../ucode/register.h
#define P_MLVDS_CLK_CTL_LO 		CBUS_REG_ADDR(MLVDS_CLK_CTL_LO) 	///../ucode/register.h
#define MLVDS_DUAL_GATE_WR_START 0x14f6 	///../ucode/register.h
#define P_MLVDS_DUAL_GATE_WR_START 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_WR_START) 	///../ucode/register.h
#define MLVDS_DUAL_GATE_WR_END 0x14f7 	///../ucode/register.h
#define P_MLVDS_DUAL_GATE_WR_END 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_WR_END) 	///../ucode/register.h
#define MLVDS_DUAL_GATE_RD_START 0x14f8 	///../ucode/register.h
#define P_MLVDS_DUAL_GATE_RD_START 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_RD_START) 	///../ucode/register.h
#define MLVDS_DUAL_GATE_RD_END 0x14f9 	///../ucode/register.h
#define P_MLVDS_DUAL_GATE_RD_END 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_RD_END) 	///../ucode/register.h
#define MLVDS_SECOND_RESET_CTL 0x14fa 	///../ucode/register.h
#define P_MLVDS_SECOND_RESET_CTL 		CBUS_REG_ADDR(MLVDS_SECOND_RESET_CTL) 	///../ucode/register.h
#define MLVDS_DUAL_GATE_CTL_HI 0x14fb 	///../ucode/register.h
#define P_MLVDS_DUAL_GATE_CTL_HI 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_CTL_HI) 	///../ucode/register.h
#define MLVDS_DUAL_GATE_CTL_LO 0x14fc 	///../ucode/register.h
#define P_MLVDS_DUAL_GATE_CTL_LO 		CBUS_REG_ADDR(MLVDS_DUAL_GATE_CTL_LO) 	///../ucode/register.h
#define MLVDS_RESET_CONFIG_HI 0x14fd 	///../ucode/register.h
#define P_MLVDS_RESET_CONFIG_HI 		CBUS_REG_ADDR(MLVDS_RESET_CONFIG_HI) 	///../ucode/register.h
#define MLVDS_RESET_CONFIG_LO 0x14fe 	///../ucode/register.h
#define P_MLVDS_RESET_CONFIG_LO 		CBUS_REG_ADDR(MLVDS_RESET_CONFIG_LO) 	///../ucode/register.h
#define VPU_OSD1_MMC_CTRL 0x2701 	///../ucode/register.h
#define P_VPU_OSD1_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD1_MMC_CTRL) 	///../ucode/register.h
#define VPU_OSD2_MMC_CTRL 0x2702 	///../ucode/register.h
#define P_VPU_OSD2_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD2_MMC_CTRL) 	///../ucode/register.h
#define VPU_VD1_MMC_CTRL 0x2703 	///../ucode/register.h
#define P_VPU_VD1_MMC_CTRL 		CBUS_REG_ADDR(VPU_VD1_MMC_CTRL) 	///../ucode/register.h
#define VPU_VD2_MMC_CTRL 0x2704 	///../ucode/register.h
#define P_VPU_VD2_MMC_CTRL 		CBUS_REG_ADDR(VPU_VD2_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_IF1_MMC_CTRL 0x2705 	///../ucode/register.h
#define P_VPU_DI_IF1_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_IF1_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_MEM_MMC_CTRL 0x2706 	///../ucode/register.h
#define P_VPU_DI_MEM_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_MEM_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_INP_MMC_CTRL 0x2707 	///../ucode/register.h
#define P_VPU_DI_INP_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_INP_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_MTNRD_MMC_CTRL 0x2708 	///../ucode/register.h
#define P_VPU_DI_MTNRD_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_MTNRD_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_CHAN2_MMC_CTRL 0x2709 	///../ucode/register.h
#define P_VPU_DI_CHAN2_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_CHAN2_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_MTNWR_MMC_CTRL 0x270a 	///../ucode/register.h
#define P_VPU_DI_MTNWR_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_MTNWR_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_NRWR_MMC_CTRL 0x270b 	///../ucode/register.h
#define P_VPU_DI_NRWR_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_NRWR_MMC_CTRL) 	///../ucode/register.h
#define VPU_DI_DIWR_MMC_CTRL 0x270c 	///../ucode/register.h
#define P_VPU_DI_DIWR_MMC_CTRL 		CBUS_REG_ADDR(VPU_DI_DIWR_MMC_CTRL) 	///../ucode/register.h
#define VPU_VDIN0_MMC_CTRL 0x270d 	///../ucode/register.h
#define P_VPU_VDIN0_MMC_CTRL 		CBUS_REG_ADDR(VPU_VDIN0_MMC_CTRL) 	///../ucode/register.h
#define VPU_VDIN1_MMC_CTRL 0x270e 	///../ucode/register.h
#define P_VPU_VDIN1_MMC_CTRL 		CBUS_REG_ADDR(VPU_VDIN1_MMC_CTRL) 	///../ucode/register.h
#define VPU_BT656_MMC_CTRL 0x270f 	///../ucode/register.h
#define P_VPU_BT656_MMC_CTRL 		CBUS_REG_ADDR(VPU_BT656_MMC_CTRL) 	///../ucode/register.h
#define VPU_TVD3D_MMC_CTRL 0x2710 	///../ucode/register.h
#define P_VPU_TVD3D_MMC_CTRL 		CBUS_REG_ADDR(VPU_TVD3D_MMC_CTRL) 	///../ucode/register.h
#define VPU_TVDVBI_MMC_CTRL 0x2711 	///../ucode/register.h
#define P_VPU_TVDVBI_MMC_CTRL 		CBUS_REG_ADDR(VPU_TVDVBI_MMC_CTRL) 	///../ucode/register.h
#define VPU_TVDVBI_VSLATCH_ADDR 0x2712 	///../ucode/register.h
#define P_VPU_TVDVBI_VSLATCH_ADDR 		CBUS_REG_ADDR(VPU_TVDVBI_VSLATCH_ADDR) 	///../ucode/register.h
#define VPU_TVDVBI_WRRSP_ADDR 0x2713 	///../ucode/register.h
#define P_VPU_TVDVBI_WRRSP_ADDR 		CBUS_REG_ADDR(VPU_TVDVBI_WRRSP_ADDR) 	///../ucode/register.h
#define VPU_VDIN_PRE_ARB_CTRL 0x2714 	///../ucode/register.h
#define P_VPU_VDIN_PRE_ARB_CTRL 		CBUS_REG_ADDR(VPU_VDIN_PRE_ARB_CTRL) 	///../ucode/register.h
#define VPU_VDISP_PRE_ARB_CTRL 0x2715 	///../ucode/register.h
#define P_VPU_VDISP_PRE_ARB_CTRL 		CBUS_REG_ADDR(VPU_VDISP_PRE_ARB_CTRL) 	///../ucode/register.h
#define VPU_VPUARB2_PRE_ARB_CTRL 0x2716 	///../ucode/register.h
#define P_VPU_VPUARB2_PRE_ARB_CTRL 		CBUS_REG_ADDR(VPU_VPUARB2_PRE_ARB_CTRL) 	///../ucode/register.h
#define VPU_OSD3_MMC_CTRL 0x2717 	///../ucode/register.h
#define P_VPU_OSD3_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD3_MMC_CTRL) 	///../ucode/register.h
#define VPU_OSD4_MMC_CTRL 0x2718 	///../ucode/register.h
#define P_VPU_OSD4_MMC_CTRL 		CBUS_REG_ADDR(VPU_OSD4_MMC_CTRL) 	///../ucode/register.h
#define VPU_VD3_MMC_CTRL 0x2719 	///../ucode/register.h
#define P_VPU_VD3_MMC_CTRL 		CBUS_REG_ADDR(VPU_VD3_MMC_CTRL) 	///../ucode/register.h
#define VPU_VIU_VENC_MUX_CTRL 0x271a 	///../ucode/register.h
#define P_VPU_VIU_VENC_MUX_CTRL 		CBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL) 	///../ucode/register.h
#define VPU_HDMI_SETTING 0x271b 	///../ucode/register.h
#define P_VPU_HDMI_SETTING 		CBUS_REG_ADDR(VPU_HDMI_SETTING) 	///../ucode/register.h
#define ENCI_INFO_READ 0x271c 	///../ucode/register.h
#define P_ENCI_INFO_READ 		CBUS_REG_ADDR(ENCI_INFO_READ) 	///../ucode/register.h
#define ENCP_INFO_READ 0x271d 	///../ucode/register.h
#define P_ENCP_INFO_READ 		CBUS_REG_ADDR(ENCP_INFO_READ) 	///../ucode/register.h
#define ENCT_INFO_READ 0x271e 	///../ucode/register.h
#define P_ENCT_INFO_READ 		CBUS_REG_ADDR(ENCT_INFO_READ) 	///../ucode/register.h
#define ENCL_INFO_READ 0x271f 	///../ucode/register.h
#define P_ENCL_INFO_READ 		CBUS_REG_ADDR(ENCL_INFO_READ) 	///../ucode/register.h
#define AUDIO_COP_CTL2 0x2f01 	///../ucode/register.h
#define P_AUDIO_COP_CTL2 		CBUS_REG_ADDR(AUDIO_COP_CTL2) 	///../ucode/register.h
#define OPERAND_M_CTL 0x2f02 	///../ucode/register.h
#define P_OPERAND_M_CTL 		CBUS_REG_ADDR(OPERAND_M_CTL) 	///../ucode/register.h
#define OPERAND1_ADDR 0x2f03 	///../ucode/register.h
#define P_OPERAND1_ADDR 		CBUS_REG_ADDR(OPERAND1_ADDR) 	///../ucode/register.h
#define OPERAND2_ADDR 0x2f04 	///../ucode/register.h
#define P_OPERAND2_ADDR 		CBUS_REG_ADDR(OPERAND2_ADDR) 	///../ucode/register.h
#define RESULT_M_CTL 0x2f05 	///../ucode/register.h
#define P_RESULT_M_CTL 		CBUS_REG_ADDR(RESULT_M_CTL) 	///../ucode/register.h
#define RESULT1_ADDR 0x2f06 	///../ucode/register.h
#define P_RESULT1_ADDR 		CBUS_REG_ADDR(RESULT1_ADDR) 	///../ucode/register.h
#define RESULT2_ADDR 0x2f07 	///../ucode/register.h
#define P_RESULT2_ADDR 		CBUS_REG_ADDR(RESULT2_ADDR) 	///../ucode/register.h
#define ADD_SHFT_CTL 0x2f08 	///../ucode/register.h
#define P_ADD_SHFT_CTL 		CBUS_REG_ADDR(ADD_SHFT_CTL) 	///../ucode/register.h
#define OPERAND_ONE_H 0x2f09 	///../ucode/register.h
#define P_OPERAND_ONE_H 		CBUS_REG_ADDR(OPERAND_ONE_H) 	///../ucode/register.h
#define OPERAND_ONE_L 0x2f0a 	///../ucode/register.h
#define P_OPERAND_ONE_L 		CBUS_REG_ADDR(OPERAND_ONE_L) 	///../ucode/register.h
#define OPERAND_TWO_H 0x2f0b 	///../ucode/register.h
#define P_OPERAND_TWO_H 		CBUS_REG_ADDR(OPERAND_TWO_H) 	///../ucode/register.h
#define OPERAND_TWO_L 0x2f0c 	///../ucode/register.h
#define P_OPERAND_TWO_L 		CBUS_REG_ADDR(OPERAND_TWO_L) 	///../ucode/register.h
#define RESULT_H 0x2f0d 	///../ucode/register.h
#define P_RESULT_H 		CBUS_REG_ADDR(RESULT_H) 	///../ucode/register.h
#define RESULT_M 0x2f0e 	///../ucode/register.h
#define P_RESULT_M 		CBUS_REG_ADDR(RESULT_M) 	///../ucode/register.h
#define RESULT_L 0x2f0f 	///../ucode/register.h
#define P_RESULT_L 		CBUS_REG_ADDR(RESULT_L) 	///../ucode/register.h
#define WMEM_R_PTR 0x2f10 	///../ucode/register.h
#define P_WMEM_R_PTR 		CBUS_REG_ADDR(WMEM_R_PTR) 	///../ucode/register.h
#define WMEM_W_PTR 0x2f11 	///../ucode/register.h
#define P_WMEM_W_PTR 		CBUS_REG_ADDR(WMEM_W_PTR) 	///../ucode/register.h
#define AUDIO_LAYER 0x2f20 	///../ucode/register.h
#define P_AUDIO_LAYER 		CBUS_REG_ADDR(AUDIO_LAYER) 	///../ucode/register.h
#define AC3_DECODING 0x2f21 	///../ucode/register.h
#define P_AC3_DECODING 		CBUS_REG_ADDR(AC3_DECODING) 	///../ucode/register.h
#define AC3_DYNAMIC 0x2f22 	///../ucode/register.h
#define P_AC3_DYNAMIC 		CBUS_REG_ADDR(AC3_DYNAMIC) 	///../ucode/register.h
#define AC3_MELODY 0x2f23 	///../ucode/register.h
#define P_AC3_MELODY 		CBUS_REG_ADDR(AC3_MELODY) 	///../ucode/register.h
#define AC3_VOCAL 0x2f24 	///../ucode/register.h
#define P_AC3_VOCAL 		CBUS_REG_ADDR(AC3_VOCAL) 	///../ucode/register.h
#define ASSIST_AMR_SCRATCH0 0x1f4f 	///../ucode/register.h
#define P_ASSIST_AMR_SCRATCH0 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH0) 	///../ucode/register.h
#define ASSIST_AMR_SCRATCH1 0x1f50 	///../ucode/register.h
#define P_ASSIST_AMR_SCRATCH1 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH1) 	///../ucode/register.h
#define ASSIST_AMR_SCRATCH2 0x1f51 	///../ucode/register.h
#define P_ASSIST_AMR_SCRATCH2 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH2) 	///../ucode/register.h
#define ASSIST_AMR_SCRATCH3 0x1f52 	///../ucode/register.h
#define P_ASSIST_AMR_SCRATCH3 		CBUS_REG_ADDR(ASSIST_AMR_SCRATCH3) 	///../ucode/register.h
#define ASSIST_HW_REV 0x1f53 	///../ucode/register.h
#define P_ASSIST_HW_REV 		CBUS_REG_ADDR(ASSIST_HW_REV) 	///../ucode/register.h
#define ASSIST_POR_CONFIG 0x1f55 	///../ucode/register.h
#define P_ASSIST_POR_CONFIG 		CBUS_REG_ADDR(ASSIST_POR_CONFIG) 	///../ucode/register.h
#define ASSIST_SPARE16_REG1 0x1f56 	///../ucode/register.h
#define P_ASSIST_SPARE16_REG1 		CBUS_REG_ADDR(ASSIST_SPARE16_REG1) 	///../ucode/register.h
#define ASSIST_SPARE16_REG2 0x1f57 	///../ucode/register.h
#define P_ASSIST_SPARE16_REG2 		CBUS_REG_ADDR(ASSIST_SPARE16_REG2) 	///../ucode/register.h
#define ASSIST_SPARE8_REG1 0x1f58 	///../ucode/register.h
#define P_ASSIST_SPARE8_REG1 		CBUS_REG_ADDR(ASSIST_SPARE8_REG1) 	///../ucode/register.h
#define ASSIST_SPARE8_REG2 0x1f59 	///../ucode/register.h
#define P_ASSIST_SPARE8_REG2 		CBUS_REG_ADDR(ASSIST_SPARE8_REG2) 	///../ucode/register.h
#define ASSIST_SPARE8_REG3 0x1f5a 	///../ucode/register.h
#define P_ASSIST_SPARE8_REG3 		CBUS_REG_ADDR(ASSIST_SPARE8_REG3) 	///../ucode/register.h
#define AC3_CTRL_REG1 0x1f5b 	///../ucode/register.h
#define P_AC3_CTRL_REG1 		CBUS_REG_ADDR(AC3_CTRL_REG1) 	///../ucode/register.h
#define AC3_CTRL_REG2 0x1f5c 	///../ucode/register.h
#define P_AC3_CTRL_REG2 		CBUS_REG_ADDR(AC3_CTRL_REG2) 	///../ucode/register.h
#define AC3_CTRL_REG3 0x1f5d 	///../ucode/register.h
#define P_AC3_CTRL_REG3 		CBUS_REG_ADDR(AC3_CTRL_REG3) 	///../ucode/register.h
#define AC3_CTRL_REG4 0x1f5e 	///../ucode/register.h
#define P_AC3_CTRL_REG4 		CBUS_REG_ADDR(AC3_CTRL_REG4) 	///../ucode/register.h
#define ASSIST_GEN_CNTL 0x1f68 	///../ucode/register.h
#define P_ASSIST_GEN_CNTL 		CBUS_REG_ADDR(ASSIST_GEN_CNTL) 	///../ucode/register.h
#define AUDIN_SPDIF_MODE 0x2800 	///../ucode/register.h
#define P_AUDIN_SPDIF_MODE 		CBUS_REG_ADDR(AUDIN_SPDIF_MODE) 	///../ucode/register.h
#define AUDIN_SPDIF_FS_CLK_RLTN 0x2801 	///../ucode/register.h
#define P_AUDIN_SPDIF_FS_CLK_RLTN 		CBUS_REG_ADDR(AUDIN_SPDIF_FS_CLK_RLTN) 	///../ucode/register.h
#define AUDIN_SPDIF_CHNL_STS_A 0x2802 	///../ucode/register.h
#define P_AUDIN_SPDIF_CHNL_STS_A 		CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_A) 	///../ucode/register.h
#define AUDIN_SPDIF_CHNL_STS_B 0x2803 	///../ucode/register.h
#define P_AUDIN_SPDIF_CHNL_STS_B 		CBUS_REG_ADDR(AUDIN_SPDIF_CHNL_STS_B) 	///../ucode/register.h
#define AUDIN_SPDIF_MISC 0x2804 	///../ucode/register.h
#define P_AUDIN_SPDIF_MISC 		CBUS_REG_ADDR(AUDIN_SPDIF_MISC) 	///../ucode/register.h
#define AUDIN_SPDIF_NPCM_PCPD 0x2805 	///../ucode/register.h
#define P_AUDIN_SPDIF_NPCM_PCPD 		CBUS_REG_ADDR(AUDIN_SPDIF_NPCM_PCPD) 	///../ucode/register.h
#define AUDIN_SPDIF_END 0x280f 	///../ucode/register.h
#define P_AUDIN_SPDIF_END 		CBUS_REG_ADDR(AUDIN_SPDIF_END) 	///../ucode/register.h
#define AUDIN_I2SIN_CTRL 0x2810 	///../ucode/register.h
#define P_AUDIN_I2SIN_CTRL 		CBUS_REG_ADDR(AUDIN_I2SIN_CTRL) 	///../ucode/register.h
#define AUDIN_SOURCE_SEL 0x2811 	///../ucode/register.h
#define P_AUDIN_SOURCE_SEL 		CBUS_REG_ADDR(AUDIN_SOURCE_SEL) 	///../ucode/register.h
#define AUDIN_FIFO0_START 0x2820 	///../ucode/register.h
#define P_AUDIN_FIFO0_START 		CBUS_REG_ADDR(AUDIN_FIFO0_START) 	///../ucode/register.h
#define AUDIN_FIFO0_END 0x2821 	///../ucode/register.h
#define P_AUDIN_FIFO0_END 		CBUS_REG_ADDR(AUDIN_FIFO0_END) 	///../ucode/register.h
#define AUDIN_FIFO0_PTR 0x2822 	///../ucode/register.h
#define P_AUDIN_FIFO0_PTR 		CBUS_REG_ADDR(AUDIN_FIFO0_PTR) 	///../ucode/register.h
#define AUDIN_FIFO0_INTR 0x2823 	///../ucode/register.h
#define P_AUDIN_FIFO0_INTR 		CBUS_REG_ADDR(AUDIN_FIFO0_INTR) 	///../ucode/register.h
#define AUDIN_FIFO0_RDPTR 0x2824 	///../ucode/register.h
#define P_AUDIN_FIFO0_RDPTR 		CBUS_REG_ADDR(AUDIN_FIFO0_RDPTR) 	///../ucode/register.h
#define AUDIN_FIFO0_CTRL 0x2825 	///../ucode/register.h
#define P_AUDIN_FIFO0_CTRL 		CBUS_REG_ADDR(AUDIN_FIFO0_CTRL) 	///../ucode/register.h
#define AUDIN_FIFO0_CTRL1 0x2826 	///../ucode/register.h
#define P_AUDIN_FIFO0_CTRL1 		CBUS_REG_ADDR(AUDIN_FIFO0_CTRL1) 	///../ucode/register.h
#define AUDIN_FIFO0_LVL0 0x2827 	///../ucode/register.h
#define P_AUDIN_FIFO0_LVL0 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL0) 	///../ucode/register.h
#define AUDIN_FIFO0_LVL1 0x2828 	///../ucode/register.h
#define P_AUDIN_FIFO0_LVL1 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL1) 	///../ucode/register.h
#define AUDIN_FIFO0_LVL2 0x2829 	///../ucode/register.h
#define P_AUDIN_FIFO0_LVL2 		CBUS_REG_ADDR(AUDIN_FIFO0_LVL2) 	///../ucode/register.h
#define AUDIN_FIFO1_START 0x282a 	///../ucode/register.h
#define P_AUDIN_FIFO1_START 		CBUS_REG_ADDR(AUDIN_FIFO1_START) 	///../ucode/register.h
#define AUDIN_FIFO1_END 0x282b 	///../ucode/register.h
#define P_AUDIN_FIFO1_END 		CBUS_REG_ADDR(AUDIN_FIFO1_END) 	///../ucode/register.h
#define AUDIN_FIFO1_PTR 0x282c 	///../ucode/register.h
#define P_AUDIN_FIFO1_PTR 		CBUS_REG_ADDR(AUDIN_FIFO1_PTR) 	///../ucode/register.h
#define AUDIN_FIFO1_INTR 0x282d 	///../ucode/register.h
#define P_AUDIN_FIFO1_INTR 		CBUS_REG_ADDR(AUDIN_FIFO1_INTR) 	///../ucode/register.h
#define AUDIN_FIFO1_RDPTR 0x282e 	///../ucode/register.h
#define P_AUDIN_FIFO1_RDPTR 		CBUS_REG_ADDR(AUDIN_FIFO1_RDPTR) 	///../ucode/register.h
#define AUDIN_FIFO1_CTRL 0x282f 	///../ucode/register.h
#define P_AUDIN_FIFO1_CTRL 		CBUS_REG_ADDR(AUDIN_FIFO1_CTRL) 	///../ucode/register.h
#define AUDIN_FIFO1_CTRL1 0x2830 	///../ucode/register.h
#define P_AUDIN_FIFO1_CTRL1 		CBUS_REG_ADDR(AUDIN_FIFO1_CTRL1) 	///../ucode/register.h
#define AUDIN_FIFO1_LVL0 0x2831 	///../ucode/register.h
#define P_AUDIN_FIFO1_LVL0 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL0) 	///../ucode/register.h
#define AUDIN_FIFO1_LVL1 0x2832 	///../ucode/register.h
#define P_AUDIN_FIFO1_LVL1 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL1) 	///../ucode/register.h
#define AUDIN_FIFO1_LVL2 0x2833 	///../ucode/register.h
#define P_AUDIN_FIFO1_LVL2 		CBUS_REG_ADDR(AUDIN_FIFO1_LVL2) 	///../ucode/register.h
#define AUDIN_FIFO0_REQID 0x2834 	///../ucode/register.h
#define P_AUDIN_FIFO0_REQID 		CBUS_REG_ADDR(AUDIN_FIFO0_REQID) 	///../ucode/register.h
#define AUDIN_FIFO1_REQID 0x2835 	///../ucode/register.h
#define P_AUDIN_FIFO1_REQID 		CBUS_REG_ADDR(AUDIN_FIFO1_REQID) 	///../ucode/register.h
#define AUDIN_INT_CTRL 0x2836 	///../ucode/register.h
#define P_AUDIN_INT_CTRL 		CBUS_REG_ADDR(AUDIN_INT_CTRL) 	///../ucode/register.h
#define AUDIN_FIFO_INT 0x2837 	///../ucode/register.h
#define P_AUDIN_FIFO_INT 		CBUS_REG_ADDR(AUDIN_FIFO_INT) 	///../ucode/register.h
#define AUDIN_FIFO0_WRAP 0x2838 	///../ucode/register.h
#define P_AUDIN_FIFO0_WRAP 		CBUS_REG_ADDR(AUDIN_FIFO0_WRAP) 	///../ucode/register.h
#define AUDIN_FIFO1_WRAP 0x2839 	///../ucode/register.h
#define P_AUDIN_FIFO1_WRAP 		CBUS_REG_ADDR(AUDIN_FIFO1_WRAP) 	///../ucode/register.h
#define AUDIN_PIO_STS 0x283a 	///../ucode/register.h
#define P_AUDIN_PIO_STS 		CBUS_REG_ADDR(AUDIN_PIO_STS) 	///../ucode/register.h
#define AUDIN_RD_L 0x283b 	///../ucode/register.h
#define P_AUDIN_RD_L 		CBUS_REG_ADDR(AUDIN_RD_L) 	///../ucode/register.h
#define AUDIN_RD_H 0x283c 	///../ucode/register.h
#define P_AUDIN_RD_H 		CBUS_REG_ADDR(AUDIN_RD_H) 	///../ucode/register.h
#define PCMIN_CTRL0 0x2840 	///../ucode/register.h
#define P_PCMIN_CTRL0 		CBUS_REG_ADDR(PCMIN_CTRL0) 	///../ucode/register.h
#define PCMIN_CTRL1 0x2841 	///../ucode/register.h
#define P_PCMIN_CTRL1 		CBUS_REG_ADDR(PCMIN_CTRL1) 	///../ucode/register.h
#define PCMOUT_CTRL0 0x2850 	///../ucode/register.h
#define P_PCMOUT_CTRL0 		CBUS_REG_ADDR(PCMOUT_CTRL0) 	///../ucode/register.h
#define PCMOUT_CTRL1 0x2851 	///../ucode/register.h
#define P_PCMOUT_CTRL1 		CBUS_REG_ADDR(PCMOUT_CTRL1) 	///../ucode/register.h
#define PCMOUT_CTRL2 0x2852 	///../ucode/register.h
#define P_PCMOUT_CTRL2 		CBUS_REG_ADDR(PCMOUT_CTRL2) 	///../ucode/register.h
#define PCMOUT_CTRL3 0x2853 	///../ucode/register.h
#define P_PCMOUT_CTRL3 		CBUS_REG_ADDR(PCMOUT_CTRL3) 	///../ucode/register.h
#define AUDOUT_CTRL 0x2860 	///../ucode/register.h
#define P_AUDOUT_CTRL 		CBUS_REG_ADDR(AUDOUT_CTRL) 	///../ucode/register.h
#define AUDOUT_CTRL1 0x2861 	///../ucode/register.h
#define P_AUDOUT_CTRL1 		CBUS_REG_ADDR(AUDOUT_CTRL1) 	///../ucode/register.h
#define AUDOUT_BUF0_STA 0x2862 	///../ucode/register.h
#define P_AUDOUT_BUF0_STA 		CBUS_REG_ADDR(AUDOUT_BUF0_STA) 	///../ucode/register.h
#define AUDOUT_BUF0_EDA 0x2863 	///../ucode/register.h
#define P_AUDOUT_BUF0_EDA 		CBUS_REG_ADDR(AUDOUT_BUF0_EDA) 	///../ucode/register.h
#define AUDOUT_BUF0_WPTR 0x2864 	///../ucode/register.h
#define P_AUDOUT_BUF0_WPTR 		CBUS_REG_ADDR(AUDOUT_BUF0_WPTR) 	///../ucode/register.h
#define AUDOUT_BUF1_STA 0x2865 	///../ucode/register.h
#define P_AUDOUT_BUF1_STA 		CBUS_REG_ADDR(AUDOUT_BUF1_STA) 	///../ucode/register.h
#define AUDOUT_BUF1_EDA 0x2866 	///../ucode/register.h
#define P_AUDOUT_BUF1_EDA 		CBUS_REG_ADDR(AUDOUT_BUF1_EDA) 	///../ucode/register.h
#define AUDOUT_BUF1_WPTR 0x2867 	///../ucode/register.h
#define P_AUDOUT_BUF1_WPTR 		CBUS_REG_ADDR(AUDOUT_BUF1_WPTR) 	///../ucode/register.h
#define AUDOUT_FIFO_RPTR 0x2868 	///../ucode/register.h
#define P_AUDOUT_FIFO_RPTR 		CBUS_REG_ADDR(AUDOUT_FIFO_RPTR) 	///../ucode/register.h
#define AUDOUT_INTR_PTR 0x2869 	///../ucode/register.h
#define P_AUDOUT_INTR_PTR 		CBUS_REG_ADDR(AUDOUT_INTR_PTR) 	///../ucode/register.h
#define AUDOUT_FIFO_STS 0x286a 	///../ucode/register.h
#define P_AUDOUT_FIFO_STS 		CBUS_REG_ADDR(AUDOUT_FIFO_STS) 	///../ucode/register.h
#define AUDOUT_WR_L 0x286b 	///../ucode/register.h
#define P_AUDOUT_WR_L 		CBUS_REG_ADDR(AUDOUT_WR_L) 	///../ucode/register.h
#define AUDOUT_WR_H 0x286c 	///../ucode/register.h
#define P_AUDOUT_WR_H 		CBUS_REG_ADDR(AUDOUT_WR_H) 	///../ucode/register.h
#define AUDIN_ADDR_END 0x287f 	///../ucode/register.h
#define P_AUDIN_ADDR_END 		CBUS_REG_ADDR(AUDIN_ADDR_END) 	///../ucode/register.h
#define P_AO_RTI_STATUS_REG0 		AOBUS_REG_ADDR((0x00 << 10) | (0x00 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_RTI_STATUS_REG1 		AOBUS_REG_ADDR((0x00 << 10) | (0x01 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_RTI_STATUS_REG2 		AOBUS_REG_ADDR((0x00 << 10) | (0x02 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_RTI_PWR_CNTL_REG0 		AOBUS_REG_ADDR((0x00 << 10) | (0x04 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_RTI_PIN_MUX_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x05 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_WD_GPIO_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x06 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_REMAP_REG0 		AOBUS_REG_ADDR((0x00 << 10) | (0x07 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_REMAP_REG1 		AOBUS_REG_ADDR((0x00 << 10) | (0x08 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_GPIO_O_EN_N 		AOBUS_REG_ADDR((0x00 << 10) | (0x09 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_GPIO_I 		AOBUS_REG_ADDR((0x00 << 10) | (0x0A << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_RTI_PULL_UP_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x0B << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_RTI_WD_MARK 		AOBUS_REG_ADDR((0x00 << 10) | (0x0D << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_RTI_GEN_CNTL_REG0 		AOBUS_REG_ADDR((0x00 << 10) | (0x10 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_WATCHDOG_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x11 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_WATCHDOG_RESET 		AOBUS_REG_ADDR((0x00 << 10) | (0x12 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_TIMER_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x13 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_TIMERA_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x14 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_TIMERE_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x15 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_AHB2DDR_CNTL 		AOBUS_REG_ADDR((0x00 << 10) | (0x18 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IRQ_MASK_FIQ_SEL 		AOBUS_REG_ADDR((0x00 << 10) | (0x20 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IRQ_GPIO_REG 		AOBUS_REG_ADDR((0x00 << 10) | (0x21 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IRQ_STAT 		AOBUS_REG_ADDR((0x00 << 10) | (0x22 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IRQ_STAT_CLR 		AOBUS_REG_ADDR((0x00 << 10) | (0x23 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_DEBUG_REG0 		AOBUS_REG_ADDR((0x00 << 10) | (0x28 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_DEBUG_REG1 		AOBUS_REG_ADDR((0x00 << 10) | (0x29 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_DEBUG_REG2 		AOBUS_REG_ADDR((0x00 << 10) | (0x2a << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_DEBUG_REG3 		AOBUS_REG_ADDR((0x00 << 10) | (0x2b << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_LDR_ACTIVE 		AOBUS_REG_ADDR((0x01 << 10) | (0x20 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_LDR_IDLE 		AOBUS_REG_ADDR((0x01 << 10) | (0x21 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_LDR_REPEAT 		AOBUS_REG_ADDR((0x01 << 10) | (0x22 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_BIT_0 		AOBUS_REG_ADDR((0x01 << 10) | (0x23 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_REG0 		AOBUS_REG_ADDR((0x01 << 10) | (0x24 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_FRAME 		AOBUS_REG_ADDR((0x01 << 10) | (0x25 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_STATUS 		AOBUS_REG_ADDR((0x01 << 10) | (0x26 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_IR_DEC_REG1 		AOBUS_REG_ADDR((0x01 << 10) | (0x27 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART_WFIFO 		AOBUS_REG_ADDR((0x01 << 10) | (0x30 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART_RFIFO 		AOBUS_REG_ADDR((0x01 << 10) | (0x31 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART_CONTROL 		AOBUS_REG_ADDR((0x01 << 10) | (0x32 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART_STATUS 		AOBUS_REG_ADDR((0x01 << 10) | (0x33 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART_MISC 		AOBUS_REG_ADDR((0x01 << 10) | (0x34 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART_REG5 		AOBUS_REG_ADDR((0x01 << 10) | (0x35 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART2_WFIFO 		AOBUS_REG_ADDR((0x01 << 10) | (0x38 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART2_RFIFO 		AOBUS_REG_ADDR((0x01 << 10) | (0x39 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART2_CONTROL 		AOBUS_REG_ADDR((0x01 << 10) | (0x3a << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART2_STATUS 		AOBUS_REG_ADDR((0x01 << 10) | (0x3b << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART2_MISC 		AOBUS_REG_ADDR((0x01 << 10) | (0x3c << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_UART2_REG5 		AOBUS_REG_ADDR((0x01 << 10) | (0x3d << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_CONTROL_REG 		AOBUS_REG_ADDR((0x01 << 10) | (0x40 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_SLAVE_ADDR 		AOBUS_REG_ADDR((0x01 << 10) | (0x41 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_TOKEN_LIST0 		AOBUS_REG_ADDR((0x01 << 10) | (0x42 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_TOKEN_LIST1 		AOBUS_REG_ADDR((0x01 << 10) | (0x43 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_WDATA_REG0 		AOBUS_REG_ADDR((0x01 << 10) | (0x44 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_WDATA_REG1 		AOBUS_REG_ADDR((0x01 << 10) | (0x45 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_RDATA_REG0 		AOBUS_REG_ADDR((0x01 << 10) | (0x46 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_M_0_RDATA_REG1 		AOBUS_REG_ADDR((0x01 << 10) | (0x47 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_S_CONTROL_REG 		AOBUS_REG_ADDR((0x01 << 10) | (0x50 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_S_SEND_REG 		AOBUS_REG_ADDR((0x01 << 10) | (0x51 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_S_RECV_REG 		AOBUS_REG_ADDR((0x01 << 10) | (0x52 << 2)) 	///../ucode/c_always_on_pointer.h
#define P_AO_I2C_S_CNTL1_REG 		AOBUS_REG_ADDR((0x01 << 10) | (0x53 << 2)) 	///../ucode/c_always_on_pointer.h
#define UPCTL_STAT_ADDR 0x0008 	///../ucode/pctl.h
#define P_UPCTL_STAT_ADDR 		APB_REG_ADDR(UPCTL_STAT_ADDR) 	///../ucode/pctl.h
#define UPCTL_INTRSTAT_ADDR 0x000c 	///../ucode/pctl.h
#define P_UPCTL_INTRSTAT_ADDR 		APB_REG_ADDR(UPCTL_INTRSTAT_ADDR) 	///../ucode/pctl.h
#define UPCTL_SCTL_ADDR 0x0004 	///../ucode/pctl.h
#define P_UPCTL_SCTL_ADDR 		APB_REG_ADDR(UPCTL_SCTL_ADDR) 	///../ucode/pctl.h
#define UPCTL_SCFG_ADDR 0x0000 	///../ucode/pctl.h
#define P_UPCTL_SCFG_ADDR 		APB_REG_ADDR(UPCTL_SCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_POWSTAT_ADDR 0x0048 	///../ucode/pctl.h
#define P_UPCTL_POWSTAT_ADDR 		APB_REG_ADDR(UPCTL_POWSTAT_ADDR) 	///../ucode/pctl.h
#define UPCTL_MRRSTAT0_ADDR 0x0064 	///../ucode/pctl.h
#define P_UPCTL_MRRSTAT0_ADDR 		APB_REG_ADDR(UPCTL_MRRSTAT0_ADDR) 	///../ucode/pctl.h
#define UPCTL_CMDTSTAT_ADDR 0x004c 	///../ucode/pctl.h
#define P_UPCTL_CMDTSTAT_ADDR 		APB_REG_ADDR(UPCTL_CMDTSTAT_ADDR) 	///../ucode/pctl.h
#define UPCTL_MCMD_ADDR 0x0040 	///../ucode/pctl.h
#define P_UPCTL_MCMD_ADDR 		APB_REG_ADDR(UPCTL_MCMD_ADDR) 	///../ucode/pctl.h
#define UPCTL_MRRSTAT1_ADDR 0x0068 	///../ucode/pctl.h
#define P_UPCTL_MRRSTAT1_ADDR 		APB_REG_ADDR(UPCTL_MRRSTAT1_ADDR) 	///../ucode/pctl.h
#define UPCTL_MRRCFG0_ADDR 0x0060 	///../ucode/pctl.h
#define P_UPCTL_MRRCFG0_ADDR 		APB_REG_ADDR(UPCTL_MRRCFG0_ADDR) 	///../ucode/pctl.h
#define UPCTL_CMDTSTATEN_ADDR 0x0050 	///../ucode/pctl.h
#define P_UPCTL_CMDTSTATEN_ADDR 		APB_REG_ADDR(UPCTL_CMDTSTATEN_ADDR) 	///../ucode/pctl.h
#define UPCTL_POWCTL_ADDR 0x0044 	///../ucode/pctl.h
#define P_UPCTL_POWCTL_ADDR 		APB_REG_ADDR(UPCTL_POWCTL_ADDR) 	///../ucode/pctl.h
#define UPCTL_LPDDR2ZQCFG_ADDR 0x008c 	///../ucode/pctl.h
#define P_UPCTL_LPDDR2ZQCFG_ADDR 		APB_REG_ADDR(UPCTL_LPDDR2ZQCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_PPCFG_ADDR 0x0084 	///../ucode/pctl.h
#define P_UPCTL_PPCFG_ADDR 		APB_REG_ADDR(UPCTL_PPCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_MCFG1_ADDR 0x007c 	///../ucode/pctl.h
#define P_UPCTL_MCFG1_ADDR 		APB_REG_ADDR(UPCTL_MCFG1_ADDR) 	///../ucode/pctl.h
#define UPCTL_MSTAT_ADDR 0x0088 	///../ucode/pctl.h
#define P_UPCTL_MSTAT_ADDR 		APB_REG_ADDR(UPCTL_MSTAT_ADDR) 	///../ucode/pctl.h
#define UPCTL_MCFG_ADDR 0x0080 	///../ucode/pctl.h
#define P_UPCTL_MCFG_ADDR 		APB_REG_ADDR(UPCTL_MCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUAWDT_ADDR 0x00b0 	///../ucode/pctl.h
#define P_UPCTL_DTUAWDT_ADDR 		APB_REG_ADDR(UPCTL_DTUAWDT_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUPRD2_ADDR 0x00a8 	///../ucode/pctl.h
#define P_UPCTL_DTUPRD2_ADDR 		APB_REG_ADDR(UPCTL_DTUPRD2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUPRD3_ADDR 0x00ac 	///../ucode/pctl.h
#define P_UPCTL_DTUPRD3_ADDR 		APB_REG_ADDR(UPCTL_DTUPRD3_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUNE_ADDR 0x009c 	///../ucode/pctl.h
#define P_UPCTL_DTUNE_ADDR 		APB_REG_ADDR(UPCTL_DTUNE_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUPDES_ADDR 0x0094 	///../ucode/pctl.h
#define P_UPCTL_DTUPDES_ADDR 		APB_REG_ADDR(UPCTL_DTUPDES_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUNA_ADDR 0x0098 	///../ucode/pctl.h
#define P_UPCTL_DTUNA_ADDR 		APB_REG_ADDR(UPCTL_DTUNA_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUPRD0_ADDR 0x00a0 	///../ucode/pctl.h
#define P_UPCTL_DTUPRD0_ADDR 		APB_REG_ADDR(UPCTL_DTUPRD0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUPRD1_ADDR 0x00a4 	///../ucode/pctl.h
#define P_UPCTL_DTUPRD1_ADDR 		APB_REG_ADDR(UPCTL_DTUPRD1_ADDR) 	///../ucode/pctl.h
#define UPCTL_TCKSRE_ADDR 0x0124 	///../ucode/pctl.h
#define P_UPCTL_TCKSRE_ADDR 		APB_REG_ADDR(UPCTL_TCKSRE_ADDR) 	///../ucode/pctl.h
#define UPCTL_TZQCSI_ADDR 0x011c 	///../ucode/pctl.h
#define P_UPCTL_TZQCSI_ADDR 		APB_REG_ADDR(UPCTL_TZQCSI_ADDR) 	///../ucode/pctl.h
#define UPCTL_TINIT_ADDR 0x00c4 	///../ucode/pctl.h
#define P_UPCTL_TINIT_ADDR 		APB_REG_ADDR(UPCTL_TINIT_ADDR) 	///../ucode/pctl.h
#define UPCTL_TDPD_ADDR 0x0144 	///../ucode/pctl.h
#define P_UPCTL_TDPD_ADDR 		APB_REG_ADDR(UPCTL_TDPD_ADDR) 	///../ucode/pctl.h
#define UPCTL_TOGCNT1U_ADDR 0x00c0 	///../ucode/pctl.h
#define P_UPCTL_TOGCNT1U_ADDR 		APB_REG_ADDR(UPCTL_TOGCNT1U_ADDR) 	///../ucode/pctl.h
#define UPCTL_TCKE_ADDR 0x012c 	///../ucode/pctl.h
#define P_UPCTL_TCKE_ADDR 		APB_REG_ADDR(UPCTL_TCKE_ADDR) 	///../ucode/pctl.h
#define UPCTL_TMOD_ADDR 0x0130 	///../ucode/pctl.h
#define P_UPCTL_TMOD_ADDR 		APB_REG_ADDR(UPCTL_TMOD_ADDR) 	///../ucode/pctl.h
#define UPCTL_TEXSR_ADDR 0x010c 	///../ucode/pctl.h
#define P_UPCTL_TEXSR_ADDR 		APB_REG_ADDR(UPCTL_TEXSR_ADDR) 	///../ucode/pctl.h
#define UPCTL_TAL_ADDR 0x00e4 	///../ucode/pctl.h
#define P_UPCTL_TAL_ADDR 		APB_REG_ADDR(UPCTL_TAL_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRTP_ADDR 0x0100 	///../ucode/pctl.h
#define P_UPCTL_TRTP_ADDR 		APB_REG_ADDR(UPCTL_TRTP_ADDR) 	///../ucode/pctl.h
#define UPCTL_TCKSRX_ADDR 0x0128 	///../ucode/pctl.h
#define P_UPCTL_TCKSRX_ADDR 		APB_REG_ADDR(UPCTL_TCKSRX_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRTW_ADDR 0x00e0 	///../ucode/pctl.h
#define P_UPCTL_TRTW_ADDR 		APB_REG_ADDR(UPCTL_TRTW_ADDR) 	///../ucode/pctl.h
#define UPCTL_TCWL_ADDR 0x00ec 	///../ucode/pctl.h
#define P_UPCTL_TCWL_ADDR 		APB_REG_ADDR(UPCTL_TCWL_ADDR) 	///../ucode/pctl.h
#define UPCTL_TWR_ADDR 0x0104 	///../ucode/pctl.h
#define P_UPCTL_TWR_ADDR 		APB_REG_ADDR(UPCTL_TWR_ADDR) 	///../ucode/pctl.h
#define UPCTL_TCL_ADDR 0x00e8 	///../ucode/pctl.h
#define P_UPCTL_TCL_ADDR 		APB_REG_ADDR(UPCTL_TCL_ADDR) 	///../ucode/pctl.h
#define UPCTL_TDQS_ADDR 0x0120 	///../ucode/pctl.h
#define P_UPCTL_TDQS_ADDR 		APB_REG_ADDR(UPCTL_TDQS_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRSTH_ADDR 0x00c8 	///../ucode/pctl.h
#define P_UPCTL_TRSTH_ADDR 		APB_REG_ADDR(UPCTL_TRSTH_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRCD_ADDR 0x00f8 	///../ucode/pctl.h
#define P_UPCTL_TRCD_ADDR 		APB_REG_ADDR(UPCTL_TRCD_ADDR) 	///../ucode/pctl.h
#define UPCTL_TXP_ADDR 0x0110 	///../ucode/pctl.h
#define P_UPCTL_TXP_ADDR 		APB_REG_ADDR(UPCTL_TXP_ADDR) 	///../ucode/pctl.h
#define UPCTL_TOGCNT100N_ADDR 0x00cc 	///../ucode/pctl.h
#define P_UPCTL_TOGCNT100N_ADDR 		APB_REG_ADDR(UPCTL_TOGCNT100N_ADDR) 	///../ucode/pctl.h
#define UPCTL_TMRD_ADDR 0x00d4 	///../ucode/pctl.h
#define P_UPCTL_TMRD_ADDR 		APB_REG_ADDR(UPCTL_TMRD_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRSTL_ADDR 0x0134 	///../ucode/pctl.h
#define P_UPCTL_TRSTL_ADDR 		APB_REG_ADDR(UPCTL_TRSTL_ADDR) 	///../ucode/pctl.h
#define UPCTL_TREFI_ADDR 0x00d0 	///../ucode/pctl.h
#define P_UPCTL_TREFI_ADDR 		APB_REG_ADDR(UPCTL_TREFI_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRAS_ADDR 0x00f0 	///../ucode/pctl.h
#define P_UPCTL_TRAS_ADDR 		APB_REG_ADDR(UPCTL_TRAS_ADDR) 	///../ucode/pctl.h
#define UPCTL_TWTR_ADDR 0x0108 	///../ucode/pctl.h
#define P_UPCTL_TWTR_ADDR 		APB_REG_ADDR(UPCTL_TWTR_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRC_ADDR 0x00f4 	///../ucode/pctl.h
#define P_UPCTL_TRC_ADDR 		APB_REG_ADDR(UPCTL_TRC_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRFC_ADDR 0x00d8 	///../ucode/pctl.h
#define P_UPCTL_TRFC_ADDR 		APB_REG_ADDR(UPCTL_TRFC_ADDR) 	///../ucode/pctl.h
#define UPCTL_TMRR_ADDR 0x013c 	///../ucode/pctl.h
#define P_UPCTL_TMRR_ADDR 		APB_REG_ADDR(UPCTL_TMRR_ADDR) 	///../ucode/pctl.h
#define UPCTL_TCKESR_ADDR 0x0140 	///../ucode/pctl.h
#define P_UPCTL_TCKESR_ADDR 		APB_REG_ADDR(UPCTL_TCKESR_ADDR) 	///../ucode/pctl.h
#define UPCTL_TZQCL_ADDR 0x0138 	///../ucode/pctl.h
#define P_UPCTL_TZQCL_ADDR 		APB_REG_ADDR(UPCTL_TZQCL_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRRD_ADDR 0x00fc 	///../ucode/pctl.h
#define P_UPCTL_TRRD_ADDR 		APB_REG_ADDR(UPCTL_TRRD_ADDR) 	///../ucode/pctl.h
#define UPCTL_TRP_ADDR 0x00dc 	///../ucode/pctl.h
#define P_UPCTL_TRP_ADDR 		APB_REG_ADDR(UPCTL_TRP_ADDR) 	///../ucode/pctl.h
#define UPCTL_TZQCS_ADDR 0x0118 	///../ucode/pctl.h
#define P_UPCTL_TZQCS_ADDR 		APB_REG_ADDR(UPCTL_TZQCS_ADDR) 	///../ucode/pctl.h
#define UPCTL_TXPDLL_ADDR 0x0114 	///../ucode/pctl.h
#define P_UPCTL_TXPDLL_ADDR 		APB_REG_ADDR(UPCTL_TXPDLL_ADDR) 	///../ucode/pctl.h
#define UPCTL_ECCCFG_ADDR 0x0180 	///../ucode/pctl.h
#define P_UPCTL_ECCCFG_ADDR 		APB_REG_ADDR(UPCTL_ECCCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_ECCLOG_ADDR 0x018c 	///../ucode/pctl.h
#define P_UPCTL_ECCLOG_ADDR 		APB_REG_ADDR(UPCTL_ECCLOG_ADDR) 	///../ucode/pctl.h
#define UPCTL_ECCCLR_ADDR 0x0188 	///../ucode/pctl.h
#define P_UPCTL_ECCCLR_ADDR 		APB_REG_ADDR(UPCTL_ECCCLR_ADDR) 	///../ucode/pctl.h
#define UPCTL_ECCTST_ADDR 0x0184 	///../ucode/pctl.h
#define P_UPCTL_ECCTST_ADDR 		APB_REG_ADDR(UPCTL_ECCTST_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUWD0_ADDR 0x0210 	///../ucode/pctl.h
#define P_UPCTL_DTUWD0_ADDR 		APB_REG_ADDR(UPCTL_DTUWD0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUWD1_ADDR 0x0214 	///../ucode/pctl.h
#define P_UPCTL_DTUWD1_ADDR 		APB_REG_ADDR(UPCTL_DTUWD1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUWACTL_ADDR 0x0200 	///../ucode/pctl.h
#define P_UPCTL_DTUWACTL_ADDR 		APB_REG_ADDR(UPCTL_DTUWACTL_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTULFSRRD_ADDR 0x0238 	///../ucode/pctl.h
#define P_UPCTL_DTULFSRRD_ADDR 		APB_REG_ADDR(UPCTL_DTULFSRRD_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUWD2_ADDR 0x0218 	///../ucode/pctl.h
#define P_UPCTL_DTUWD2_ADDR 		APB_REG_ADDR(UPCTL_DTUWD2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUWD3_ADDR 0x021c 	///../ucode/pctl.h
#define P_UPCTL_DTUWD3_ADDR 		APB_REG_ADDR(UPCTL_DTUWD3_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTULFSRWD_ADDR 0x0234 	///../ucode/pctl.h
#define P_UPCTL_DTULFSRWD_ADDR 		APB_REG_ADDR(UPCTL_DTULFSRWD_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTURACTL_ADDR 0x0204 	///../ucode/pctl.h
#define P_UPCTL_DTURACTL_ADDR 		APB_REG_ADDR(UPCTL_DTURACTL_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUWDM_ADDR 0x0220 	///../ucode/pctl.h
#define P_UPCTL_DTUWDM_ADDR 		APB_REG_ADDR(UPCTL_DTUWDM_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTURD0_ADDR 0x0224 	///../ucode/pctl.h
#define P_UPCTL_DTURD0_ADDR 		APB_REG_ADDR(UPCTL_DTURD0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTURD1_ADDR 0x0228 	///../ucode/pctl.h
#define P_UPCTL_DTURD1_ADDR 		APB_REG_ADDR(UPCTL_DTURD1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTURD2_ADDR 0x022c 	///../ucode/pctl.h
#define P_UPCTL_DTURD2_ADDR 		APB_REG_ADDR(UPCTL_DTURD2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTURD3_ADDR 0x0230 	///../ucode/pctl.h
#define P_UPCTL_DTURD3_ADDR 		APB_REG_ADDR(UPCTL_DTURD3_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUCFG_ADDR 0x0208 	///../ucode/pctl.h
#define P_UPCTL_DTUCFG_ADDR 		APB_REG_ADDR(UPCTL_DTUCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUEAF_ADDR 0x023c 	///../ucode/pctl.h
#define P_UPCTL_DTUEAF_ADDR 		APB_REG_ADDR(UPCTL_DTUEAF_ADDR) 	///../ucode/pctl.h
#define UPCTL_DTUECTL_ADDR 0x020c 	///../ucode/pctl.h
#define P_UPCTL_DTUECTL_ADDR 		APB_REG_ADDR(UPCTL_DTUECTL_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFIODTCFG1_ADDR 0x0248 	///../ucode/pctl.h
#define P_UPCTL_DFIODTCFG1_ADDR 		APB_REG_ADDR(UPCTL_DFIODTCFG1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITCTRLDELAY_ADDR 0x0240 	///../ucode/pctl.h
#define P_UPCTL_DFITCTRLDELAY_ADDR 		APB_REG_ADDR(UPCTL_DFITCTRLDELAY_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFIODTRANKMAP_ADDR 0x024c 	///../ucode/pctl.h
#define P_UPCTL_DFIODTRANKMAP_ADDR 		APB_REG_ADDR(UPCTL_DFIODTRANKMAP_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFIODTCFG_ADDR 0x0244 	///../ucode/pctl.h
#define P_UPCTL_DFIODTCFG_ADDR 		APB_REG_ADDR(UPCTL_DFIODTCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITPHYWRLAT_ADDR 0x0254 	///../ucode/pctl.h
#define P_UPCTL_DFITPHYWRLAT_ADDR 		APB_REG_ADDR(UPCTL_DFITPHYWRLAT_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITPHYWRDATA_ADDR 0x0250 	///../ucode/pctl.h
#define P_UPCTL_DFITPHYWRDATA_ADDR 		APB_REG_ADDR(UPCTL_DFITPHYWRDATA_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRDDATAEN_ADDR 0x0260 	///../ucode/pctl.h
#define P_UPCTL_DFITRDDATAEN_ADDR 		APB_REG_ADDR(UPCTL_DFITRDDATAEN_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITPHYRDLAT_ADDR 0x0264 	///../ucode/pctl.h
#define P_UPCTL_DFITPHYRDLAT_ADDR 		APB_REG_ADDR(UPCTL_DFITPHYRDLAT_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITREFMSKI_ADDR 0x0294 	///../ucode/pctl.h
#define P_UPCTL_DFITREFMSKI_ADDR 		APB_REG_ADDR(UPCTL_DFITREFMSKI_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITPHYUPDTYPE0_ADDR 0x0270 	///../ucode/pctl.h
#define P_UPCTL_DFITPHYUPDTYPE0_ADDR 		APB_REG_ADDR(UPCTL_DFITPHYUPDTYPE0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITPHYUPDTYPE1_ADDR 0x0274 	///../ucode/pctl.h
#define P_UPCTL_DFITPHYUPDTYPE1_ADDR 		APB_REG_ADDR(UPCTL_DFITPHYUPDTYPE1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITCTRLUPDDLY_ADDR 0x0288 	///../ucode/pctl.h
#define P_UPCTL_DFITCTRLUPDDLY_ADDR 		APB_REG_ADDR(UPCTL_DFITCTRLUPDDLY_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITPHYUPDTYPE2_ADDR 0x0278 	///../ucode/pctl.h
#define P_UPCTL_DFITPHYUPDTYPE2_ADDR 		APB_REG_ADDR(UPCTL_DFITPHYUPDTYPE2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITCTRLUPDMIN_ADDR 0x0280 	///../ucode/pctl.h
#define P_UPCTL_DFITCTRLUPDMIN_ADDR 		APB_REG_ADDR(UPCTL_DFITCTRLUPDMIN_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITPHYUPDTYPE3_ADDR 0x027c 	///../ucode/pctl.h
#define P_UPCTL_DFITPHYUPDTYPE3_ADDR 		APB_REG_ADDR(UPCTL_DFITPHYUPDTYPE3_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFIUPDCFG_ADDR 0x0290 	///../ucode/pctl.h
#define P_UPCTL_DFIUPDCFG_ADDR 		APB_REG_ADDR(UPCTL_DFIUPDCFG_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITCTRLUPDMAX_ADDR 0x0284 	///../ucode/pctl.h
#define P_UPCTL_DFITCTRLUPDMAX_ADDR 		APB_REG_ADDR(UPCTL_DFITCTRLUPDMAX_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITCTRLUPDI_ADDR 0x0298 	///../ucode/pctl.h
#define P_UPCTL_DFITCTRLUPDI_ADDR 		APB_REG_ADDR(UPCTL_DFITCTRLUPDI_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLEN_ADDR 0x02b8 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLEN_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLEN_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRSTAT0_ADDR 0x02b0 	///../ucode/pctl.h
#define P_UPCTL_DFITRSTAT0_ADDR 		APB_REG_ADDR(UPCTL_DFITRSTAT0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRWRLVLEN_ADDR 0x02b4 	///../ucode/pctl.h
#define P_UPCTL_DFITRWRLVLEN_ADDR 		APB_REG_ADDR(UPCTL_DFITRWRLVLEN_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRCFG0_ADDR 0x02ac 	///../ucode/pctl.h
#define P_UPCTL_DFITRCFG0_ADDR 		APB_REG_ADDR(UPCTL_DFITRCFG0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLGATEEN_ADDR 0x02bc 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLGATEEN_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLGATEEN_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFISTSTAT0_ADDR 0x02c0 	///../ucode/pctl.h
#define P_UPCTL_DFISTSTAT0_ADDR 		APB_REG_ADDR(UPCTL_DFISTSTAT0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFISTPARLOG_ADDR 0x02e0 	///../ucode/pctl.h
#define P_UPCTL_DFISTPARLOG_ADDR 		APB_REG_ADDR(UPCTL_DFISTPARLOG_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITDRAMCLKEN_ADDR 0x02d0 	///../ucode/pctl.h
#define P_UPCTL_DFITDRAMCLKEN_ADDR 		APB_REG_ADDR(UPCTL_DFITDRAMCLKEN_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFISTPARCLR_ADDR 0x02dc 	///../ucode/pctl.h
#define P_UPCTL_DFISTPARCLR_ADDR 		APB_REG_ADDR(UPCTL_DFISTPARCLR_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFISTCFG0_ADDR 0x02c4 	///../ucode/pctl.h
#define P_UPCTL_DFISTCFG0_ADDR 		APB_REG_ADDR(UPCTL_DFISTCFG0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFISTCFG1_ADDR 0x02c8 	///../ucode/pctl.h
#define P_UPCTL_DFISTCFG1_ADDR 		APB_REG_ADDR(UPCTL_DFISTCFG1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFISTCFG2_ADDR 0x02d8 	///../ucode/pctl.h
#define P_UPCTL_DFISTCFG2_ADDR 		APB_REG_ADDR(UPCTL_DFISTCFG2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITDRAMCLKDIS_ADDR 0x02d4 	///../ucode/pctl.h
#define P_UPCTL_DFITDRAMCLKDIS_ADDR 		APB_REG_ADDR(UPCTL_DFITDRAMCLKDIS_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFILPCFG0_ADDR 0x02f0 	///../ucode/pctl.h
#define P_UPCTL_DFILPCFG0_ADDR 		APB_REG_ADDR(UPCTL_DFILPCFG0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRWRLVLDELAY0_ADDR 0x0318 	///../ucode/pctl.h
#define P_UPCTL_DFITRWRLVLDELAY0_ADDR 		APB_REG_ADDR(UPCTL_DFITRWRLVLDELAY0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRWRLVLDELAY1_ADDR 0x031c 	///../ucode/pctl.h
#define P_UPCTL_DFITRWRLVLDELAY1_ADDR 		APB_REG_ADDR(UPCTL_DFITRWRLVLDELAY1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRWRLVLDELAY2_ADDR 0x0320 	///../ucode/pctl.h
#define P_UPCTL_DFITRWRLVLDELAY2_ADDR 		APB_REG_ADDR(UPCTL_DFITRWRLVLDELAY2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLRESP0_ADDR 0x030c 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLRESP0_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLRESP0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLRESP1_ADDR 0x0310 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLRESP1_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLRESP1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLRESP2_ADDR 0x0314 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLRESP2_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLRESP2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRWRLVLRESP0_ADDR 0x0300 	///../ucode/pctl.h
#define P_UPCTL_DFITRWRLVLRESP0_ADDR 		APB_REG_ADDR(UPCTL_DFITRWRLVLRESP0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLDELAY0_ADDR 0x0324 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLDELAY0_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLDELAY0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLDELAY1_ADDR 0x0328 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLDELAY1_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLDELAY1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRWRLVLRESP1_ADDR 0x0304 	///../ucode/pctl.h
#define P_UPCTL_DFITRWRLVLRESP1_ADDR 		APB_REG_ADDR(UPCTL_DFITRWRLVLRESP1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLDELAY2_ADDR 0x032c 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLDELAY2_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLDELAY2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRWRLVLRESP2_ADDR 0x0308 	///../ucode/pctl.h
#define P_UPCTL_DFITRWRLVLRESP2_ADDR 		APB_REG_ADDR(UPCTL_DFITRWRLVLRESP2_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLGATEDELAY0_ADDR 0x0330 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLGATEDELAY0_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLGATEDELAY0_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRCMD_ADDR 0x033c 	///../ucode/pctl.h
#define P_UPCTL_DFITRCMD_ADDR 		APB_REG_ADDR(UPCTL_DFITRCMD_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLGATEDELAY1_ADDR 0x0334 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLGATEDELAY1_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLGATEDELAY1_ADDR) 	///../ucode/pctl.h
#define UPCTL_DFITRRDLVLGATEDELAY2_ADDR 0x0338 	///../ucode/pctl.h
#define P_UPCTL_DFITRRDLVLGATEDELAY2_ADDR 		APB_REG_ADDR(UPCTL_DFITRRDLVLGATEDELAY2_ADDR) 	///../ucode/pctl.h
#define UPCTL_IPTR_ADDR 0x03fc 	///../ucode/pctl.h
#define P_UPCTL_IPTR_ADDR 		APB_REG_ADDR(UPCTL_IPTR_ADDR) 	///../ucode/pctl.h
#define UPCTL_IPVR_ADDR 0x03f8 	///../ucode/pctl.h
#define P_UPCTL_IPVR_ADDR 		APB_REG_ADDR(UPCTL_IPVR_ADDR) 	///../ucode/pctl.h
#define PUB_RIDR_ADDR 0x1000 	///../ucode/pctl.h
#define P_PUB_RIDR_ADDR 		APB_REG_ADDR(PUB_RIDR_ADDR) 	///../ucode/pctl.h
#define PUB_PIR_ADDR 0x1004 	///../ucode/pctl.h
#define P_PUB_PIR_ADDR 		APB_REG_ADDR(PUB_PIR_ADDR) 	///../ucode/pctl.h
#define PUB_PGCR_ADDR 0x1008 	///../ucode/pctl.h
#define P_PUB_PGCR_ADDR 		APB_REG_ADDR(PUB_PGCR_ADDR) 	///../ucode/pctl.h
#define PUB_PGSR_ADDR 0x100c 	///../ucode/pctl.h
#define P_PUB_PGSR_ADDR 		APB_REG_ADDR(PUB_PGSR_ADDR) 	///../ucode/pctl.h
#define PUB_DLLGCR_ADDR 0x1010 	///../ucode/pctl.h
#define P_PUB_DLLGCR_ADDR 		APB_REG_ADDR(PUB_DLLGCR_ADDR) 	///../ucode/pctl.h
#define PUB_ACDLLCR_ADDR 0x1014 	///../ucode/pctl.h
#define P_PUB_ACDLLCR_ADDR 		APB_REG_ADDR(PUB_ACDLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_PTR0_ADDR 0x1018 	///../ucode/pctl.h
#define P_PUB_PTR0_ADDR 		APB_REG_ADDR(PUB_PTR0_ADDR) 	///../ucode/pctl.h
#define PUB_PTR1_ADDR 0x101c 	///../ucode/pctl.h
#define P_PUB_PTR1_ADDR 		APB_REG_ADDR(PUB_PTR1_ADDR) 	///../ucode/pctl.h
#define PUB_PTR2_ADDR 0x1020 	///../ucode/pctl.h
#define P_PUB_PTR2_ADDR 		APB_REG_ADDR(PUB_PTR2_ADDR) 	///../ucode/pctl.h
#define PUB_ACIOCR_ADDR 0x1024 	///../ucode/pctl.h
#define P_PUB_ACIOCR_ADDR 		APB_REG_ADDR(PUB_ACIOCR_ADDR) 	///../ucode/pctl.h
#define PUB_DXCCR_ADDR 0x1028 	///../ucode/pctl.h
#define P_PUB_DXCCR_ADDR 		APB_REG_ADDR(PUB_DXCCR_ADDR) 	///../ucode/pctl.h
#define PUB_DSGCR_ADDR 0x102c 	///../ucode/pctl.h
#define P_PUB_DSGCR_ADDR 		APB_REG_ADDR(PUB_DSGCR_ADDR) 	///../ucode/pctl.h
#define PUB_DCR_ADDR 0x1030 	///../ucode/pctl.h
#define P_PUB_DCR_ADDR 		APB_REG_ADDR(PUB_DCR_ADDR) 	///../ucode/pctl.h
#define PUB_DTPR0_ADDR 0x1034 	///../ucode/pctl.h
#define P_PUB_DTPR0_ADDR 		APB_REG_ADDR(PUB_DTPR0_ADDR) 	///../ucode/pctl.h
#define PUB_DTPR1_ADDR 0x1038 	///../ucode/pctl.h
#define P_PUB_DTPR1_ADDR 		APB_REG_ADDR(PUB_DTPR1_ADDR) 	///../ucode/pctl.h
#define PUB_DTPR2_ADDR 0x103c 	///../ucode/pctl.h
#define P_PUB_DTPR2_ADDR 		APB_REG_ADDR(PUB_DTPR2_ADDR) 	///../ucode/pctl.h
#define PUB_MR0_ADDR 0x1040 	///../ucode/pctl.h
#define P_PUB_MR0_ADDR 		APB_REG_ADDR(PUB_MR0_ADDR) 	///../ucode/pctl.h
#define PUB_MR1_ADDR 0x1044 	///../ucode/pctl.h
#define P_PUB_MR1_ADDR 		APB_REG_ADDR(PUB_MR1_ADDR) 	///../ucode/pctl.h
#define PUB_MR2_ADDR 0x1048 	///../ucode/pctl.h
#define P_PUB_MR2_ADDR 		APB_REG_ADDR(PUB_MR2_ADDR) 	///../ucode/pctl.h
#define PUB_MR3_ADDR 0x104c 	///../ucode/pctl.h
#define P_PUB_MR3_ADDR 		APB_REG_ADDR(PUB_MR3_ADDR) 	///../ucode/pctl.h
#define PUB_ODTCR_ADDR 0x1050 	///../ucode/pctl.h
#define P_PUB_ODTCR_ADDR 		APB_REG_ADDR(PUB_ODTCR_ADDR) 	///../ucode/pctl.h
#define PUB_DTAR_ADDR 0x1054 	///../ucode/pctl.h
#define P_PUB_DTAR_ADDR 		APB_REG_ADDR(PUB_DTAR_ADDR) 	///../ucode/pctl.h
#define PUB_DTDR0_ADDR 0x1058 	///../ucode/pctl.h
#define P_PUB_DTDR0_ADDR 		APB_REG_ADDR(PUB_DTDR0_ADDR) 	///../ucode/pctl.h
#define PUB_DTDR1_ADDR 0x105c 	///../ucode/pctl.h
#define P_PUB_DTDR1_ADDR 		APB_REG_ADDR(PUB_DTDR1_ADDR) 	///../ucode/pctl.h
#define PUB_DCUAR_ADDR 0x10c0 	///../ucode/pctl.h
#define P_PUB_DCUAR_ADDR 		APB_REG_ADDR(PUB_DCUAR_ADDR) 	///../ucode/pctl.h
#define PUB_DCUDR_ADDR 0x10c4 	///../ucode/pctl.h
#define P_PUB_DCUDR_ADDR 		APB_REG_ADDR(PUB_DCUDR_ADDR) 	///../ucode/pctl.h
#define PUB_DCURR_ADDR 0x10c8 	///../ucode/pctl.h
#define P_PUB_DCURR_ADDR 		APB_REG_ADDR(PUB_DCURR_ADDR) 	///../ucode/pctl.h
#define PUB_DCULR_ADDR 0x10cc 	///../ucode/pctl.h
#define P_PUB_DCULR_ADDR 		APB_REG_ADDR(PUB_DCULR_ADDR) 	///../ucode/pctl.h
#define PUB_DCUGCR_ADDR 0x10d0 	///../ucode/pctl.h
#define P_PUB_DCUGCR_ADDR 		APB_REG_ADDR(PUB_DCUGCR_ADDR) 	///../ucode/pctl.h
#define PUB_DCUTPR_ADDR 0x10d4 	///../ucode/pctl.h
#define P_PUB_DCUTPR_ADDR 		APB_REG_ADDR(PUB_DCUTPR_ADDR) 	///../ucode/pctl.h
#define PUB_DCUSR0_ADDR 0x10d8 	///../ucode/pctl.h
#define P_PUB_DCUSR0_ADDR 		APB_REG_ADDR(PUB_DCUSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DCUSR1_ADDR 0x10dc 	///../ucode/pctl.h
#define P_PUB_DCUSR1_ADDR 		APB_REG_ADDR(PUB_DCUSR1_ADDR) 	///../ucode/pctl.h
#define PUB_BISTRR_ADDR 0x1100 	///../ucode/pctl.h
#define P_PUB_BISTRR_ADDR 		APB_REG_ADDR(PUB_BISTRR_ADDR) 	///../ucode/pctl.h
#define PUB_BISTMSKR0_ADDR 0x1104 	///../ucode/pctl.h
#define P_PUB_BISTMSKR0_ADDR 		APB_REG_ADDR(PUB_BISTMSKR0_ADDR) 	///../ucode/pctl.h
#define PUB_BISTMSKR1_ADDR 0x1108 	///../ucode/pctl.h
#define P_PUB_BISTMSKR1_ADDR 		APB_REG_ADDR(PUB_BISTMSKR1_ADDR) 	///../ucode/pctl.h
#define PUB_BISTWCR_ADDR 0x110c 	///../ucode/pctl.h
#define P_PUB_BISTWCR_ADDR 		APB_REG_ADDR(PUB_BISTWCR_ADDR) 	///../ucode/pctl.h
#define PUB_BISTLSR_ADDR 0x1110 	///../ucode/pctl.h
#define P_PUB_BISTLSR_ADDR 		APB_REG_ADDR(PUB_BISTLSR_ADDR) 	///../ucode/pctl.h
#define PUB_BISTAR0_ADDR 0x1114 	///../ucode/pctl.h
#define P_PUB_BISTAR0_ADDR 		APB_REG_ADDR(PUB_BISTAR0_ADDR) 	///../ucode/pctl.h
#define PUB_BISTAR1_ADDR 0x1118 	///../ucode/pctl.h
#define P_PUB_BISTAR1_ADDR 		APB_REG_ADDR(PUB_BISTAR1_ADDR) 	///../ucode/pctl.h
#define PUB_BISTAR2_ADDR 0x111c 	///../ucode/pctl.h
#define P_PUB_BISTAR2_ADDR 		APB_REG_ADDR(PUB_BISTAR2_ADDR) 	///../ucode/pctl.h
#define PUB_BISTUDPR_ADDR 0x1120 	///../ucode/pctl.h
#define P_PUB_BISTUDPR_ADDR 		APB_REG_ADDR(PUB_BISTUDPR_ADDR) 	///../ucode/pctl.h
#define PUB_BISTGSR_ADDR 0x1124 	///../ucode/pctl.h
#define P_PUB_BISTGSR_ADDR 		APB_REG_ADDR(PUB_BISTGSR_ADDR) 	///../ucode/pctl.h
#define PUB_BISTWER_ADDR 0x1128 	///../ucode/pctl.h
#define P_PUB_BISTWER_ADDR 		APB_REG_ADDR(PUB_BISTWER_ADDR) 	///../ucode/pctl.h
#define PUB_BISTBER0_ADDR 0x112c 	///../ucode/pctl.h
#define P_PUB_BISTBER0_ADDR 		APB_REG_ADDR(PUB_BISTBER0_ADDR) 	///../ucode/pctl.h
#define PUB_BISTBER1_ADDR 0x1130 	///../ucode/pctl.h
#define P_PUB_BISTBER1_ADDR 		APB_REG_ADDR(PUB_BISTBER1_ADDR) 	///../ucode/pctl.h
#define PUB_BISTBER2_ADDR 0x1134 	///../ucode/pctl.h
#define P_PUB_BISTBER2_ADDR 		APB_REG_ADDR(PUB_BISTBER2_ADDR) 	///../ucode/pctl.h
#define PUB_BISTWCSR_ADDR 0x1138 	///../ucode/pctl.h
#define P_PUB_BISTWCSR_ADDR 		APB_REG_ADDR(PUB_BISTWCSR_ADDR) 	///../ucode/pctl.h
#define PUB_BISTFWR0_ADDR 0x113c 	///../ucode/pctl.h
#define P_PUB_BISTFWR0_ADDR 		APB_REG_ADDR(PUB_BISTFWR0_ADDR) 	///../ucode/pctl.h
#define PUB_BISTFWR1_ADDR 0x1140 	///../ucode/pctl.h
#define P_PUB_BISTFWR1_ADDR 		APB_REG_ADDR(PUB_BISTFWR1_ADDR) 	///../ucode/pctl.h
#define PUB_GPR0_ADDR 0x1178 	///../ucode/pctl.h
#define P_PUB_GPR0_ADDR 		APB_REG_ADDR(PUB_GPR0_ADDR) 	///../ucode/pctl.h
#define PUB_GPR1_ADDR 0x117c 	///../ucode/pctl.h
#define P_PUB_GPR1_ADDR 		APB_REG_ADDR(PUB_GPR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ0CR0_ADDR 0x1180 	///../ucode/pctl.h
#define P_PUB_ZQ0CR0_ADDR 		APB_REG_ADDR(PUB_ZQ0CR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ0CR1_ADDR 0x1184 	///../ucode/pctl.h
#define P_PUB_ZQ0CR1_ADDR 		APB_REG_ADDR(PUB_ZQ0CR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ0SR0_ADDR 0x1188 	///../ucode/pctl.h
#define P_PUB_ZQ0SR0_ADDR 		APB_REG_ADDR(PUB_ZQ0SR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ0SR1_ADDR 0x118c 	///../ucode/pctl.h
#define P_PUB_ZQ0SR1_ADDR 		APB_REG_ADDR(PUB_ZQ0SR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ1CR0_ADDR 0x1190 	///../ucode/pctl.h
#define P_PUB_ZQ1CR0_ADDR 		APB_REG_ADDR(PUB_ZQ1CR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ1CR1_ADDR 0x1194 	///../ucode/pctl.h
#define P_PUB_ZQ1CR1_ADDR 		APB_REG_ADDR(PUB_ZQ1CR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ1SR0_ADDR 0x1198 	///../ucode/pctl.h
#define P_PUB_ZQ1SR0_ADDR 		APB_REG_ADDR(PUB_ZQ1SR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ1SR1_ADDR 0x119c 	///../ucode/pctl.h
#define P_PUB_ZQ1SR1_ADDR 		APB_REG_ADDR(PUB_ZQ1SR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ2CR0_ADDR 0x11a0 	///../ucode/pctl.h
#define P_PUB_ZQ2CR0_ADDR 		APB_REG_ADDR(PUB_ZQ2CR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ2CR1_ADDR 0x11a4 	///../ucode/pctl.h
#define P_PUB_ZQ2CR1_ADDR 		APB_REG_ADDR(PUB_ZQ2CR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ2SR0_ADDR 0x11a8 	///../ucode/pctl.h
#define P_PUB_ZQ2SR0_ADDR 		APB_REG_ADDR(PUB_ZQ2SR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ2SR1_ADDR 0x11ac 	///../ucode/pctl.h
#define P_PUB_ZQ2SR1_ADDR 		APB_REG_ADDR(PUB_ZQ2SR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ3CR0_ADDR 0x11b0 	///../ucode/pctl.h
#define P_PUB_ZQ3CR0_ADDR 		APB_REG_ADDR(PUB_ZQ3CR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ3CR1_ADDR 0x11b4 	///../ucode/pctl.h
#define P_PUB_ZQ3CR1_ADDR 		APB_REG_ADDR(PUB_ZQ3CR1_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ3SR0_ADDR 0x11b8 	///../ucode/pctl.h
#define P_PUB_ZQ3SR0_ADDR 		APB_REG_ADDR(PUB_ZQ3SR0_ADDR) 	///../ucode/pctl.h
#define PUB_ZQ3SR1_ADDR 0x11bc 	///../ucode/pctl.h
#define P_PUB_ZQ3SR1_ADDR 		APB_REG_ADDR(PUB_ZQ3SR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX0GCR_ADDR 0x11c0 	///../ucode/pctl.h
#define P_PUB_DX0GCR_ADDR 		APB_REG_ADDR(PUB_DX0GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX0GSR0_ADDR 0x11c4 	///../ucode/pctl.h
#define P_PUB_DX0GSR0_ADDR 		APB_REG_ADDR(PUB_DX0GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX0GSR1_ADDR 0x11c8 	///../ucode/pctl.h
#define P_PUB_DX0GSR1_ADDR 		APB_REG_ADDR(PUB_DX0GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX0DLLCR_ADDR 0x11cc 	///../ucode/pctl.h
#define P_PUB_DX0DLLCR_ADDR 		APB_REG_ADDR(PUB_DX0DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX0DQTR_ADDR 0x11d0 	///../ucode/pctl.h
#define P_PUB_DX0DQTR_ADDR 		APB_REG_ADDR(PUB_DX0DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX0DQSTR_ADDR 0x11d4 	///../ucode/pctl.h
#define P_PUB_DX0DQSTR_ADDR 		APB_REG_ADDR(PUB_DX0DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX1GCR_ADDR 0x1200 	///../ucode/pctl.h
#define P_PUB_DX1GCR_ADDR 		APB_REG_ADDR(PUB_DX1GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX1GSR0_ADDR 0x1204 	///../ucode/pctl.h
#define P_PUB_DX1GSR0_ADDR 		APB_REG_ADDR(PUB_DX1GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX1GSR1_ADDR 0x1208 	///../ucode/pctl.h
#define P_PUB_DX1GSR1_ADDR 		APB_REG_ADDR(PUB_DX1GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX1DLLCR_ADDR 0x120c 	///../ucode/pctl.h
#define P_PUB_DX1DLLCR_ADDR 		APB_REG_ADDR(PUB_DX1DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX1DQTR_ADDR 0x1210 	///../ucode/pctl.h
#define P_PUB_DX1DQTR_ADDR 		APB_REG_ADDR(PUB_DX1DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX1DQSTR_ADDR 0x1214 	///../ucode/pctl.h
#define P_PUB_DX1DQSTR_ADDR 		APB_REG_ADDR(PUB_DX1DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX2GCR_ADDR 0x1240 	///../ucode/pctl.h
#define P_PUB_DX2GCR_ADDR 		APB_REG_ADDR(PUB_DX2GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX2GSR0_ADDR 0x1244 	///../ucode/pctl.h
#define P_PUB_DX2GSR0_ADDR 		APB_REG_ADDR(PUB_DX2GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX2GSR1_ADDR 0x1248 	///../ucode/pctl.h
#define P_PUB_DX2GSR1_ADDR 		APB_REG_ADDR(PUB_DX2GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX2DLLCR_ADDR 0x124c 	///../ucode/pctl.h
#define P_PUB_DX2DLLCR_ADDR 		APB_REG_ADDR(PUB_DX2DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX2DQTR_ADDR 0x1250 	///../ucode/pctl.h
#define P_PUB_DX2DQTR_ADDR 		APB_REG_ADDR(PUB_DX2DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX2DQSTR_ADDR 0x1254 	///../ucode/pctl.h
#define P_PUB_DX2DQSTR_ADDR 		APB_REG_ADDR(PUB_DX2DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX3GCR_ADDR 0x1280 	///../ucode/pctl.h
#define P_PUB_DX3GCR_ADDR 		APB_REG_ADDR(PUB_DX3GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX3GSR0_ADDR 0x1284 	///../ucode/pctl.h
#define P_PUB_DX3GSR0_ADDR 		APB_REG_ADDR(PUB_DX3GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX3GSR1_ADDR 0x1288 	///../ucode/pctl.h
#define P_PUB_DX3GSR1_ADDR 		APB_REG_ADDR(PUB_DX3GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX3DLLCR_ADDR 0x128c 	///../ucode/pctl.h
#define P_PUB_DX3DLLCR_ADDR 		APB_REG_ADDR(PUB_DX3DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX3DQTR_ADDR 0x1290 	///../ucode/pctl.h
#define P_PUB_DX3DQTR_ADDR 		APB_REG_ADDR(PUB_DX3DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX3DQSTR_ADDR 0x1294 	///../ucode/pctl.h
#define P_PUB_DX3DQSTR_ADDR 		APB_REG_ADDR(PUB_DX3DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX4GCR_ADDR 0x12c0 	///../ucode/pctl.h
#define P_PUB_DX4GCR_ADDR 		APB_REG_ADDR(PUB_DX4GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX4GSR0_ADDR 0x12c4 	///../ucode/pctl.h
#define P_PUB_DX4GSR0_ADDR 		APB_REG_ADDR(PUB_DX4GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX4GSR1_ADDR 0x12c8 	///../ucode/pctl.h
#define P_PUB_DX4GSR1_ADDR 		APB_REG_ADDR(PUB_DX4GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX4DLLCR_ADDR 0x12cc 	///../ucode/pctl.h
#define P_PUB_DX4DLLCR_ADDR 		APB_REG_ADDR(PUB_DX4DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX4DQTR_ADDR 0x12d0 	///../ucode/pctl.h
#define P_PUB_DX4DQTR_ADDR 		APB_REG_ADDR(PUB_DX4DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX4DQSTR_ADDR 0x12d4 	///../ucode/pctl.h
#define P_PUB_DX4DQSTR_ADDR 		APB_REG_ADDR(PUB_DX4DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX5GCR_ADDR 0x1300 	///../ucode/pctl.h
#define P_PUB_DX5GCR_ADDR 		APB_REG_ADDR(PUB_DX5GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX5GSR0_ADDR 0x1304 	///../ucode/pctl.h
#define P_PUB_DX5GSR0_ADDR 		APB_REG_ADDR(PUB_DX5GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX5GSR1_ADDR 0x1308 	///../ucode/pctl.h
#define P_PUB_DX5GSR1_ADDR 		APB_REG_ADDR(PUB_DX5GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX5DLLCR_ADDR 0x130c 	///../ucode/pctl.h
#define P_PUB_DX5DLLCR_ADDR 		APB_REG_ADDR(PUB_DX5DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX5DQTR_ADDR 0x1310 	///../ucode/pctl.h
#define P_PUB_DX5DQTR_ADDR 		APB_REG_ADDR(PUB_DX5DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX5DQSTR_ADDR 0x1314 	///../ucode/pctl.h
#define P_PUB_DX5DQSTR_ADDR 		APB_REG_ADDR(PUB_DX5DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX6GCR_ADDR 0x1340 	///../ucode/pctl.h
#define P_PUB_DX6GCR_ADDR 		APB_REG_ADDR(PUB_DX6GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX6GSR0_ADDR 0x1344 	///../ucode/pctl.h
#define P_PUB_DX6GSR0_ADDR 		APB_REG_ADDR(PUB_DX6GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX6GSR1_ADDR 0x1348 	///../ucode/pctl.h
#define P_PUB_DX6GSR1_ADDR 		APB_REG_ADDR(PUB_DX6GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX6DLLCR_ADDR 0x134c 	///../ucode/pctl.h
#define P_PUB_DX6DLLCR_ADDR 		APB_REG_ADDR(PUB_DX6DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX6DQTR_ADDR 0x1350 	///../ucode/pctl.h
#define P_PUB_DX6DQTR_ADDR 		APB_REG_ADDR(PUB_DX6DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX6DQSTR_ADDR 0x1354 	///../ucode/pctl.h
#define P_PUB_DX6DQSTR_ADDR 		APB_REG_ADDR(PUB_DX6DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX7GCR_ADDR 0x1380 	///../ucode/pctl.h
#define P_PUB_DX7GCR_ADDR 		APB_REG_ADDR(PUB_DX7GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX7GSR0_ADDR 0x1384 	///../ucode/pctl.h
#define P_PUB_DX7GSR0_ADDR 		APB_REG_ADDR(PUB_DX7GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX7GSR1_ADDR 0x1388 	///../ucode/pctl.h
#define P_PUB_DX7GSR1_ADDR 		APB_REG_ADDR(PUB_DX7GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX7DLLCR_ADDR 0x138c 	///../ucode/pctl.h
#define P_PUB_DX7DLLCR_ADDR 		APB_REG_ADDR(PUB_DX7DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX7DQTR_ADDR 0x1390 	///../ucode/pctl.h
#define P_PUB_DX7DQTR_ADDR 		APB_REG_ADDR(PUB_DX7DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX7DQSTR_ADDR 0x1394 	///../ucode/pctl.h
#define P_PUB_DX7DQSTR_ADDR 		APB_REG_ADDR(PUB_DX7DQSTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX8GCR_ADDR 0x13c0 	///../ucode/pctl.h
#define P_PUB_DX8GCR_ADDR 		APB_REG_ADDR(PUB_DX8GCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX8GSR0_ADDR 0x13c4 	///../ucode/pctl.h
#define P_PUB_DX8GSR0_ADDR 		APB_REG_ADDR(PUB_DX8GSR0_ADDR) 	///../ucode/pctl.h
#define PUB_DX8GSR1_ADDR 0x13c8 	///../ucode/pctl.h
#define P_PUB_DX8GSR1_ADDR 		APB_REG_ADDR(PUB_DX8GSR1_ADDR) 	///../ucode/pctl.h
#define PUB_DX8DLLCR_ADDR 0x13cc 	///../ucode/pctl.h
#define P_PUB_DX8DLLCR_ADDR 		APB_REG_ADDR(PUB_DX8DLLCR_ADDR) 	///../ucode/pctl.h
#define PUB_DX8DQTR_ADDR 0x13d0 	///../ucode/pctl.h
#define P_PUB_DX8DQTR_ADDR 		APB_REG_ADDR(PUB_DX8DQTR_ADDR) 	///../ucode/pctl.h
#define PUB_DX8DQSTR_ADDR 0x13d4 	///../ucode/pctl.h
#define P_PUB_DX8DQSTR_ADDR 		APB_REG_ADDR(PUB_DX8DQSTR_ADDR) 	///../ucode/pctl.h
#define MMC_DDR_CTRL 0x6000 	///../ucode/pctl.h
#define P_MMC_DDR_CTRL 		APB_REG_ADDR(MMC_DDR_CTRL) 	///../ucode/pctl.h
#define MMC_ARB_CTRL 0x6008 	///../ucode/pctl.h
#define P_MMC_ARB_CTRL 		APB_REG_ADDR(MMC_ARB_CTRL) 	///../ucode/pctl.h
#define MMC_ARB_CTRL1 0x600c 	///../ucode/pctl.h
#define P_MMC_ARB_CTRL1 		APB_REG_ADDR(MMC_ARB_CTRL1) 	///../ucode/pctl.h
#define MMC_QOS0_CTRL 0x6010 	///../ucode/pctl.h
#define P_MMC_QOS0_CTRL 		APB_REG_ADDR(MMC_QOS0_CTRL) 	///../ucode/pctl.h
#define MMC_QOS0_MAX 0x6014 	///../ucode/pctl.h
#define P_MMC_QOS0_MAX 		APB_REG_ADDR(MMC_QOS0_MAX) 	///../ucode/pctl.h
#define MMC_QOS0_MIN 0x6018 	///../ucode/pctl.h
#define P_MMC_QOS0_MIN 		APB_REG_ADDR(MMC_QOS0_MIN) 	///../ucode/pctl.h
#define MMC_QOS0_LIMIT 0x601c 	///../ucode/pctl.h
#define P_MMC_QOS0_LIMIT 		APB_REG_ADDR(MMC_QOS0_LIMIT) 	///../ucode/pctl.h
#define MMC_QOS0_STOP 0x6020 	///../ucode/pctl.h
#define P_MMC_QOS0_STOP 		APB_REG_ADDR(MMC_QOS0_STOP) 	///../ucode/pctl.h
#define MMC_QOS1_CTRL 0x6024 	///../ucode/pctl.h
#define P_MMC_QOS1_CTRL 		APB_REG_ADDR(MMC_QOS1_CTRL) 	///../ucode/pctl.h
#define MMC_QOS1_MAX 0x6028 	///../ucode/pctl.h
#define P_MMC_QOS1_MAX 		APB_REG_ADDR(MMC_QOS1_MAX) 	///../ucode/pctl.h
#define MMC_QOS1_MIN 0x602c 	///../ucode/pctl.h
#define P_MMC_QOS1_MIN 		APB_REG_ADDR(MMC_QOS1_MIN) 	///../ucode/pctl.h
#define MMC_QOS1_STOP 0x6030 	///../ucode/pctl.h
#define P_MMC_QOS1_STOP 		APB_REG_ADDR(MMC_QOS1_STOP) 	///../ucode/pctl.h
#define MMC_QOS1_LIMIT 0x6034 	///../ucode/pctl.h
#define P_MMC_QOS1_LIMIT 		APB_REG_ADDR(MMC_QOS1_LIMIT) 	///../ucode/pctl.h
#define MMC_QOS2_CTRL 0x6038 	///../ucode/pctl.h
#define P_MMC_QOS2_CTRL 		APB_REG_ADDR(MMC_QOS2_CTRL) 	///../ucode/pctl.h
#define MMC_QOS2_MAX 0x603c 	///../ucode/pctl.h
#define P_MMC_QOS2_MAX 		APB_REG_ADDR(MMC_QOS2_MAX) 	///../ucode/pctl.h
#define MMC_QOS2_MIN 0x6040 	///../ucode/pctl.h
#define P_MMC_QOS2_MIN 		APB_REG_ADDR(MMC_QOS2_MIN) 	///../ucode/pctl.h
#define MMC_QOS2_STOP 0x6044 	///../ucode/pctl.h
#define P_MMC_QOS2_STOP 		APB_REG_ADDR(MMC_QOS2_STOP) 	///../ucode/pctl.h
#define MMC_QOS2_LIMIT 0x6048 	///../ucode/pctl.h
#define P_MMC_QOS2_LIMIT 		APB_REG_ADDR(MMC_QOS2_LIMIT) 	///../ucode/pctl.h
#define MMC_QOS3_CTRL 0x604c 	///../ucode/pctl.h
#define P_MMC_QOS3_CTRL 		APB_REG_ADDR(MMC_QOS3_CTRL) 	///../ucode/pctl.h
#define MMC_QOS3_MAX 0x6050 	///../ucode/pctl.h
#define P_MMC_QOS3_MAX 		APB_REG_ADDR(MMC_QOS3_MAX) 	///../ucode/pctl.h
#define MMC_QOS3_MIN 0x6054 	///../ucode/pctl.h
#define P_MMC_QOS3_MIN 		APB_REG_ADDR(MMC_QOS3_MIN) 	///../ucode/pctl.h
#define MMC_QOS3_STOP 0x6058 	///../ucode/pctl.h
#define P_MMC_QOS3_STOP 		APB_REG_ADDR(MMC_QOS3_STOP) 	///../ucode/pctl.h
#define MMC_QOS3_LIMIT 0x605c 	///../ucode/pctl.h
#define P_MMC_QOS3_LIMIT 		APB_REG_ADDR(MMC_QOS3_LIMIT) 	///../ucode/pctl.h
#define MMC_QOS4_CTRL 0x6060 	///../ucode/pctl.h
#define P_MMC_QOS4_CTRL 		APB_REG_ADDR(MMC_QOS4_CTRL) 	///../ucode/pctl.h
#define MMC_QOS4_MAX 0x6064 	///../ucode/pctl.h
#define P_MMC_QOS4_MAX 		APB_REG_ADDR(MMC_QOS4_MAX) 	///../ucode/pctl.h
#define MMC_QOS4_MIN 0x6068 	///../ucode/pctl.h
#define P_MMC_QOS4_MIN 		APB_REG_ADDR(MMC_QOS4_MIN) 	///../ucode/pctl.h
#define MMC_QOS4_STOP 0x606c 	///../ucode/pctl.h
#define P_MMC_QOS4_STOP 		APB_REG_ADDR(MMC_QOS4_STOP) 	///../ucode/pctl.h
#define MMC_QOS4_LIMIT 0x6070 	///../ucode/pctl.h
#define P_MMC_QOS4_LIMIT 		APB_REG_ADDR(MMC_QOS4_LIMIT) 	///../ucode/pctl.h
#define MMC_QOS5_CTRL 0x6074 	///../ucode/pctl.h
#define P_MMC_QOS5_CTRL 		APB_REG_ADDR(MMC_QOS5_CTRL) 	///../ucode/pctl.h
#define MMC_QOS5_MAX 0x6078 	///../ucode/pctl.h
#define P_MMC_QOS5_MAX 		APB_REG_ADDR(MMC_QOS5_MAX) 	///../ucode/pctl.h
#define MMC_QOS5_MIN 0x607c 	///../ucode/pctl.h
#define P_MMC_QOS5_MIN 		APB_REG_ADDR(MMC_QOS5_MIN) 	///../ucode/pctl.h
#define MMC_QOS5_STOP 0x6080 	///../ucode/pctl.h
#define P_MMC_QOS5_STOP 		APB_REG_ADDR(MMC_QOS5_STOP) 	///../ucode/pctl.h
#define MMC_QOS5_LIMIT 0x6084 	///../ucode/pctl.h
#define P_MMC_QOS5_LIMIT 		APB_REG_ADDR(MMC_QOS5_LIMIT) 	///../ucode/pctl.h
#define MMC_QOS6_CTRL 0x6088 	///../ucode/pctl.h
#define P_MMC_QOS6_CTRL 		APB_REG_ADDR(MMC_QOS6_CTRL) 	///../ucode/pctl.h
#define MMC_QOS6_MAX 0x608c 	///../ucode/pctl.h
#define P_MMC_QOS6_MAX 		APB_REG_ADDR(MMC_QOS6_MAX) 	///../ucode/pctl.h
#define MMC_QOS6_MIN 0x6090 	///../ucode/pctl.h
#define P_MMC_QOS6_MIN 		APB_REG_ADDR(MMC_QOS6_MIN) 	///../ucode/pctl.h
#define MMC_QOS6_STOP 0x6094 	///../ucode/pctl.h
#define P_MMC_QOS6_STOP 		APB_REG_ADDR(MMC_QOS6_STOP) 	///../ucode/pctl.h
#define MMC_QOS6_LIMIT 0x6098 	///../ucode/pctl.h
#define P_MMC_QOS6_LIMIT 		APB_REG_ADDR(MMC_QOS6_LIMIT) 	///../ucode/pctl.h
#define MMC_QOS7_CTRL 0x609c 	///../ucode/pctl.h
#define P_MMC_QOS7_CTRL 		APB_REG_ADDR(MMC_QOS7_CTRL) 	///../ucode/pctl.h
#define MMC_QOS7_MAX 0x60a0 	///../ucode/pctl.h
#define P_MMC_QOS7_MAX 		APB_REG_ADDR(MMC_QOS7_MAX) 	///../ucode/pctl.h
#define MMC_QOS7_MIN 0x60a4 	///../ucode/pctl.h
#define P_MMC_QOS7_MIN 		APB_REG_ADDR(MMC_QOS7_MIN) 	///../ucode/pctl.h
#define MMC_QOS7_STOP 0x60a8 	///../ucode/pctl.h
#define P_MMC_QOS7_STOP 		APB_REG_ADDR(MMC_QOS7_STOP) 	///../ucode/pctl.h
#define MMC_QOS7_LIMIT 0x60ac 	///../ucode/pctl.h
#define P_MMC_QOS7_LIMIT 		APB_REG_ADDR(MMC_QOS7_LIMIT) 	///../ucode/pctl.h
#define MMC_QOSMON_CTRL 0x60b0 	///../ucode/pctl.h
#define P_MMC_QOSMON_CTRL 		APB_REG_ADDR(MMC_QOSMON_CTRL) 	///../ucode/pctl.h
#define MMC_QOSMON_TIM 0x60b4 	///../ucode/pctl.h
#define P_MMC_QOSMON_TIM 		APB_REG_ADDR(MMC_QOSMON_TIM) 	///../ucode/pctl.h
#define MMC_QOSMON_MST 0x60b8 	///../ucode/pctl.h
#define P_MMC_QOSMON_MST 		APB_REG_ADDR(MMC_QOSMON_MST) 	///../ucode/pctl.h
#define MMC_MON_CLKCNT 0x60bc 	///../ucode/pctl.h
#define P_MMC_MON_CLKCNT 		APB_REG_ADDR(MMC_MON_CLKCNT) 	///../ucode/pctl.h
#define MMC_ALL_REQCNT 0x60c0 	///../ucode/pctl.h
#define P_MMC_ALL_REQCNT 		APB_REG_ADDR(MMC_ALL_REQCNT) 	///../ucode/pctl.h
#define MMC_ALL_GANTCNT 0x60c4 	///../ucode/pctl.h
#define P_MMC_ALL_GANTCNT 		APB_REG_ADDR(MMC_ALL_GANTCNT) 	///../ucode/pctl.h
#define MMC_ONE_REQCNT 0x60c8 	///../ucode/pctl.h
#define P_MMC_ONE_REQCNT 		APB_REG_ADDR(MMC_ONE_REQCNT) 	///../ucode/pctl.h
#define MMC_ONE_CYCLE_CNT 0x60cc 	///../ucode/pctl.h
#define P_MMC_ONE_CYCLE_CNT 		APB_REG_ADDR(MMC_ONE_CYCLE_CNT) 	///../ucode/pctl.h
#define MMC_ONE_DATA_CNT 0x60d0 	///../ucode/pctl.h
#define P_MMC_ONE_DATA_CNT 		APB_REG_ADDR(MMC_ONE_DATA_CNT) 	///../ucode/pctl.h
#define DC_CAV_CTRL 0x6300 	///../ucode/pctl.h
#define P_DC_CAV_CTRL 		APB_REG_ADDR(DC_CAV_CTRL) 	///../ucode/pctl.h
#define DC_CAV_LVL3_GRANT 0x6304 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_GRANT 		APB_REG_ADDR(DC_CAV_LVL3_GRANT) 	///../ucode/pctl.h
#define DC_CAV_LVL3_GH 0x6308 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_GH 		APB_REG_ADDR(DC_CAV_LVL3_GH) 	///../ucode/pctl.h
#define DC_CAV_LVL3_FLIP 0x630c 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_FLIP 		APB_REG_ADDR(DC_CAV_LVL3_FLIP) 	///../ucode/pctl.h
#define DC_CAV_LVL3_FH 0x6310 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_FH 		APB_REG_ADDR(DC_CAV_LVL3_FH) 	///../ucode/pctl.h
#define DC_CAV_LVL3_CTRL0 0x6314 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_CTRL0 		APB_REG_ADDR(DC_CAV_LVL3_CTRL0) 	///../ucode/pctl.h
#define DC_CAV_LVL3_CTRL1 0x6318 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_CTRL1 		APB_REG_ADDR(DC_CAV_LVL3_CTRL1) 	///../ucode/pctl.h
#define DC_CAV_LVL3_CTRL2 0x631c 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_CTRL2 		APB_REG_ADDR(DC_CAV_LVL3_CTRL2) 	///../ucode/pctl.h
#define DC_CAV_LVL3_CTRL3 0x6320 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_CTRL3 		APB_REG_ADDR(DC_CAV_LVL3_CTRL3) 	///../ucode/pctl.h
#define DC_CAV_LUT_DATAL 0x6324 	///../ucode/pctl.h
#define P_DC_CAV_LUT_DATAL 		APB_REG_ADDR(DC_CAV_LUT_DATAL) 	///../ucode/pctl.h
#define DC_CAV_LUT_DATAH 0x6328 	///../ucode/pctl.h
#define P_DC_CAV_LUT_DATAH 		APB_REG_ADDR(DC_CAV_LUT_DATAH) 	///../ucode/pctl.h
#define DC_CAV_LUT_ADDR 0x632c 	///../ucode/pctl.h
#define P_DC_CAV_LUT_ADDR 		APB_REG_ADDR(DC_CAV_LUT_ADDR) 	///../ucode/pctl.h
#define DC_CAV_LVL3_MODE 0x6330 	///../ucode/pctl.h
#define P_DC_CAV_LVL3_MODE 		APB_REG_ADDR(DC_CAV_LVL3_MODE) 	///../ucode/pctl.h
#define MMC_PROT_ADDR 0x6334 	///../ucode/pctl.h
#define P_MMC_PROT_ADDR 		APB_REG_ADDR(MMC_PROT_ADDR) 	///../ucode/pctl.h
#define MMC_PROT_SELH 0x6338 	///../ucode/pctl.h
#define P_MMC_PROT_SELH 		APB_REG_ADDR(MMC_PROT_SELH) 	///../ucode/pctl.h
#define MMC_PROT_SELL 0x633c 	///../ucode/pctl.h
#define P_MMC_PROT_SELL 		APB_REG_ADDR(MMC_PROT_SELL) 	///../ucode/pctl.h
#define MMC_PROT_CTL_STS 0x6340 	///../ucode/pctl.h
#define P_MMC_PROT_CTL_STS 		APB_REG_ADDR(MMC_PROT_CTL_STS) 	///../ucode/pctl.h
#define MMC_INT_STS 0x6344 	///../ucode/pctl.h
#define P_MMC_INT_STS 		APB_REG_ADDR(MMC_INT_STS) 	///../ucode/pctl.h
#define MMC_REQ0_CTRL 0x6388 	///../ucode/pctl.h
#define P_MMC_REQ0_CTRL 		APB_REG_ADDR(MMC_REQ0_CTRL) 	///../ucode/pctl.h
#define MMC_REQ1_CTRL 0x638c 	///../ucode/pctl.h
#define P_MMC_REQ1_CTRL 		APB_REG_ADDR(MMC_REQ1_CTRL) 	///../ucode/pctl.h
#define MMC_REQ2_CTRL 0x6390 	///../ucode/pctl.h
#define P_MMC_REQ2_CTRL 		APB_REG_ADDR(MMC_REQ2_CTRL) 	///../ucode/pctl.h
#define MMC_REQ3_CTRL 0x6394 	///../ucode/pctl.h
#define P_MMC_REQ3_CTRL 		APB_REG_ADDR(MMC_REQ3_CTRL) 	///../ucode/pctl.h
#define MMC_REQ4_CTRL 0x6398 	///../ucode/pctl.h
#define P_MMC_REQ4_CTRL 		APB_REG_ADDR(MMC_REQ4_CTRL) 	///../ucode/pctl.h
#define MMC_REQ5_CTRL 0x639c 	///../ucode/pctl.h
#define P_MMC_REQ5_CTRL 		APB_REG_ADDR(MMC_REQ5_CTRL) 	///../ucode/pctl.h
#define MMC_REQ6_CTRL 0x63a0 	///../ucode/pctl.h
#define P_MMC_REQ6_CTRL 		APB_REG_ADDR(MMC_REQ6_CTRL) 	///../ucode/pctl.h
#define MMC_REQ7_CTRL 0x63a4 	///../ucode/pctl.h
#define P_MMC_REQ7_CTRL 		APB_REG_ADDR(MMC_REQ7_CTRL) 	///../ucode/pctl.h
#define MMC_REQ_CTRL 0x6400 	///../ucode/pctl.h
#define P_MMC_REQ_CTRL 		APB_REG_ADDR(MMC_REQ_CTRL) 	///../ucode/pctl.h
#define MMC_SOFT_RST 0x6404 	///../ucode/pctl.h
#define P_MMC_SOFT_RST 		APB_REG_ADDR(MMC_SOFT_RST) 	///../ucode/pctl.h
#define MMC_RST_STS 0x6408 	///../ucode/pctl.h
#define P_MMC_RST_STS 		APB_REG_ADDR(MMC_RST_STS) 	///../ucode/pctl.h
#define MMC_APB3_CTRL 0x640c 	///../ucode/pctl.h
#define P_MMC_APB3_CTRL 		APB_REG_ADDR(MMC_APB3_CTRL) 	///../ucode/pctl.h
#define MMC_CHAN_STS 0x6410 	///../ucode/pctl.h
#define P_MMC_CHAN_STS 		APB_REG_ADDR(MMC_CHAN_STS) 	///../ucode/pctl.h
#define MMC_CLKG_CNTL0 0x6414 	///../ucode/pctl.h
#define P_MMC_CLKG_CNTL0 		APB_REG_ADDR(MMC_CLKG_CNTL0) 	///../ucode/pctl.h
#define MMC_CLKG_CNTL1 0x6418 	///../ucode/pctl.h
#define P_MMC_CLKG_CNTL1 		APB_REG_ADDR(MMC_CLKG_CNTL1) 	///../ucode/pctl.h
#define MMC_CLK_CNTL 0x641c 	///../ucode/pctl.h
#define P_MMC_CLK_CNTL 		APB_REG_ADDR(MMC_CLK_CNTL) 	///../ucode/pctl.h
#define MMC_DDR_PHY_GPR0 0x6420 	///../ucode/pctl.h
#define P_MMC_DDR_PHY_GPR0 		APB_REG_ADDR(MMC_DDR_PHY_GPR0) 	///../ucode/pctl.h
#define MMC_DDR_PHY_GPR1 0x6424 	///../ucode/pctl.h
#define P_MMC_DDR_PHY_GPR1 		APB_REG_ADDR(MMC_DDR_PHY_GPR1) 	///../ucode/pctl.h
#define MMC_LP_CTRL1 0x6428 	///../ucode/pctl.h
#define P_MMC_LP_CTRL1 		APB_REG_ADDR(MMC_LP_CTRL1) 	///../ucode/pctl.h
#define MMC_LP_CTRL2 0x642c 	///../ucode/pctl.h
#define P_MMC_LP_CTRL2 		APB_REG_ADDR(MMC_LP_CTRL2) 	///../ucode/pctl.h
#define MMC_LP_CTRL3 0x6430 	///../ucode/pctl.h
#define P_MMC_LP_CTRL3 		APB_REG_ADDR(MMC_LP_CTRL3) 	///../ucode/pctl.h
#define MMC_PCTL_STAT 0x6434 	///../ucode/pctl.h
#define P_MMC_PCTL_STAT 		APB_REG_ADDR(MMC_PCTL_STAT) 	///../ucode/pctl.h
#define MMC_CMDZQ_CTRL 0x6438 	///../ucode/pctl.h
#define P_MMC_CMDZQ_CTRL 		APB_REG_ADDR(MMC_CMDZQ_CTRL) 	///../ucode/pctl.h
#define STB_VERSION 0x1600 	///../ucode/c_stb_define.h
#define P_STB_VERSION 		CBUS_REG_ADDR(STB_VERSION) 	///../ucode/c_stb_define.h
#define STB_VERSION_2 0x1650 	///../ucode/c_stb_define.h
#define P_STB_VERSION_2 		CBUS_REG_ADDR(STB_VERSION_2) 	///../ucode/c_stb_define.h
#define STB_VERSION_3 0x16a0 	///../ucode/c_stb_define.h
#define P_STB_VERSION_3 		CBUS_REG_ADDR(STB_VERSION_3) 	///../ucode/c_stb_define.h
#define STB_TEST_REG 0x1601 	///../ucode/c_stb_define.h
#define P_STB_TEST_REG 		CBUS_REG_ADDR(STB_TEST_REG) 	///../ucode/c_stb_define.h
#define STB_TEST_REG_2 0x1651 	///../ucode/c_stb_define.h
#define P_STB_TEST_REG_2 		CBUS_REG_ADDR(STB_TEST_REG_2) 	///../ucode/c_stb_define.h
#define STB_TEST_REG_3 0x16a1 	///../ucode/c_stb_define.h
#define P_STB_TEST_REG_3 		CBUS_REG_ADDR(STB_TEST_REG_3) 	///../ucode/c_stb_define.h
#define FEC_INPUT_CONTROL 0x1602 	///../ucode/c_stb_define.h
#define P_FEC_INPUT_CONTROL 		CBUS_REG_ADDR(FEC_INPUT_CONTROL) 	///../ucode/c_stb_define.h
#define FEC_INPUT_CONTROL_2 0x1652 	///../ucode/c_stb_define.h
#define P_FEC_INPUT_CONTROL_2 		CBUS_REG_ADDR(FEC_INPUT_CONTROL_2) 	///../ucode/c_stb_define.h
#define FEC_INPUT_CONTROL_3 0x16a2 	///../ucode/c_stb_define.h
#define P_FEC_INPUT_CONTROL_3 		CBUS_REG_ADDR(FEC_INPUT_CONTROL_3) 	///../ucode/c_stb_define.h
#define FEC_INPUT_DATA 0x1603 	///../ucode/c_stb_define.h
#define P_FEC_INPUT_DATA 		CBUS_REG_ADDR(FEC_INPUT_DATA) 	///../ucode/c_stb_define.h
#define FEC_INPUT_DATA_2 0x1653 	///../ucode/c_stb_define.h
#define P_FEC_INPUT_DATA_2 		CBUS_REG_ADDR(FEC_INPUT_DATA_2) 	///../ucode/c_stb_define.h
#define FEC_INPUT_DATA_3 0x16a3 	///../ucode/c_stb_define.h
#define P_FEC_INPUT_DATA_3 		CBUS_REG_ADDR(FEC_INPUT_DATA_3) 	///../ucode/c_stb_define.h
#define DEMUX_CONTROL 0x1604 	///../ucode/c_stb_define.h
#define P_DEMUX_CONTROL 		CBUS_REG_ADDR(DEMUX_CONTROL) 	///../ucode/c_stb_define.h
#define DEMUX_CONTROL_2 0x1654 	///../ucode/c_stb_define.h
#define P_DEMUX_CONTROL_2 		CBUS_REG_ADDR(DEMUX_CONTROL_2) 	///../ucode/c_stb_define.h
#define DEMUX_CONTROL_3 0x16a4 	///../ucode/c_stb_define.h
#define P_DEMUX_CONTROL_3 		CBUS_REG_ADDR(DEMUX_CONTROL_3) 	///../ucode/c_stb_define.h
#define FEC_SYNC_BYTE 0x1605 	///../ucode/c_stb_define.h
#define P_FEC_SYNC_BYTE 		CBUS_REG_ADDR(FEC_SYNC_BYTE) 	///../ucode/c_stb_define.h
#define FEC_SYNC_BYTE_2 0x1655 	///../ucode/c_stb_define.h
#define P_FEC_SYNC_BYTE_2 		CBUS_REG_ADDR(FEC_SYNC_BYTE_2) 	///../ucode/c_stb_define.h
#define FEC_SYNC_BYTE_3 0x16a5 	///../ucode/c_stb_define.h
#define P_FEC_SYNC_BYTE_3 		CBUS_REG_ADDR(FEC_SYNC_BYTE_3) 	///../ucode/c_stb_define.h
#define FM_WR_DATA 0x1606 	///../ucode/c_stb_define.h
#define P_FM_WR_DATA 		CBUS_REG_ADDR(FM_WR_DATA) 	///../ucode/c_stb_define.h
#define FM_WR_DATA_2 0x1656 	///../ucode/c_stb_define.h
#define P_FM_WR_DATA_2 		CBUS_REG_ADDR(FM_WR_DATA_2) 	///../ucode/c_stb_define.h
#define FM_WR_DATA_3 0x16a6 	///../ucode/c_stb_define.h
#define P_FM_WR_DATA_3 		CBUS_REG_ADDR(FM_WR_DATA_3) 	///../ucode/c_stb_define.h
#define FM_WR_ADDR 0x1607 	///../ucode/c_stb_define.h
#define P_FM_WR_ADDR 		CBUS_REG_ADDR(FM_WR_ADDR) 	///../ucode/c_stb_define.h
#define FM_WR_ADDR_2 0x1657 	///../ucode/c_stb_define.h
#define P_FM_WR_ADDR_2 		CBUS_REG_ADDR(FM_WR_ADDR_2) 	///../ucode/c_stb_define.h
#define FM_WR_ADDR_3 0x16a7 	///../ucode/c_stb_define.h
#define P_FM_WR_ADDR_3 		CBUS_REG_ADDR(FM_WR_ADDR_3) 	///../ucode/c_stb_define.h
#define MAX_FM_COMP_ADDR 0x1608 	///../ucode/c_stb_define.h
#define P_MAX_FM_COMP_ADDR 		CBUS_REG_ADDR(MAX_FM_COMP_ADDR) 	///../ucode/c_stb_define.h
#define MAX_FM_COMP_ADDR_2 0x1658 	///../ucode/c_stb_define.h
#define P_MAX_FM_COMP_ADDR_2 		CBUS_REG_ADDR(MAX_FM_COMP_ADDR_2) 	///../ucode/c_stb_define.h
#define MAX_FM_COMP_ADDR_3 0x16a8 	///../ucode/c_stb_define.h
#define P_MAX_FM_COMP_ADDR_3 		CBUS_REG_ADDR(MAX_FM_COMP_ADDR_3) 	///../ucode/c_stb_define.h
#define TS_HEAD_0 0x1609 	///../ucode/c_stb_define.h
#define P_TS_HEAD_0 		CBUS_REG_ADDR(TS_HEAD_0) 	///../ucode/c_stb_define.h
#define TS_HEAD_0_2 0x1659 	///../ucode/c_stb_define.h
#define P_TS_HEAD_0_2 		CBUS_REG_ADDR(TS_HEAD_0_2) 	///../ucode/c_stb_define.h
#define TS_HEAD_0_3 0x16a9 	///../ucode/c_stb_define.h
#define P_TS_HEAD_0_3 		CBUS_REG_ADDR(TS_HEAD_0_3) 	///../ucode/c_stb_define.h
#define TS_HEAD_1 0x160a 	///../ucode/c_stb_define.h
#define P_TS_HEAD_1 		CBUS_REG_ADDR(TS_HEAD_1) 	///../ucode/c_stb_define.h
#define TS_HEAD_1_2 0x165a 	///../ucode/c_stb_define.h
#define P_TS_HEAD_1_2 		CBUS_REG_ADDR(TS_HEAD_1_2) 	///../ucode/c_stb_define.h
#define TS_HEAD_1_3 0x16aa 	///../ucode/c_stb_define.h
#define P_TS_HEAD_1_3 		CBUS_REG_ADDR(TS_HEAD_1_3) 	///../ucode/c_stb_define.h
#define OM_CMD_STATUS 0x160b 	///../ucode/c_stb_define.h
#define P_OM_CMD_STATUS 		CBUS_REG_ADDR(OM_CMD_STATUS) 	///../ucode/c_stb_define.h
#define OM_CMD_STATUS_2 0x165b 	///../ucode/c_stb_define.h
#define P_OM_CMD_STATUS_2 		CBUS_REG_ADDR(OM_CMD_STATUS_2) 	///../ucode/c_stb_define.h
#define OM_CMD_STATUS_3 0x16ab 	///../ucode/c_stb_define.h
#define P_OM_CMD_STATUS_3 		CBUS_REG_ADDR(OM_CMD_STATUS_3) 	///../ucode/c_stb_define.h
#define OM_CMD_DATA 0x160c 	///../ucode/c_stb_define.h
#define P_OM_CMD_DATA 		CBUS_REG_ADDR(OM_CMD_DATA) 	///../ucode/c_stb_define.h
#define OM_CMD_DATA_2 0x165c 	///../ucode/c_stb_define.h
#define P_OM_CMD_DATA_2 		CBUS_REG_ADDR(OM_CMD_DATA_2) 	///../ucode/c_stb_define.h
#define OM_CMD_DATA_3 0x16ac 	///../ucode/c_stb_define.h
#define P_OM_CMD_DATA_3 		CBUS_REG_ADDR(OM_CMD_DATA_3) 	///../ucode/c_stb_define.h
#define OM_CMD_DATA2 0x160d 	///../ucode/c_stb_define.h
#define P_OM_CMD_DATA2 		CBUS_REG_ADDR(OM_CMD_DATA2) 	///../ucode/c_stb_define.h
#define OM_CMD_DATA2_2 0x165d 	///../ucode/c_stb_define.h
#define P_OM_CMD_DATA2_2 		CBUS_REG_ADDR(OM_CMD_DATA2_2) 	///../ucode/c_stb_define.h
#define OM_CMD_DATA2_3 0x16ad 	///../ucode/c_stb_define.h
#define P_OM_CMD_DATA2_3 		CBUS_REG_ADDR(OM_CMD_DATA2_3) 	///../ucode/c_stb_define.h
#define SEC_BUFF_01_START 0x160e 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_01_START 		CBUS_REG_ADDR(SEC_BUFF_01_START) 	///../ucode/c_stb_define.h
#define SEC_BUFF_01_START_2 0x165e 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_01_START_2 		CBUS_REG_ADDR(SEC_BUFF_01_START_2) 	///../ucode/c_stb_define.h
#define SEC_BUFF_01_START_3 0x16ae 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_01_START_3 		CBUS_REG_ADDR(SEC_BUFF_01_START_3) 	///../ucode/c_stb_define.h
#define SEC_BUFF_23_START 0x160f 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_23_START 		CBUS_REG_ADDR(SEC_BUFF_23_START) 	///../ucode/c_stb_define.h
#define SEC_BUFF_23_START_2 0x165f 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_23_START_2 		CBUS_REG_ADDR(SEC_BUFF_23_START_2) 	///../ucode/c_stb_define.h
#define SEC_BUFF_23_START_3 0x16af 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_23_START_3 		CBUS_REG_ADDR(SEC_BUFF_23_START_3) 	///../ucode/c_stb_define.h
#define SEC_BUFF_SIZE 0x1610 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_SIZE 		CBUS_REG_ADDR(SEC_BUFF_SIZE) 	///../ucode/c_stb_define.h
#define SEC_BUFF_SIZE_2 0x1660 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_SIZE_2 		CBUS_REG_ADDR(SEC_BUFF_SIZE_2) 	///../ucode/c_stb_define.h
#define SEC_BUFF_SIZE_3 0x16b0 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_SIZE_3 		CBUS_REG_ADDR(SEC_BUFF_SIZE_3) 	///../ucode/c_stb_define.h
#define SEC_BUFF_BUSY 0x1611 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_BUSY 		CBUS_REG_ADDR(SEC_BUFF_BUSY) 	///../ucode/c_stb_define.h
#define SEC_BUFF_BUSY_2 0x1661 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_BUSY_2 		CBUS_REG_ADDR(SEC_BUFF_BUSY_2) 	///../ucode/c_stb_define.h
#define SEC_BUFF_BUSY_3 0x16b1 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_BUSY_3 		CBUS_REG_ADDR(SEC_BUFF_BUSY_3) 	///../ucode/c_stb_define.h
#define SEC_BUFF_READY 0x1612 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_READY 		CBUS_REG_ADDR(SEC_BUFF_READY) 	///../ucode/c_stb_define.h
#define SEC_BUFF_READY_2 0x1662 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_READY_2 		CBUS_REG_ADDR(SEC_BUFF_READY_2) 	///../ucode/c_stb_define.h
#define SEC_BUFF_READY_3 0x16b2 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_READY_3 		CBUS_REG_ADDR(SEC_BUFF_READY_3) 	///../ucode/c_stb_define.h
#define SEC_BUFF_NUMBER 0x1613 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_NUMBER 		CBUS_REG_ADDR(SEC_BUFF_NUMBER) 	///../ucode/c_stb_define.h
#define SEC_BUFF_NUMBER_2 0x1663 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_NUMBER_2 		CBUS_REG_ADDR(SEC_BUFF_NUMBER_2) 	///../ucode/c_stb_define.h
#define SEC_BUFF_NUMBER_3 0x16b3 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_NUMBER_3 		CBUS_REG_ADDR(SEC_BUFF_NUMBER_3) 	///../ucode/c_stb_define.h
#define ASSIGN_PID_NUMBER 0x1614 	///../ucode/c_stb_define.h
#define P_ASSIGN_PID_NUMBER 		CBUS_REG_ADDR(ASSIGN_PID_NUMBER) 	///../ucode/c_stb_define.h
#define ASSIGN_PID_NUMBER_2 0x1664 	///../ucode/c_stb_define.h
#define P_ASSIGN_PID_NUMBER_2 		CBUS_REG_ADDR(ASSIGN_PID_NUMBER_2) 	///../ucode/c_stb_define.h
#define ASSIGN_PID_NUMBER_3 0x16b4 	///../ucode/c_stb_define.h
#define P_ASSIGN_PID_NUMBER_3 		CBUS_REG_ADDR(ASSIGN_PID_NUMBER_3) 	///../ucode/c_stb_define.h
#define VIDEO_STREAM_ID 0x1615 	///../ucode/c_stb_define.h
#define P_VIDEO_STREAM_ID 		CBUS_REG_ADDR(VIDEO_STREAM_ID) 	///../ucode/c_stb_define.h
#define VIDEO_STREAM_ID_2 0x1665 	///../ucode/c_stb_define.h
#define P_VIDEO_STREAM_ID_2 		CBUS_REG_ADDR(VIDEO_STREAM_ID_2) 	///../ucode/c_stb_define.h
#define VIDEO_STREAM_ID_3 0x16b5 	///../ucode/c_stb_define.h
#define P_VIDEO_STREAM_ID_3 		CBUS_REG_ADDR(VIDEO_STREAM_ID_3) 	///../ucode/c_stb_define.h
#define AUDIO_STREAM_ID 0x1616 	///../ucode/c_stb_define.h
#define P_AUDIO_STREAM_ID 		CBUS_REG_ADDR(AUDIO_STREAM_ID) 	///../ucode/c_stb_define.h
#define AUDIO_STREAM_ID_2 0x1666 	///../ucode/c_stb_define.h
#define P_AUDIO_STREAM_ID_2 		CBUS_REG_ADDR(AUDIO_STREAM_ID_2) 	///../ucode/c_stb_define.h
#define AUDIO_STREAM_ID_3 0x16b6 	///../ucode/c_stb_define.h
#define P_AUDIO_STREAM_ID_3 		CBUS_REG_ADDR(AUDIO_STREAM_ID_3) 	///../ucode/c_stb_define.h
#define SUB_STREAM_ID 0x1617 	///../ucode/c_stb_define.h
#define P_SUB_STREAM_ID 		CBUS_REG_ADDR(SUB_STREAM_ID) 	///../ucode/c_stb_define.h
#define SUB_STREAM_ID_2 0x1667 	///../ucode/c_stb_define.h
#define P_SUB_STREAM_ID_2 		CBUS_REG_ADDR(SUB_STREAM_ID_2) 	///../ucode/c_stb_define.h
#define SUB_STREAM_ID_3 0x16b7 	///../ucode/c_stb_define.h
#define P_SUB_STREAM_ID_3 		CBUS_REG_ADDR(SUB_STREAM_ID_3) 	///../ucode/c_stb_define.h
#define OTHER_STREAM_ID 0x1618 	///../ucode/c_stb_define.h
#define P_OTHER_STREAM_ID 		CBUS_REG_ADDR(OTHER_STREAM_ID) 	///../ucode/c_stb_define.h
#define OTHER_STREAM_ID_2 0x1668 	///../ucode/c_stb_define.h
#define P_OTHER_STREAM_ID_2 		CBUS_REG_ADDR(OTHER_STREAM_ID_2) 	///../ucode/c_stb_define.h
#define OTHER_STREAM_ID_3 0x16b8 	///../ucode/c_stb_define.h
#define P_OTHER_STREAM_ID_3 		CBUS_REG_ADDR(OTHER_STREAM_ID_3) 	///../ucode/c_stb_define.h
#define PCR90K_CTL 0x1619 	///../ucode/c_stb_define.h
#define P_PCR90K_CTL 		CBUS_REG_ADDR(PCR90K_CTL) 	///../ucode/c_stb_define.h
#define PCR90K_CTL_2 0x1669 	///../ucode/c_stb_define.h
#define P_PCR90K_CTL_2 		CBUS_REG_ADDR(PCR90K_CTL_2) 	///../ucode/c_stb_define.h
#define PCR90K_CTL_3 0x16b9 	///../ucode/c_stb_define.h
#define P_PCR90K_CTL_3 		CBUS_REG_ADDR(PCR90K_CTL_3) 	///../ucode/c_stb_define.h
#define PCR_DEMUX 0x161a 	///../ucode/c_stb_define.h
#define P_PCR_DEMUX 		CBUS_REG_ADDR(PCR_DEMUX) 	///../ucode/c_stb_define.h
#define PCR_DEMUX_2 0x166a 	///../ucode/c_stb_define.h
#define P_PCR_DEMUX_2 		CBUS_REG_ADDR(PCR_DEMUX_2) 	///../ucode/c_stb_define.h
#define PCR_DEMUX_3 0x16ba 	///../ucode/c_stb_define.h
#define P_PCR_DEMUX_3 		CBUS_REG_ADDR(PCR_DEMUX_3) 	///../ucode/c_stb_define.h
#define VIDEO_PTS_DEMUX 0x161b 	///../ucode/c_stb_define.h
#define P_VIDEO_PTS_DEMUX 		CBUS_REG_ADDR(VIDEO_PTS_DEMUX) 	///../ucode/c_stb_define.h
#define VIDEO_PTS_DEMUX_2 0x166b 	///../ucode/c_stb_define.h
#define P_VIDEO_PTS_DEMUX_2 		CBUS_REG_ADDR(VIDEO_PTS_DEMUX_2) 	///../ucode/c_stb_define.h
#define VIDEO_PTS_DEMUX_3 0x16bb 	///../ucode/c_stb_define.h
#define P_VIDEO_PTS_DEMUX_3 		CBUS_REG_ADDR(VIDEO_PTS_DEMUX_3) 	///../ucode/c_stb_define.h
#define VIDEO_DTS_DEMUX 0x161c 	///../ucode/c_stb_define.h
#define P_VIDEO_DTS_DEMUX 		CBUS_REG_ADDR(VIDEO_DTS_DEMUX) 	///../ucode/c_stb_define.h
#define VIDEO_DTS_DEMUX_2 0x166c 	///../ucode/c_stb_define.h
#define P_VIDEO_DTS_DEMUX_2 		CBUS_REG_ADDR(VIDEO_DTS_DEMUX_2) 	///../ucode/c_stb_define.h
#define VIDEO_DTS_DEMUX_3 0x16bc 	///../ucode/c_stb_define.h
#define P_VIDEO_DTS_DEMUX_3 		CBUS_REG_ADDR(VIDEO_DTS_DEMUX_3) 	///../ucode/c_stb_define.h
#define AUDIO_PTS_DEMUX 0x161d 	///../ucode/c_stb_define.h
#define P_AUDIO_PTS_DEMUX 		CBUS_REG_ADDR(AUDIO_PTS_DEMUX) 	///../ucode/c_stb_define.h
#define AUDIO_PTS_DEMUX_2 0x166d 	///../ucode/c_stb_define.h
#define P_AUDIO_PTS_DEMUX_2 		CBUS_REG_ADDR(AUDIO_PTS_DEMUX_2) 	///../ucode/c_stb_define.h
#define AUDIO_PTS_DEMUX_3 0x16bd 	///../ucode/c_stb_define.h
#define P_AUDIO_PTS_DEMUX_3 		CBUS_REG_ADDR(AUDIO_PTS_DEMUX_3) 	///../ucode/c_stb_define.h
#define SUB_PTS_DEMUX 0x161e 	///../ucode/c_stb_define.h
#define P_SUB_PTS_DEMUX 		CBUS_REG_ADDR(SUB_PTS_DEMUX) 	///../ucode/c_stb_define.h
#define SUB_PTS_DEMUX_2 0x166e 	///../ucode/c_stb_define.h
#define P_SUB_PTS_DEMUX_2 		CBUS_REG_ADDR(SUB_PTS_DEMUX_2) 	///../ucode/c_stb_define.h
#define SUB_PTS_DEMUX_3 0x16be 	///../ucode/c_stb_define.h
#define P_SUB_PTS_DEMUX_3 		CBUS_REG_ADDR(SUB_PTS_DEMUX_3) 	///../ucode/c_stb_define.h
#define STB_PTS_DTS_STATUS 0x161f 	///../ucode/c_stb_define.h
#define P_STB_PTS_DTS_STATUS 		CBUS_REG_ADDR(STB_PTS_DTS_STATUS) 	///../ucode/c_stb_define.h
#define STB_PTS_DTS_STATUS_2 0x166f 	///../ucode/c_stb_define.h
#define P_STB_PTS_DTS_STATUS_2 		CBUS_REG_ADDR(STB_PTS_DTS_STATUS_2) 	///../ucode/c_stb_define.h
#define STB_PTS_DTS_STATUS_3 0x16bf 	///../ucode/c_stb_define.h
#define P_STB_PTS_DTS_STATUS_3 		CBUS_REG_ADDR(STB_PTS_DTS_STATUS_3) 	///../ucode/c_stb_define.h
#define STB_DEBUG_INDEX 0x1620 	///../ucode/c_stb_define.h
#define P_STB_DEBUG_INDEX 		CBUS_REG_ADDR(STB_DEBUG_INDEX) 	///../ucode/c_stb_define.h
#define STB_DEBUG_INDEX_2 0x1670 	///../ucode/c_stb_define.h
#define P_STB_DEBUG_INDEX_2 		CBUS_REG_ADDR(STB_DEBUG_INDEX_2) 	///../ucode/c_stb_define.h
#define STB_DEBUG_INDEX_3 0x16c0 	///../ucode/c_stb_define.h
#define P_STB_DEBUG_INDEX_3 		CBUS_REG_ADDR(STB_DEBUG_INDEX_3) 	///../ucode/c_stb_define.h
#define STB_DEBUG_DATAUT_O 0x1621 	///../ucode/c_stb_define.h
#define P_STB_DEBUG_DATAUT_O 		CBUS_REG_ADDR(STB_DEBUG_DATAUT_O) 	///../ucode/c_stb_define.h
#define STB_DEBUG_DATAUT_O_2 0x1671 	///../ucode/c_stb_define.h
#define P_STB_DEBUG_DATAUT_O_2 		CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_2) 	///../ucode/c_stb_define.h
#define STB_DEBUG_DATAUT_O_3 0x16c1 	///../ucode/c_stb_define.h
#define P_STB_DEBUG_DATAUT_O_3 		CBUS_REG_ADDR(STB_DEBUG_DATAUT_O_3) 	///../ucode/c_stb_define.h
#define STBM_CTL_O 0x1622 	///../ucode/c_stb_define.h
#define P_STBM_CTL_O 		CBUS_REG_ADDR(STBM_CTL_O) 	///../ucode/c_stb_define.h
#define STBM_CTL_O_2 0x1672 	///../ucode/c_stb_define.h
#define P_STBM_CTL_O_2 		CBUS_REG_ADDR(STBM_CTL_O_2) 	///../ucode/c_stb_define.h
#define STBM_CTL_O_3 0x16c2 	///../ucode/c_stb_define.h
#define P_STBM_CTL_O_3 		CBUS_REG_ADDR(STBM_CTL_O_3) 	///../ucode/c_stb_define.h
#define STB_INT_STATUS 0x1623 	///../ucode/c_stb_define.h
#define P_STB_INT_STATUS 		CBUS_REG_ADDR(STB_INT_STATUS) 	///../ucode/c_stb_define.h
#define STB_INT_STATUS_2 0x1673 	///../ucode/c_stb_define.h
#define P_STB_INT_STATUS_2 		CBUS_REG_ADDR(STB_INT_STATUS_2) 	///../ucode/c_stb_define.h
#define STB_INT_STATUS_3 0x16c3 	///../ucode/c_stb_define.h
#define P_STB_INT_STATUS_3 		CBUS_REG_ADDR(STB_INT_STATUS_3) 	///../ucode/c_stb_define.h
#define DEMUX_ENDIAN 0x1624 	///../ucode/c_stb_define.h
#define P_DEMUX_ENDIAN 		CBUS_REG_ADDR(DEMUX_ENDIAN) 	///../ucode/c_stb_define.h
#define DEMUX_ENDIAN_2 0x1674 	///../ucode/c_stb_define.h
#define P_DEMUX_ENDIAN_2 		CBUS_REG_ADDR(DEMUX_ENDIAN_2) 	///../ucode/c_stb_define.h
#define DEMUX_ENDIAN_3 0x16c4 	///../ucode/c_stb_define.h
#define P_DEMUX_ENDIAN_3 		CBUS_REG_ADDR(DEMUX_ENDIAN_3) 	///../ucode/c_stb_define.h
#define TS_HIU_CTL 0x1625 	///../ucode/c_stb_define.h
#define P_TS_HIU_CTL 		CBUS_REG_ADDR(TS_HIU_CTL) 	///../ucode/c_stb_define.h
#define TS_HIU_CTL_2 0x1675 	///../ucode/c_stb_define.h
#define P_TS_HIU_CTL_2 		CBUS_REG_ADDR(TS_HIU_CTL_2) 	///../ucode/c_stb_define.h
#define TS_HIU_CTL_3 0x16c5 	///../ucode/c_stb_define.h
#define P_TS_HIU_CTL_3 		CBUS_REG_ADDR(TS_HIU_CTL_3) 	///../ucode/c_stb_define.h
#define SEC_BUFF_BASE 0x1626 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_BASE 		CBUS_REG_ADDR(SEC_BUFF_BASE) 	///../ucode/c_stb_define.h
#define SEC_BUFF_BASE_2 0x1676 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_BASE_2 		CBUS_REG_ADDR(SEC_BUFF_BASE_2) 	///../ucode/c_stb_define.h
#define SEC_BUFF_BASE_3 0x16c6 	///../ucode/c_stb_define.h
#define P_SEC_BUFF_BASE_3 		CBUS_REG_ADDR(SEC_BUFF_BASE_3) 	///../ucode/c_stb_define.h
#define DEMUX_MEM_REQ_EN 0x1627 	///../ucode/c_stb_define.h
#define P_DEMUX_MEM_REQ_EN 		CBUS_REG_ADDR(DEMUX_MEM_REQ_EN) 	///../ucode/c_stb_define.h
#define DEMUX_MEM_REQ_EN_2 0x1677 	///../ucode/c_stb_define.h
#define P_DEMUX_MEM_REQ_EN_2 		CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_2) 	///../ucode/c_stb_define.h
#define DEMUX_MEM_REQ_EN_3 0x16c7 	///../ucode/c_stb_define.h
#define P_DEMUX_MEM_REQ_EN_3 		CBUS_REG_ADDR(DEMUX_MEM_REQ_EN_3) 	///../ucode/c_stb_define.h
#define VIDEO_PDTS_WR_PTR 0x1628 	///../ucode/c_stb_define.h
#define P_VIDEO_PDTS_WR_PTR 		CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR) 	///../ucode/c_stb_define.h
#define VIDEO_PDTS_WR_PTR_2 0x1678 	///../ucode/c_stb_define.h
#define P_VIDEO_PDTS_WR_PTR_2 		CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_2) 	///../ucode/c_stb_define.h
#define VIDEO_PDTS_WR_PTR_3 0x16c8 	///../ucode/c_stb_define.h
#define P_VIDEO_PDTS_WR_PTR_3 		CBUS_REG_ADDR(VIDEO_PDTS_WR_PTR_3) 	///../ucode/c_stb_define.h
#define AUDIO_PDTS_WR_PTR 0x1629 	///../ucode/c_stb_define.h
#define P_AUDIO_PDTS_WR_PTR 		CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR) 	///../ucode/c_stb_define.h
#define AUDIO_PDTS_WR_PTR_2 0x1679 	///../ucode/c_stb_define.h
#define P_AUDIO_PDTS_WR_PTR_2 		CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_2) 	///../ucode/c_stb_define.h
#define AUDIO_PDTS_WR_PTR_3 0x16c9 	///../ucode/c_stb_define.h
#define P_AUDIO_PDTS_WR_PTR_3 		CBUS_REG_ADDR(AUDIO_PDTS_WR_PTR_3) 	///../ucode/c_stb_define.h
#define SUB_WR_PTR 0x162a 	///../ucode/c_stb_define.h
#define P_SUB_WR_PTR 		CBUS_REG_ADDR(SUB_WR_PTR) 	///../ucode/c_stb_define.h
#define SUB_WR_PTR_2 0x167a 	///../ucode/c_stb_define.h
#define P_SUB_WR_PTR_2 		CBUS_REG_ADDR(SUB_WR_PTR_2) 	///../ucode/c_stb_define.h
#define SUB_WR_PTR_3 0x16ca 	///../ucode/c_stb_define.h
#define P_SUB_WR_PTR_3 		CBUS_REG_ADDR(SUB_WR_PTR_3) 	///../ucode/c_stb_define.h
#define SB_START 0x162b 	///../ucode/c_stb_define.h
#define P_SB_START 		CBUS_REG_ADDR(SB_START) 	///../ucode/c_stb_define.h
#define SB_START_2 0x167b 	///../ucode/c_stb_define.h
#define P_SB_START_2 		CBUS_REG_ADDR(SB_START_2) 	///../ucode/c_stb_define.h
#define SB_START_3 0x16cb 	///../ucode/c_stb_define.h
#define P_SB_START_3 		CBUS_REG_ADDR(SB_START_3) 	///../ucode/c_stb_define.h
#define SB_LAST_ADDR 0x162c 	///../ucode/c_stb_define.h
#define P_SB_LAST_ADDR 		CBUS_REG_ADDR(SB_LAST_ADDR) 	///../ucode/c_stb_define.h
#define SB_LAST_ADDR_2 0x167c 	///../ucode/c_stb_define.h
#define P_SB_LAST_ADDR_2 		CBUS_REG_ADDR(SB_LAST_ADDR_2) 	///../ucode/c_stb_define.h
#define SB_LAST_ADDR_3 0x16cc 	///../ucode/c_stb_define.h
#define P_SB_LAST_ADDR_3 		CBUS_REG_ADDR(SB_LAST_ADDR_3) 	///../ucode/c_stb_define.h
#define SB_PES_WR_PTR 0x162d 	///../ucode/c_stb_define.h
#define P_SB_PES_WR_PTR 		CBUS_REG_ADDR(SB_PES_WR_PTR) 	///../ucode/c_stb_define.h
#define SB_PES_WR_PTR_2 0x167d 	///../ucode/c_stb_define.h
#define P_SB_PES_WR_PTR_2 		CBUS_REG_ADDR(SB_PES_WR_PTR_2) 	///../ucode/c_stb_define.h
#define SB_PES_WR_PTR_3 0x16cd 	///../ucode/c_stb_define.h
#define P_SB_PES_WR_PTR_3 		CBUS_REG_ADDR(SB_PES_WR_PTR_3) 	///../ucode/c_stb_define.h
#define OTHER_WR_PTR 0x162e 	///../ucode/c_stb_define.h
#define P_OTHER_WR_PTR 		CBUS_REG_ADDR(OTHER_WR_PTR) 	///../ucode/c_stb_define.h
#define OTHER_WR_PTR_2 0x167e 	///../ucode/c_stb_define.h
#define P_OTHER_WR_PTR_2 		CBUS_REG_ADDR(OTHER_WR_PTR_2) 	///../ucode/c_stb_define.h
#define OTHER_WR_PTR_3 0x16ce 	///../ucode/c_stb_define.h
#define P_OTHER_WR_PTR_3 		CBUS_REG_ADDR(OTHER_WR_PTR_3) 	///../ucode/c_stb_define.h
#define OB_START 0x162f 	///../ucode/c_stb_define.h
#define P_OB_START 		CBUS_REG_ADDR(OB_START) 	///../ucode/c_stb_define.h
#define OB_START_2 0x167f 	///../ucode/c_stb_define.h
#define P_OB_START_2 		CBUS_REG_ADDR(OB_START_2) 	///../ucode/c_stb_define.h
#define OB_START_3 0x16cf 	///../ucode/c_stb_define.h
#define P_OB_START_3 		CBUS_REG_ADDR(OB_START_3) 	///../ucode/c_stb_define.h
#define OB_LAST_ADDR 0x1630 	///../ucode/c_stb_define.h
#define P_OB_LAST_ADDR 		CBUS_REG_ADDR(OB_LAST_ADDR) 	///../ucode/c_stb_define.h
#define OB_LAST_ADDR_2 0x1680 	///../ucode/c_stb_define.h
#define P_OB_LAST_ADDR_2 		CBUS_REG_ADDR(OB_LAST_ADDR_2) 	///../ucode/c_stb_define.h
#define OB_LAST_ADDR_3 0x16d0 	///../ucode/c_stb_define.h
#define P_OB_LAST_ADDR_3 		CBUS_REG_ADDR(OB_LAST_ADDR_3) 	///../ucode/c_stb_define.h
#define OB_PES_WR_PTR 0x1631 	///../ucode/c_stb_define.h
#define P_OB_PES_WR_PTR 		CBUS_REG_ADDR(OB_PES_WR_PTR) 	///../ucode/c_stb_define.h
#define OB_PES_WR_PTR_2 0x1681 	///../ucode/c_stb_define.h
#define P_OB_PES_WR_PTR_2 		CBUS_REG_ADDR(OB_PES_WR_PTR_2) 	///../ucode/c_stb_define.h
#define OB_PES_WR_PTR_3 0x16d1 	///../ucode/c_stb_define.h
#define P_OB_PES_WR_PTR_3 		CBUS_REG_ADDR(OB_PES_WR_PTR_3) 	///../ucode/c_stb_define.h
#define STB_INT_MASK 0x1632 	///../ucode/c_stb_define.h
#define P_STB_INT_MASK 		CBUS_REG_ADDR(STB_INT_MASK) 	///../ucode/c_stb_define.h
#define STB_INT_MASK_2 0x1682 	///../ucode/c_stb_define.h
#define P_STB_INT_MASK_2 		CBUS_REG_ADDR(STB_INT_MASK_2) 	///../ucode/c_stb_define.h
#define STB_INT_MASK_3 0x16d2 	///../ucode/c_stb_define.h
#define P_STB_INT_MASK_3 		CBUS_REG_ADDR(STB_INT_MASK_3) 	///../ucode/c_stb_define.h
#define VIDEO_SPLICING_CTL 0x1633 	///../ucode/c_stb_define.h
#define P_VIDEO_SPLICING_CTL 		CBUS_REG_ADDR(VIDEO_SPLICING_CTL) 	///../ucode/c_stb_define.h
#define VIDEO_SPLICING_CTL_2 0x1683 	///../ucode/c_stb_define.h
#define P_VIDEO_SPLICING_CTL_2 		CBUS_REG_ADDR(VIDEO_SPLICING_CTL_2) 	///../ucode/c_stb_define.h
#define VIDEO_SPLICING_CTL_3 0x16d3 	///../ucode/c_stb_define.h
#define P_VIDEO_SPLICING_CTL_3 		CBUS_REG_ADDR(VIDEO_SPLICING_CTL_3) 	///../ucode/c_stb_define.h
#define AUDIO_SPLICING_CTL 0x1634 	///../ucode/c_stb_define.h
#define P_AUDIO_SPLICING_CTL 		CBUS_REG_ADDR(AUDIO_SPLICING_CTL) 	///../ucode/c_stb_define.h
#define AUDIO_SPLICING_CTL_2 0x1684 	///../ucode/c_stb_define.h
#define P_AUDIO_SPLICING_CTL_2 		CBUS_REG_ADDR(AUDIO_SPLICING_CTL_2) 	///../ucode/c_stb_define.h
#define AUDIO_SPLICING_CTL_3 0x16d4 	///../ucode/c_stb_define.h
#define P_AUDIO_SPLICING_CTL_3 		CBUS_REG_ADDR(AUDIO_SPLICING_CTL_3) 	///../ucode/c_stb_define.h
#define TS_PACKAGE_BYTE_COUNT 0x1635 	///../ucode/c_stb_define.h
#define P_TS_PACKAGE_BYTE_COUNT 		CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT) 	///../ucode/c_stb_define.h
#define TS_PACKAGE_BYTE_COUNT_2 0x1685 	///../ucode/c_stb_define.h
#define P_TS_PACKAGE_BYTE_COUNT_2 		CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_2) 	///../ucode/c_stb_define.h
#define TS_PACKAGE_BYTE_COUNT_3 0x16d5 	///../ucode/c_stb_define.h
#define P_TS_PACKAGE_BYTE_COUNT_3 		CBUS_REG_ADDR(TS_PACKAGE_BYTE_COUNT_3) 	///../ucode/c_stb_define.h
#define PES_STRONG_SYNC 0x1636 	///../ucode/c_stb_define.h
#define P_PES_STRONG_SYNC 		CBUS_REG_ADDR(PES_STRONG_SYNC) 	///../ucode/c_stb_define.h
#define PES_STRONG_SYNC_2 0x1686 	///../ucode/c_stb_define.h
#define P_PES_STRONG_SYNC_2 		CBUS_REG_ADDR(PES_STRONG_SYNC_2) 	///../ucode/c_stb_define.h
#define PES_STRONG_SYNC_3 0x16d6 	///../ucode/c_stb_define.h
#define P_PES_STRONG_SYNC_3 		CBUS_REG_ADDR(PES_STRONG_SYNC_3) 	///../ucode/c_stb_define.h
#define OM_DATA_RD_ADDR 0x1637 	///../ucode/c_stb_define.h
#define P_OM_DATA_RD_ADDR 		CBUS_REG_ADDR(OM_DATA_RD_ADDR) 	///../ucode/c_stb_define.h
#define OM_DATA_RD_ADDR_2 0x1687 	///../ucode/c_stb_define.h
#define P_OM_DATA_RD_ADDR_2 		CBUS_REG_ADDR(OM_DATA_RD_ADDR_2) 	///../ucode/c_stb_define.h
#define OM_DATA_RD_ADDR_3 0x16d7 	///../ucode/c_stb_define.h
#define P_OM_DATA_RD_ADDR_3 		CBUS_REG_ADDR(OM_DATA_RD_ADDR_3) 	///../ucode/c_stb_define.h
#define OM_DATA_RD 0x1638 	///../ucode/c_stb_define.h
#define P_OM_DATA_RD 		CBUS_REG_ADDR(OM_DATA_RD) 	///../ucode/c_stb_define.h
#define OM_DATA_RD_2 0x1688 	///../ucode/c_stb_define.h
#define P_OM_DATA_RD_2 		CBUS_REG_ADDR(OM_DATA_RD_2) 	///../ucode/c_stb_define.h
#define OM_DATA_RD_3 0x16d8 	///../ucode/c_stb_define.h
#define P_OM_DATA_RD_3 		CBUS_REG_ADDR(OM_DATA_RD_3) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_3 0x1639 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_3) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_3_2 0x1689 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_3_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_3_2) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_3_3 0x16d9 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_3_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_3_3) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_2 0x163a 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_2) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_2_2 0x168a 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_2_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_2_2) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_2_3 0x16da 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_2_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_2_3) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_1 0x163b 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_1 		CBUS_REG_ADDR(SECTION_AUTO_STOP_1) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_1_2 0x168b 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_1_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_1_2) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_1_3 0x16db 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_1_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_1_3) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_0 0x163c 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_0 		CBUS_REG_ADDR(SECTION_AUTO_STOP_0) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_0_2 0x168c 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_0_2 		CBUS_REG_ADDR(SECTION_AUTO_STOP_0_2) 	///../ucode/c_stb_define.h
#define SECTION_AUTO_STOP_0_3 0x16dc 	///../ucode/c_stb_define.h
#define P_SECTION_AUTO_STOP_0_3 		CBUS_REG_ADDR(SECTION_AUTO_STOP_0_3) 	///../ucode/c_stb_define.h
#define DEMUX_CHANNEL_RESET 0x163d 	///../ucode/c_stb_define.h
#define P_DEMUX_CHANNEL_RESET 		CBUS_REG_ADDR(DEMUX_CHANNEL_RESET) 	///../ucode/c_stb_define.h
#define DEMUX_CHANNEL_RESET_2 0x168d 	///../ucode/c_stb_define.h
#define P_DEMUX_CHANNEL_RESET_2 		CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_2) 	///../ucode/c_stb_define.h
#define DEMUX_CHANNEL_RESET_3 0x16dd 	///../ucode/c_stb_define.h
#define P_DEMUX_CHANNEL_RESET_3 		CBUS_REG_ADDR(DEMUX_CHANNEL_RESET_3) 	///../ucode/c_stb_define.h
#define DEMUX_SCRAMBLING_STATE 0x163e 	///../ucode/c_stb_define.h
#define P_DEMUX_SCRAMBLING_STATE 		CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE) 	///../ucode/c_stb_define.h
#define DEMUX_SCRAMBLING_STATE_2 0x168e 	///../ucode/c_stb_define.h
#define P_DEMUX_SCRAMBLING_STATE_2 		CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_2) 	///../ucode/c_stb_define.h
#define DEMUX_SCRAMBLING_STATE_3 0x16de 	///../ucode/c_stb_define.h
#define P_DEMUX_SCRAMBLING_STATE_3 		CBUS_REG_ADDR(DEMUX_SCRAMBLING_STATE_3) 	///../ucode/c_stb_define.h
#define DEMUX_CHANNEL_ACTIVITY 0x163f 	///../ucode/c_stb_define.h
#define P_DEMUX_CHANNEL_ACTIVITY 		CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY) 	///../ucode/c_stb_define.h
#define DEMUX_CHANNEL_ACTIVITY_2 0x168f 	///../ucode/c_stb_define.h
#define P_DEMUX_CHANNEL_ACTIVITY_2 		CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_2) 	///../ucode/c_stb_define.h
#define DEMUX_CHANNEL_ACTIVITY_3 0x16df 	///../ucode/c_stb_define.h
#define P_DEMUX_CHANNEL_ACTIVITY_3 		CBUS_REG_ADDR(DEMUX_CHANNEL_ACTIVITY_3) 	///../ucode/c_stb_define.h
#define DEMUX_STAMP_CTL 0x1640 	///../ucode/c_stb_define.h
#define P_DEMUX_STAMP_CTL 		CBUS_REG_ADDR(DEMUX_STAMP_CTL) 	///../ucode/c_stb_define.h
#define DEMUX_STAMP_CTL_2 0x1690 	///../ucode/c_stb_define.h
#define P_DEMUX_STAMP_CTL_2 		CBUS_REG_ADDR(DEMUX_STAMP_CTL_2) 	///../ucode/c_stb_define.h
#define DEMUX_STAMP_CTL_3 0x16e0 	///../ucode/c_stb_define.h
#define P_DEMUX_STAMP_CTL_3 		CBUS_REG_ADDR(DEMUX_STAMP_CTL_3) 	///../ucode/c_stb_define.h
#define DEMUX_VIDEO_STAMP_SYNC_0 0x1641 	///../ucode/c_stb_define.h
#define P_DEMUX_VIDEO_STAMP_SYNC_0 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0) 	///../ucode/c_stb_define.h
#define DEMUX_VIDEO_STAMP_SYNC_0_2 0x1691 	///../ucode/c_stb_define.h
#define P_DEMUX_VIDEO_STAMP_SYNC_0_2 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_2) 	///../ucode/c_stb_define.h
#define DEMUX_VIDEO_STAMP_SYNC_0_3 0x16e1 	///../ucode/c_stb_define.h
#define P_DEMUX_VIDEO_STAMP_SYNC_0_3 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_0_3) 	///../ucode/c_stb_define.h
#define DEMUX_VIDEO_STAMP_SYNC_1 0x1642 	///../ucode/c_stb_define.h
#define P_DEMUX_VIDEO_STAMP_SYNC_1 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1) 	///../ucode/c_stb_define.h
#define DEMUX_VIDEO_STAMP_SYNC_1_2 0x1692 	///../ucode/c_stb_define.h
#define P_DEMUX_VIDEO_STAMP_SYNC_1_2 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_2) 	///../ucode/c_stb_define.h
#define DEMUX_VIDEO_STAMP_SYNC_1_3 0x16e2 	///../ucode/c_stb_define.h
#define P_DEMUX_VIDEO_STAMP_SYNC_1_3 		CBUS_REG_ADDR(DEMUX_VIDEO_STAMP_SYNC_1_3) 	///../ucode/c_stb_define.h
#define DEMUX_AUDIO_STAMP_SYNC_0 0x1643 	///../ucode/c_stb_define.h
#define P_DEMUX_AUDIO_STAMP_SYNC_0 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0) 	///../ucode/c_stb_define.h
#define DEMUX_AUDIO_STAMP_SYNC_0_2 0x1693 	///../ucode/c_stb_define.h
#define P_DEMUX_AUDIO_STAMP_SYNC_0_2 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_2) 	///../ucode/c_stb_define.h
#define DEMUX_AUDIO_STAMP_SYNC_0_3 0x16e3 	///../ucode/c_stb_define.h
#define P_DEMUX_AUDIO_STAMP_SYNC_0_3 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_0_3) 	///../ucode/c_stb_define.h
#define DEMUX_AUDIO_STAMP_SYNC_1 0x1644 	///../ucode/c_stb_define.h
#define P_DEMUX_AUDIO_STAMP_SYNC_1 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1) 	///../ucode/c_stb_define.h
#define DEMUX_AUDIO_STAMP_SYNC_1_2 0x1694 	///../ucode/c_stb_define.h
#define P_DEMUX_AUDIO_STAMP_SYNC_1_2 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_2) 	///../ucode/c_stb_define.h
#define DEMUX_AUDIO_STAMP_SYNC_1_3 0x16e4 	///../ucode/c_stb_define.h
#define P_DEMUX_AUDIO_STAMP_SYNC_1_3 		CBUS_REG_ADDR(DEMUX_AUDIO_STAMP_SYNC_1_3) 	///../ucode/c_stb_define.h
#define DEMUX_SECTION_RESET 0x1645 	///../ucode/c_stb_define.h
#define P_DEMUX_SECTION_RESET 		CBUS_REG_ADDR(DEMUX_SECTION_RESET) 	///../ucode/c_stb_define.h
#define DEMUX_SECTION_RESET_2 0x1695 	///../ucode/c_stb_define.h
#define P_DEMUX_SECTION_RESET_2 		CBUS_REG_ADDR(DEMUX_SECTION_RESET_2) 	///../ucode/c_stb_define.h
#define DEMUX_SECTION_RESET_3 0x16e5 	///../ucode/c_stb_define.h
#define P_DEMUX_SECTION_RESET_3 		CBUS_REG_ADDR(DEMUX_SECTION_RESET_3) 	///../ucode/c_stb_define.h
#define EFUSE_CNTL0 0x0 	///../ucode/secure_apb.h
#define P_EFUSE_CNTL0 		SECBUS_REG_ADDR(EFUSE_CNTL0) 	///../ucode/secure_apb.h
#define EFUSE_CNTL1 0x1 	///../ucode/secure_apb.h
#define P_EFUSE_CNTL1 		SECBUS_REG_ADDR(EFUSE_CNTL1) 	///../ucode/secure_apb.h
#define EFUSE_CNTL2 0x2 	///../ucode/secure_apb.h
#define P_EFUSE_CNTL2 		SECBUS_REG_ADDR(EFUSE_CNTL2) 	///../ucode/secure_apb.h
#define EFUSE_CNTL3 0x3 	///../ucode/secure_apb.h
#define P_EFUSE_CNTL3 		SECBUS_REG_ADDR(EFUSE_CNTL3) 	///../ucode/secure_apb.h
#define EFUSE_CNTL4 0x4 	///../ucode/secure_apb.h
#define P_EFUSE_CNTL4 		SECBUS_REG_ADDR(EFUSE_CNTL4) 	///../ucode/secure_apb.h
#define AO_SECURE_REG0 0x00 	///../ucode/secure_apb.h
#define P_AO_SECURE_REG0 		SECBUS2_REG_ADDR(AO_SECURE_REG0) 	///../ucode/secure_apb.h
#define AO_SECURE_REG1 0x01 	///../ucode/secure_apb.h
#define P_AO_SECURE_REG1 		SECBUS2_REG_ADDR(AO_SECURE_REG1) 	///../ucode/secure_apb.h
#define AO_RTC_ADDR0 0xd0 	///../ucode/secure_apb.h
#define P_AO_RTC_ADDR0 		SECBUS2_REG_ADDR(AO_RTC_ADDR0) 	///../ucode/secure_apb.h
#define AO_RTC_ADDR1 0xd1 	///../ucode/secure_apb.h
#define P_AO_RTC_ADDR1 		SECBUS2_REG_ADDR(AO_RTC_ADDR1) 	///../ucode/secure_apb.h
#define AO_RTC_ADDR2 0xd2 	///../ucode/secure_apb.h
#define P_AO_RTC_ADDR2 		SECBUS2_REG_ADDR(AO_RTC_ADDR2) 	///../ucode/secure_apb.h
#define AO_RTC_ADDR3 0xd3 	///../ucode/secure_apb.h
#define P_AO_RTC_ADDR3 		SECBUS2_REG_ADDR(AO_RTC_ADDR3) 	///../ucode/secure_apb.h
#define AO_RTC_ADDR4 0xd4 	///../ucode/secure_apb.h
#define P_AO_RTC_ADDR4 		SECBUS2_REG_ADDR(AO_RTC_ADDR4) 	///../ucode/secure_apb.h
#define HDMI_ADDR_PORT 0xc8002000 	///../ucode/hdmi.h
#define P_HDMI_ADDR_PORT 		APB_REG_ADDR(HDMI_ADDR_PORT) 	///../ucode/hdmi.h
#define HDMI_DATA_PORT 0xc8002004 	///../ucode/hdmi.h
#define P_HDMI_DATA_PORT 		APB_REG_ADDR(HDMI_DATA_PORT) 	///../ucode/hdmi.h
#define HDMI_CTRL_PORT 0xc8002008 	///../ucode/hdmi.h
#define P_HDMI_CTRL_PORT 		APB_REG_ADDR(HDMI_CTRL_PORT) 	///../ucode/hdmi.h
#endif
